FPGA Fault EmulatorFPGA Fault Emulator

JiJiří Kvasnička, Pavel Kubalík, Hana Kubátováří Kvasnička, Pavel Kubalík, Hana Kubátová

PurposePurpose of FPGA of FPGA FFault ault EmulatorEmulator

Observe the SEU resistance of the design Observe the SEU resistance of the design mapped in FPGA (with regard to the bitstream mapped in FPGA (with regard to the bitstream utilization)utilization)

The SEU is emulated by 1-bit change in the The SEU is emulated by 1-bit change in the bitstreambitstream

Evaluation of Fault Security (FS), Self Testing Evaluation of Fault Security (FS), Self Testing (ST) and Totally Self-Checking (TSC) properties(ST) and Totally Self-Checking (TSC) properties

Evaluation of dependability parameters for Evaluation of dependability parameters for practical applicationpractical application

Hardware RealizationHardware Realization

AT94K40AL FPSLIC (FPGA+AVR)AT94K40AL FPSLIC (FPGA+AVR)Two copies of benchmark present: tested and “golden”Two copies of benchmark present: tested and “golden”Exhaustive test generator and fault class evaluation logicExhaustive test generator and fault class evaluation logicAVR controls the testing and reconfigurationAVR controls the testing and reconfigurationBitstream analysis and area selection are performed in PC.Bitstream analysis and area selection are performed in PC.

FPGA

Tested benchmark

Test generator

Comp

checker

Faultclass logic

AVR

sta

rt

finis

hreconfiguration

Ref. benchmark

cla

ss

SRAM

Commands Results

Used fault classificationUsed fault classification

A: A: Hidden faultHidden fault ( (The result is always OKThe result is always OK))B: B: Detected faultDetected fault ( (wrong result always detected by CEDwrong result always detected by CED))C: C: Undetected faultUndetected fault ( (result is wrong, but never detected result is wrong, but never detected by CED)by CED)D: D: Temporarily detected fault Temporarily detected fault ( (The wrong result is The wrong result is sometimes detected by CED and sometimes is notsometimes detected by CED and sometimes is not))Further Further Fault securityFault security (A(A or or B)B), , Self TestingSelf Testing (B(B or or D)D) and and Totally Self-checkingTotally Self-checking (B)(B) parameters computation parameters computation

Benchmark Checker

Compa-rator

V

U

e (fault)

x

F(x)

Fe(x)

Detectable fault count

Undetectable fault count

ABCD

Codeword

Same vectors

n

m+p

m+pParity predictor

Testing areaTesting area

ResultsResults I I (LUTs) (LUTs)

More hidden faults (A category)More hidden faults (A category)

Other categories are comparableOther categories are comparable

s1488

0

10

20

30

40

50

60

70

80

90

100

A B C D

[%]

HW

SW

ResultsResults II II((LUTs,LUTs,

HW / SWHW / SWcomparisoncomparison))

SW simulation

0%

20%

40%

60%

80%

100%

ALU11 ALU21 ALU31 apla1 b111 br11 s1488 s1494 s27 s386

D

C

B

A

HW

0%

20%

40%

60%

80%

100%

ALU11 ALU21 ALU31 apla1 b111 br11 s1488 s1494 s27 s386

D

C

B

A

Tested bits rangeTested bits range11,0%

29,4%

6,8%23,3%

29,5%

LUT

Cell configuration

Cell to bus conn.

Bus to bus conn.

Others

Presented results: LUT (11% of whole bst)Presented results: LUT (11% of whole bst)

Current progressing state: LUT, Cell Current progressing state: LUT, Cell configuration and Cell connection to Busconfiguration and Cell connection to Bus

Most recent resultMost recent result

0

500

1000

1500

2000

2500

3000

LUT

Inte

rCon

n.

Conn.

0%

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

LUT

Inte

rCon

n.

Conn.

D[%]

C[%]

B[%]

A[%]

Result interpretation problemResult interpretation problem

Different count of fault in SW simulation and HW Different count of fault in SW simulation and HW emulation (comparable?)emulation (comparable?)

Result depends on place&route tool (another Result depends on place&route tool (another way throw mapping gives different results)way throw mapping gives different results)

Inconsistency of a few bits in cell interconnection Inconsistency of a few bits in cell interconnection (sometimes giving different result)(sometimes giving different result)

Testing of complete chip area results in many Testing of complete chip area results in many undetectable faults (it has a relation to the usage undetectable faults (it has a relation to the usage of the FPGA chip) – testing only used bitsof the FPGA chip) – testing only used bits

ConclusionsConclusions

+ Some results from circuit mapped in the + Some results from circuit mapped in the FPGA FPGA

– – FPGA structure and bitstream knowledge FPGA structure and bitstream knowledge requiredrequired

– – Result is affected by place and route Result is affected by place and route processprocess

– – Advantage of testing speedup (with Advantage of testing speedup (with comparison with software simulation) is comparison with software simulation) is degraded by time needed for Place&route degraded by time needed for Place&route and programmingand programming