Fpga 04-verilog-programming

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ENGR. RASHID FARID CHISHTI LECTURER,DEE, FET, IIUI [email protected] WEEK 4 VERILOG PROGRAMMING FPGA Based System Design Sunday, June 12, 2022 1 www.iiu.edu.pk

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Transcript of Fpga 04-verilog-programming

Page 1: Fpga 04-verilog-programming

ENGR. RASHID FARID CHISHTILECTURER,DEE, FET, IIUI

[email protected]

WEEK 4

VERILOG PROGRAMMING

FPGA Based System Design

Saturday, April 15, 2023

1

www.iiu.edu.pk

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A hardware description language is a computer language that is used to describe hardware.

Currently, almost all integrated circuits are designed with using HDL. Two HDLs are widely used Verilog HDL VHDL (Very High Speed Integrated Circuit Hardware

Description Language)Schematic design entry can be replaced by writing HDL

code that CAD tools understand.CAD tools can verify the HDL codes, and create the

circuits automatically from HDL codes.

Hardware Description Language

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We use Verilog, not VHDL for FPGA programming Verilog is more popular in industry than VHDL They offer similar features

History of Verilog In 1980s, originally developed by Gateway Design Automation. In 1990, was put in public domain. In 1995, adopted as an IEEE standard 1364-1995 In 2001, an enhanced version, Verilog 2001

Functions of Verilog Design entry, like schematic Simulation and verification of your design Synthesis

Facts About Verilog

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Verilog may be used to model circuits and behaviors at various levels of abstraction:

Transistor/Switch Level Modeling. LOW LEVEL Gate Level Modeling. Data Flow Modeling. Behavioral or algorithmic Modeling. HIGH LEVEL

For design with FPGA devices, transistor and gate level modeling is not appropriate.

Register Transfer Level (RTL) is a combination of behavioral and dataflow Modeling.

Verilog Usage

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//Define invertermodule my_not(out, in); output out; input in; // declare power // and ground supply1 pwr; supply0 gnd; //instantiate nmos // and pmos switches pmos (out, pwr, in); nmos (out, gnd, in); endmodule

Switch Level Modeling

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// A simple examplemodule gate1 (a,b,c);

input a,b;output c;and (c,a,b);

endmodule Modules are the basic building blocks in Verilog.

A logic circuit module, Its ports: inputs and outputs Begins with module, ends with endmodule

A Simple Verilog Example

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comment line

module nameport list

end module

port declarations

ab

c

gate1

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module eg1 (a,b,c,f);

input a,b,c;

output f;

wire g,h,i;

and (g,a,b);

not (h,b);

and (i,h,c);

or (f,g,i);

endmodule

Gate Level Modeling vs Data Flow Modeling

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// Data Flow Modeling

module ex1 (a,b,c,f); input a,b,c; output f;

assign f = (a&b) | (~b&c); endmodule

// Data Flow Modeling

module ex1 (a,b,c,f); input a,b,c; output f;

assign f = (a&b) | (~b&c); endmodule

a

c

F = AB + B'C

b

fg

ih

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Writing Test Bench

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/* testbench for ex1 block *//* testbench for ex1 block */

modulemodule ex1_tb ; ex1_tb ; wirewire f1; f1; regreg a1, b1, c1; a1, b1, c1; ex1 my_module(a1, b1, c1, f1);ex1 my_module(a1, b1, c1, f1); initialinitial beginbegin $monitor$monitor(($time$time," ", a1, b1, ," ", a1, b1, c1, ," ", f1);c1, ," ", f1); a1 = 1'ba1 = 1'b00; b1 = 1'b; b1 = 1'b11; c1 = 1'b; c1 = 1'b00;; #5#5 a1 = 1'ba1 = 1'b11; b1 = 1'b; b1 = 1'b11; c1 = 1'b; c1 = 1'b11;;

#5#5 a1 = 1'ba1 = 1'b11; b1 = 1'b; b1 = 1'b00; c1 = 1'b; c1 = 1'b11;; #5#5 a1 = 1'ba1 = 1'b11; b1 = 1'b; b1 = 1'b11; c1 = 1'b; c1 = 1'b11;; #10 #10 $finish$finish;; endendendmoduleendmodule

/* testbench for ex1 block *//* testbench for ex1 block */

modulemodule ex1_tb ; ex1_tb ; wirewire f1; f1; regreg a1, b1, c1; a1, b1, c1; ex1 my_module(a1, b1, c1, f1);ex1 my_module(a1, b1, c1, f1); initialinitial beginbegin $monitor$monitor(($time$time," ", a1, b1, ," ", a1, b1, c1, ," ", f1);c1, ," ", f1); a1 = 1'ba1 = 1'b00; b1 = 1'b; b1 = 1'b11; c1 = 1'b; c1 = 1'b00;; #5#5 a1 = 1'ba1 = 1'b11; b1 = 1'b; b1 = 1'b11; c1 = 1'b; c1 = 1'b11;;

#5#5 a1 = 1'ba1 = 1'b11; b1 = 1'b; b1 = 1'b00; c1 = 1'b; c1 = 1'b11;; #5#5 a1 = 1'ba1 = 1'b11; b1 = 1'b; b1 = 1'b11; c1 = 1'b; c1 = 1'b11;; #10 #10 $finish$finish;; endendendmoduleendmodule

module ex1 (a,b,c,f); input a,b,c; output f;

assign f=(a&b)|(!b&c); endmodule

module ex1 (a,b,c,f); input a,b,c; output f;

assign f=(a&b)|(!b&c); endmodule

Each signal in Verilog belongs to either a net or a registerA net (wire) represents a physical wire. Its signal value is determined by its driver. If it is not driven by any driver, its value is high impedance (Z). A register is like a variable in programming languages. It keeps its value until a new value is assigned to it.Unlike registers, nets do not have storage capacity.

Each signal in Verilog belongs to either a net or a registerA net (wire) represents a physical wire. Its signal value is determined by its driver. If it is not driven by any driver, its value is high impedance (Z). A register is like a variable in programming languages. It keeps its value until a new value is assigned to it.Unlike registers, nets do not have storage capacity.

print to a console

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Verilog supports basic logic gates as predefined primitives.There are two classes of basic gates: and/or gates and buf/not gates.And/or gates have one scalar output and multiple scalar inputsThe first terminal in the list of gate terminals is an output and the

other terminals are inputs.

Example 1: Gate Instantiation of And/Or Gateswire OUT, IN1, IN2;

and a1(OUT, IN1, IN2);

xnor (OUT, IN1, IN2);

// More than two inputs;

// 3 input nand gate

nand (OUT, IN1, IN2, IN3);

Basic Gates

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Truth Tables for And/Or Gates

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and 0 1 x z   or 0 1 x z   xor 0 1 x z

0 0 0 0 0   0 0 1 x x   0 0 1 x x

1 0 1 x x   1 1 1 1 1   1 1 0 x x

x 0 x x x   x x 1 x x   x x x x x

z 0 x x x   z x 1 x x   z x x x x

nand 0 1 x z nor 0 1 x z xnor 0 1 x z

0 1 1 1 1 0 1 0 x x 0 1 0 x x

1 1 0 x x 1 0 0 0 0 1 0 1 x x

x 1 x x x x x 0 x x x x x x x

z 1 x x x z x 0 x x z x x x X

1=True , 0=False, X=Unknown, Z=High impedance

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Buf/not gates have one scalar input and one or more scalar outputsThe last terminal in the port list is connected to the input. Other

terminals are connected to the outputsBasic buf/not gate primitives in verilog are buf notBuf/not gates with additional

control signal are

bufif1, notif1, bufif0, notif0

Buf/Not Gates

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buf   not

input output   input output

0 0   0 1

1 1   1 0

x x   x x

z x   z x

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The L and H symbols have a

special meaning. The L symbol

means the output has 0 or z value. The H symbol means the output

has 1 or z value. Any transition to H or L is treated

as a transition to x.

Examples

//Instantiation of bufif gates.

bufif1 b1 (out, in, ctrl);

bufif0 b0 (out, in, ctrl);

//Instantiation of notif gates

notif1 n1 (out, in, ctrl);

notif0 n0 (out, in, ctrl); x={0,1,z} L={0,z} H={1,z}

bufif1Ctrl

 

notif1Ctrl

0 1 x z 

0 1 x z

in

0 z 0 L L 

in

0 z 1 H H

1 z 1 H H 

1 z 0 L L

x z x x x 

x z x x x

z z x x x 

z z x x x

bufif0Ctrl

notif0Ctrl

0 1 x z 0 1 x z

in

0 0 z L L 

in

0 1 z H H

1 1 z H H 

1 0 z L L

x x z x x 

x x z x x

z x z x x 

z x z x x

Truth Table for bufif/notif Gates

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fpga programming

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Fpga 05-verilog-programming

Fpga 05-verilog-programming