for Abundant-DataComputing
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21 st Century NanoSystems for Abundant-Data Computing Stanford University The N3XT 1,000 × Subhasish Mitra Nanotechnology Frontiers at 20 years of NNI Proceedings, December 1, 2020, www.nseresearch.org/2020/
Transcript of for Abundant-DataComputing
21st Century NanoSystems for Abundant-Data Computing
Stanford University
The N3XT 1,000×
Subhasish Mitra
Nanotechnology Frontiers at 20 years of NNIProceedings, December 1, 2020, www.nseresearch.org/2020/
Thanks: Students, Sponsors, Collaborators
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World Relies on Computing
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Edge to Cloud10010101010101010101010101100101001010101010100110101010101010011101001100010101010101100101000111001010010101010110001011101010101010101001101001010101010101010110101001100101011001010101010110100101101010101010100111110011111011101001001011101010110101011010
World Relies on Computing
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Global Grand Challenges100101010101010101010101011001010010101010101001101010101010100111010011000101010101011001010001110010100101010101100010111010101010101010011010010101010101010101101010011001010110
Military ScienceHea1lt0h1C0a1r0e10101010010101010101101G0o0v1e0r1nment
Genomics
Smart Cities
Security
Finance
World Relies on Computing
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Military ScienceHea1lt0h1C0a1r0e10101010010101010101101G0o0v1e0r1nment
AEbdugnedtoanCtldoautda100101010101010101010101011001010010101010101001101010101010
Genomics
Smart Cities
Security
FinanceSTOP
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World Relies on Computing
7US National Academy of Sciences (2011)
Energy × Execution time
Des
ign
8Device
Improve Computing Performance
Abundant-Data Applications
Compute Memory
5%
95%
Memory Wall
Processors, accelerators
Brain-inspired ⊃ Neural Nets
Chip realization ?
•Compute + memory
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•Dense connectivity
•Energy efficiency
Many Walls Simultaneously
Also: interconnect wall, resilience wall, cooling wall …
21.4
10.7
0.5
53
Des
ign
Device11
Few experimental demos
Device ≠ system
Option 1: Better Devices
Des
ign
Multi-core
Few “tricks”
Design complexity
Power / thermal
Device12
Option 2: Design Tricks
Des
ign
Multi-core
Power, thermal
Improve Computing Performance
Device13
Target: 1,000× performance
New innovations required
NanoSystemsNew nanotech
DevicesNew systems
New applicationsNew
architecturesFabrication
a
Sensors
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Computing Today
Compute
Memory
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Dense memoryEfficient logic
Impossible with business as usual
Computation immersed in memoryIncreased
functionalityUltra-dense 3D
N3XT NanoSystems
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Nano-Engineered Computing Systems Technology
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LMC Density Metric
Logic
[DL, DM, DC]
Memory
Connections
[Wong, Proc. IEEE 20] TSMC + MIT + Stanford + UCBerkeley 18
Which Technologies for N3XT ?Many Experts, Many Opinions
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Which Technologies for N3XT ?
Common Answer
My Technology
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MRAM (quick access)
3D Resistive RAM (massive) No TSV
thermal
thermal
thermal
1D CNFET, 2D FET (logic)
Ultra-dense, fine-grained
vias
Silicon compatible
Our N3XT Implementation
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1D CNFET, 2D FET (logic)
1D CNFET, 2D FET (logic)
DARPA 3DSoC Program
Max Shulaker Anantha Chandrakasan
Subhasish Mitra, Boris Murmann, H.-S. Philip Wong, Simon Wong
Brad Ferguson Mark Nelson
Jefford Humes
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Carbon Nanotube FET (CNFET)[Stanford + IMEC + TSMC] [Stanford, MIT]
~ 9× projected benefitEnergy Delay Product (full-design)
100nmPast obstacles: Imperfections
Solution: Imperfection-immune
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Major ProgressFirst CNT computer (Stanford)
[Nature 2013]CNT RISC-V (MIT, Analog Devices)
[Nature 2019]
178 CNFETs: PMOS logic
Single instruction (Turing complete)
1-bit data
14,702 CNFETs: CMOS logicAll RV32E instructions
16-bit data
Stanford Ph.D. student MIT Professor
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Resistive RRAM (RRAM)
Low R High R
Non-volatile system
operation
ResetSet
10-year continuous edge AI
[Stanford + CEA LETI + NTU Singapore + SkyWater] 25
1TnR First multi bits/cell
arrays
10 – 100× on-chip memory
3D Integration
BEOL vias
Sparse 3D
TSV
CNFET
RRAM
Naturally< 400 °C
Dense monolithic 3D Device & arch. benefits
Monolithic 3D
TSV: Through Silicon Via BEOL: Back end of line 26
3D NanoSystem2 Million CNFETs, 1 Mbit RRAM
[Stanford] Nature 2017 27
3D NanoSystem
Memory1 Megabit RRAM
CNTs
X100,000
Ultra-dense vertical connections
Abundant data: Terabytes / secondMillions of sensors
CNT computing logic Classification accelerator
In-situ classification: extensive, accurate28
N3XT Simulation Framework
Explore architecturesEnergy,
exec. time
Physical design, yield, reliability
Heterogeneous nanotechnologies Abundant-
data apps
[Stanford + NTU Singapore] 29
N3XT Simulation Use CasesQuantify Co-explore
Massive N3XT benefits Tech + Arch +App851× 1,971× 210×
Page Rank
Energy
LSTM CNN
Execution Time 5µm 1µm 100nm
8.7×
102×
1,971×
1×
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10×
100× LSTM benefits vs. N3XT via pitch
Lab to Fab
[Stanford, 2017]
Lab3D
NanoSystem
Hyper dimensional
[Stanford + MIT + UC Berkeley, 2018]
[MIT, 2019]
3DImager
FabCommercial silicon foundry
CNFET + RRAM + Monolithic 3D
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[MIT + Stanford + SkyWater]
Conclusion NanoSystems today
Commercial foundry: CNFET + RRAM + monolithic 3D
Game ON, to era
N3XT massive benefits
Existing software, wide range of apps32
