Focus On Structural Test: AC Scan - SiliconAid · PDF fileFocus On Structural Test: AC Scan....

Alfred L. CrouchChief Scientist

Inovys Corporation

[email protected]

Focus On Structural Test:AC Scan

The DFT Equation

The ProblemWhat is Driving Modern Test Technology?

300mm Wafers• Volume Silicon/Test

Deep-Submicron/Nanometer Design• New Failure Modes• Massive Integration

SoC Design• Massive Integration• Reuse Vectors• Time-to-Market

DSM/Nanometer DefectsDSM/Nanometer Defectivity

GOS – in nanometer = no yield

Metal Bridges = mature processes• shorts to VDD/VSS• overdrive/contention connections• leaky connections

In-Line Resistances = nanometer processes• plugged vias• open vias that tunnel• dogbone routes

DSM/Nanometer Design

In DSM design problem focus moved(.5u) Delay moved into route(.35) Clock skew and routing congestion(.25) Power delivery

In nanometer design(180) Faults predominantly in route(130) Background leakage in tens of mA(90) ???

Didn’t go away – they stacked up!!!

DSM/Nanometer Design

In DSM design problem focus moved(.5u) Delay moved into route(.35) Clock skew and routing(.25) Power delivery

In nanometer design(180) Faults predominantly in route(130) Background leakage in tens of mA

Predominant Failure Mode

So What is the Solution?

What is Structural Test?

Use of fault models based on verifying the silicon structure[truth tables, interconnect, power structure, clock structure]

Not Functional Test which is the use of vectorsbased on verifying the behavior or operation of

logical functions

Structural Test and DFT/EDAComment:

Structural test is not new, but has become a more prevalent test solution since it has repeatedly proven to reduce the vector development time as compared to traditional functional vector development.

Higher Fault Coverage, in Less Time, with Less Required System Knowledge!EDA

DFT

StructuralVectors

Tools to createtest logic

and vectors

Methods to addScan, LBIST,

MBIST, Iddq logic

DeterministicVectors for

Stuck, Delay,Bridging, Leakage,

Memory, etc.

Higher FaultCoverage in Less

Time with LessSystem Knowledge

Types of Structural Test

ScanStuck-at/DCDelay/AC

Logic Built-in Self-Test (BIST)STUMPsBILBO

Memory BISTSRAM/DRAMRetention

IddqThresholdDelta-Iddq

Putting AC under the Magnifying Glass

ScanStuck-at/DC

Delay/ACLogic Built-in Self-Test (BIST)

STUMPsBILBO

Memory BISTSRAM/DRAMRetention

IddqThresholdDelta-Iddq

What is Structural Deterministic Test?

ATPG based on fault coverageStuck-At, Transition Delay, Path Delay, Leakage (Iddq)

AB Z00 001 011 110 0

A

BZ

A-S@1B-S@1Z-S@1

A-S@0B-S@0Z-S@0

What is Structural Scan?Organizing flip-flops into scan shift registersProcess is Scan Insertion or Scan Synthesis

Flip-Flops are substituted with Scan Flip-FlopsSDI and SDO scan data paths are connected seriallySE is a global fanout signal similar to a reset or a clock

D Q

Clk

StandardFlip-Flop

SE

SDID Q

ClkSDO

ScanFlip-Flop

Structural Scan ImplementationOrganizing scan chains

Single global scan chain (long skinny scan)Multiple parallel scan chains (short wide scan)Multiple separated by clock domains (scan domains)

10110010101

0000110111011001100110

11100011101

00110011101

11111000001

1110100101000011100111

10000011101

00100010100

What is AC Scan?Using Scan-based techniques to verify timing

Frequency DeterminationI/O TimingDelay Fault

AC Scan is conducting the sample/capture with the correct timing relationship between a state/nextstate (vector pair)

is not shifting at-speed (power, over engineering)is clocked from tester or embedded PLL

Difference Between DC & AC ScanClocking

Why Do AC Scan?AC Scan provides a deterministic AC test that can be used to replace some/all functional vector content

Reduces clocking requirements (shift-slow)

Eases “timing” diagnostics (targeted faults)

Simplifies binning (deterministic/targeted faults)

Vectors are portable (Core-base market)

Vectors generated by ATPG (automated)

Reduces functionality required of tester (cost)

What Does it Take to Do AC Scan?Faults, ATPG support, and Clocks

Transition faults are enumerated by tools

Paths come from Static Timing Analysis

ATPG for AC is supported by all major players

AC Scan waveforms are well understood

Delay AC Faults?Transition Delay/Gate Delay fault model

Faults based on Slow-to-Rise or Slow-to-Fall gates or nets

Transition faults are finite and enumerated by tools• Similar to Stuck-at ATPG but with extra constraint• Uses Stuck-at ATPG engine to generate vectors

• Problem: short path analysis

Delay AC Faults?Path Delay Fault Model

Faults based on Slow-to-Rise or Slow-to-Fall on a complete described path

Path faults can be viewed as a collection of transition faults • Path faults are not finite and not enumerated by tools• Requires Sequential or Multiple-Time-Frame ATPG• Longer runtime and more complex than Stuck-AT

• Problems: false Paths, ATPG Complexity

Focus on AC Scan – Path DelayPath Delay Fault Model

Faults based on Slow-to-Rise or Slow-to-Fall on a complete described path

Path faults can be viewed as a collection of transition faults • Path faults are not finite and not enumerated by tools• Requires Sequential or Multiple-Time-Frame ATPG• Longer runtime and more complex than Stuck-AT

• Problems: false Paths, ATPG Complexity

Clock Sources

InsideOutsideAll around the PLL…

AC Scan and Clocking

Two Methods to ATPG AC Tests:Last-Shift Launch (Skew Load)

Requires Shift-Bit IndependenceCan affect scan routing negativelyCan affect scan design size (dual-element)SE is critical

Two-Sample (Broadside/Functional Justification)Requires ATPG Tool to do most of the workFilters non-boolean true pathsLonger ATPG runtime

AC ATPG: Last Shift

0

1

0

1

10

0

1

1

01

0U21

101

1110

1

stf

No setuphere

0

NoChange

HereTransitionLaunch

The Identified

PathThe

ObserveEndpoint

The Launch

Endpoint

The Cone ofLogic

Off PathValues

IndependentShift-Bits

Last-Shift Scan Operation

SampleCycle

Clk

LastShift

In

FirstShiftOut

0 1Scan Data

0 1 1

SE

Parallel Data0

Launch

Capture

The SE Window

Setup

HoldSetup

Hold

Setup

HoldSetup

Hold

SE Window

OutputValid

SEDependency

StrobeDependency

StrobeOutputs

CLK

SE

Pulse Width

Last ShiftPulse Width

SampleStrobe

At 200 Mhz with 50% Duty-Cycle: the SE WindowCould range from 2ns down to 250ps

AC ATPG: 2-Sample

0-00-0

1-1

1-1

1-1

1-1

1-0

10x

1

1

1

x

x

The IdentifiedPath from STAof gates+routes

The ObserveEndpoint

The Launch

Endpoint

The Path Cone ofLogic

Off PathValues

The LaunchSetup Bits

The Setup Cone ofLogic Supported by

all ATPG toolstoday

ATPG/ATE Clock Limitation

Fast Clock

Slow Clock

One Test Interval One Test Interval

Slow Clock

Fast Clock

This is difficult forATPG and ATE

This isn’t

2-Sample Clocking Example

20ns/50Mhz

5ns

Example shows shift@50Mhz/Sample@200MHz

Raw Clock

Input Clock

Shift Clock

Raw Clock

Launch Clock

Input Clock

Raw Clock

Input Clock

Capture Clock

Raw Clock

Dead Clock

Input Clock

Last Shift Launch/Sample Capture/Sample

Note that SE is not critical with 2-sample

Dead Cycle

Scan Shift Enable

On-Chip Chop-Clock Example

Raw PLL Output

Dead Clock WF

Launch Clock WF

Input Ref Clock

Shift/Capt Clock WF

0 0 0 0

0 0 0 1

1 0 0 0

Dead Clock Counter

Launch Clock Counter

Shift Clock Counter

PLL

0 SClkor

TClk

Edge Select

Negedge Clock

On-Chip Chop-Clock Example

Raw PLL Output

Dead Clock WF

Launch Clock WF

Input Ref Clock

Shift/Capt Clock WF

0 0 0 0

0 0 0 1

1 0 0 0

Dead Clock Counter

Launch Clock Counter

Shift Clock Counter

PLL

0 SClkor

TClk

Edge Select

Negedge Clock

1 1 1 01

0

Edge Select

Cross Domain Path Delay Rules

Slow Speed FF

SlowSpeedLogic

HighSpeedLogic

High Speed FF

SlowSpeedLogic

HighSpeedLogic

FClk

SClk

SE

Launch On 1st

Sample

Capture On 2nd

Sample

SClk FClk

Slow Shiftand At-Speed

Capture


Slow Speed FF

SlowSpeedLogic

HighSpeedLogic

High Speed FF

SlowSpeedLogic

HighSpeedLogic

FClk

SClk

SE

Launch On 1st

Sample

Capture On 2nd

Sample

SClk FClk

Slow-to-Fast

Thru FastLogic


Slow Speed FF

SlowSpeedLogic

HighSpeedLogic

High Speed FF

SlowSpeedLogic

HighSpeedLogic

FClk

SClk

SE

Launch On 1st

Sample

Capture On 2nd

Sample

SClk FClk

Slow-to-Fast

Thru SlowLogic


Slow Speed FF

SlowSpeedLogic

HighSpeedLogic

High Speed FF

SlowSpeedLogic

HighSpeedLogic

FClk

SClk

SE

Launch On 1st

Sample

Capture On 2nd

Sample

SClk FClk

Fast-to-Slow

Thru FastLogic


Slow Speed FF

SlowSpeedLogic

HighSpeedLogic

High Speed FF

SlowSpeedLogic

HighSpeedLogic

FClk

SClk

SE

Launch On 1st

Sample

Capture On 2nd

Sample

SClk FClk

Fast-to-Slow

Thru SlowLogic

Let’s Collect Some Information…

All About PathsFollow the White Rabbit…

Path Delay testing is all about the Paths you Pick

What is a path?What do paths look like?Where do paths come from?How are paths used?What are the best paths to use?How many paths should be used? Are there any wrong paths?

What is a Path?Down the Rabbit Hole and into Wonderland…

Path Definition:

a boolean true path for synthesis and ATPG is a real propagation path that begins on a pin or sequential device, passes through gates and nets, and ends on a pin or sequential device.

What is a False Path?There are 2 types of False Paths

Boolean False Path:a path that is a collection of gates and net connections that cannot be exercised in functional or test mode.

Functional False Path: a path that can be exercised and resolved in a test mode, but cannot be exercised in functional mode.

What is an Incomplete Path?You Can’t Get There From Here…

The Incomplete Path:a non-contiguous description of gates and nets.

Or an inaccurate description of gates and nets.

Why?Custom circuit blocksDifferent netlists for different tools

What Does a Path Look Like?

U21

U37

U46

U6

U3 U74

U18 U55U11

Identified CriticalPath from

Static TimingAnalysis

Pins or Registers

Pin orRegister

Endpoint

A Boolean true path for synthesis and ATPGis a real propagation path that begins on a

pin/sequential device, passes through gates and nets,and ends on a pin/sequential device that is called

an Endpoint.

What Does a Path Look Like?Path R2RCoreA001 =Pin Top/CoreA/Mul/AdjReg/q;Pin Top/CoreA/Mul/U37/a;Pin Top/CoreA/Mul/U37/x;Pin Top/CoreA/Mul/U6/a;Pin Top/CoreA/Mul/U6/x;Pin Top/CoreA/Pipe/U11/b;Pin Top/CoreA/Pipe/U11/z;Pin Top/CoreA/Pipe/U18/b;Pin Top/CoreA/Pipe/U18/x;Pin Top/CoreA/Pipe/U55/a;Pin Top/CoreA/Pipe/U55/x;Pin Top/CoreA/ALUReg/d;End R2RCoreA001;

A Path Filefor

ATPG

Path Name


A Path Filefor

ATPG

Pin or Register


A Path Filefor

ATPGGate Input


A Path Filefor

ATPG Gate Output


A Path Filefor

ATPG A number of Gates


A Path Filefor

ATPG

Pin or Register

What Does a False Path Look Like?

U21

U37 U6

U74

U18U11

U7

U3

Static Timing Analysiswill ID path A whichcannot be true dueto mutual exclusive

MUX select

0

0

1

1

U3

B

A

Where Do Paths Come From?It’s about the Choices We Make…

In a Word – Static Timing Analysis:the synthesis tool must assess paths to determine if the circuit can make timing.

Paths are based on Registers to ease the definition of timing and the work function of the synthesis tool.

There may be a finite number of nets and gates in a design, but the combination of nets and gates can add up to trillions of paths.

Early design is based on wireload – End design on parasitics

How are Paths Used?Can I Eat with the Fork in the Road?…

In a Word – Vector Generation:the path represents a collection of transition delay or gate delay faults that are to be assessed simultaneously. They are used as a Path Fault description for ATPG tools.

A Vector is created that passes a transition down the complete path within one defined time period – usually one clock cycle.

Paths and ATPGSet Fault Type Path

Set System Mode ATPG

Set Abort Limit 200 200

Set Simulation Mode Combinational Depth -2

Load Paths <filename>

Add Faults –All

Run

A Run Filefor

ATPG

What are the Best Paths to Use?Don’t be Critical until You’ve Walked a Mile in Someone Elses Shoes…

Critical Paths – the Only Paths to Use

Why Critical paths? How Critical is Critical?Only a few trillion paths?What is Path Fault Coverage?

What are the Best Paths to Use?Critical Path Facts:

Critical Paths are more sensitive to timing

One worst path per endpoint proves frequency

Multiple paths per endpoint to identify delay faults

Criticality depends on several factors• Library Performance• Synthesis/Timing target• Delay Fault sizing

Only a portion of the available paths are needed for complete Path Fault Coverage

Black Magic Zone

Which Paths to Use?Endpoints

Mor

e C

ritic

al

LeastSlack

MostSlack

Flip-Flop or POwith least

Timing Margin

Flip-Flop or POwith most

Timing Margin

Endpoints presentedin Static Timing Analysis

Order


PathsMore Critical

Mor

e C

ritic

al

Paths organizedby

Slack Value

LeastSlack

MostSlack

There are multiplepaths behind each

endpointThis Box of Dotscould representtrillions of paths


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

Establish aTiming Criteria

Examples:5% of the Cycle<2ns of Slack

Size of a Defect

It’s All AboutManaging the

Number of Vectors


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At

Stuck and TransitionFaults are finite whole

space models andappear as sensitivityranges in the graph


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At

Path Delay Faultsare targeted faultsand the limit is set

by the user orcost requirements


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At

Mostly False Mostly True

Real Frequency Line


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At


We knowthis Timing

It matchesthis timing


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At


Anything Matchingthe TDelay timingcan be moved intothe TDelay space


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At


Also Fallsinto TD Space


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At


Path FaultCoverage

Area


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At


Coverage israted in delaynot percent

Path DistributionEndpoints

PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

A High PerformanceChip with Few GatesBetween Registers

The Path Depth isMinimal

Height is Tall


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

Path Depth isMaximal

A Chip with a DeepCombinational Depth


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

Designing a 30MHzChip in a 300MHz library

No Paths are Critical

Stuck-At


PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

Designing a 310MHzChip in a 300MHz libraryAll Paths are Critical

TransitionDelay

How a Human Does Path-Based ATPG

Vectors

Lots of PathsVector Status

ATPG Static TimingAnalysis

• Netlist• Library• Constraints• Setup

PathsGet Lots of Paths

• Netlist• Library• Wireload• Constraints

Boy,this is a lotof work!!!

Get 1000s of Paths

Lots More PathsMore Vector Status

4 Vectors

Which Paths I Got!!Endpoints

PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At


MostlyStuck-At

Which Paths I Want!!Endpoints

PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-At


TheCriticalPaths

How to Automate Path-Based ATPG

VectorsPaths

PathMath

Endpoint + Next

Path Description

Path FaultVector Status

• End Point Rules• Socket Control• Path Translate• Analysis Enable

False PathAnalysis

Analyze if ATPG-Untestable


Difference is that theprocess goes afterone path at a timewith one endpoint ata time – and so farmsthe critical path space

Man,I’m going to

Disney World!

Hmm, Now Where Did I Leave Those Defects?

The Problem Re-Stated

The Net RatingLayout Extraction: What information should be extracted from layout to assist in the vector generation, detection, and diagnostic/debug processes?

Bridging RulesVia RulesFanout and Wire-Length

Rating the Net: How can this information be compiled and viewed to provide the most value and assistance?

A Bridge Too Far

Example Bridging Rules: Assign a value for each rule violation associated with a given net:

+1 for each L-Bend+1 for Length > Target+1 for Mutual Capacitance > Target

Sum: Store this sum as a variable known as BR.

We’ll Cross that Via if it Comes to it

Example Via Rules: Assign a value for each rule violation associated with a given net.

+1 for each Via Crossing+1 for Complex Vias+1 for Metal Sizing Change+1 for each Metal Level

Sum: Store this sum as a variable known as VI.

When the Shift Hits the Fanout

Fanout Rules: Assign a value for each rule violation associated with a given net.

+1 for each load+1 for each stem branching

Sum: Store this value as a variable known as FA.

And the Total is…

The Math: Add the numbers together with weighting factors to allow tailoring to specific fabsand processes.

Sum: = δ1 BR + δ2 VI + δ3 FA

Representation as a Quadlet: (BR, VI, FA, Tot)

Now What Do I Do With This?

Let’s Get Physical

DSM and nanometer design: GOS, Metal Bridges, Open/Plugged Vias dominate. 60% of the defectivity is in the route and causes delay.

Bridges: Leakage, contention, shorts, resistive connections, diodic connections.

In-Line Resistances: No leakage, small opens, tunneling, stringers, and bone connections.

What’s the Rub?

Crosstalk: High mutual capacitance. Interference with the boolean propagation value.

Power Droop: High toggle or undersized power rails. Loss of state (brownout).

Clock Droop: Weak clock tree, power droop. Hold-time violations (data smearing), period expansion.

The AC Scan Recipefor Physical Debug

STA: Critical (timing sensitive) paths must be identified from Static Timing Analysis.

Layout: Potential Bridging and Via fault locations must be extracted from the Layout.

ATPG: AC Scan vectors must be generated to target Bridge and Via faults.

Failure Mode: The defect manifests itself as an interaction that causes an AC Scan vector to fail timing.

Bridging Debug with AC Scan

U74U74 is in identified

Critical Pathfrom

Static TimingAnalysis

20ns/50Mhz

Launch Capture/Sample

Capture Clock

20ns/50Mhz

Launch Clock


U74 0->1

NormalPath Delay

Test onNode U74

PASS1

0->1

20ns/50Mhz


Capture Clock

20ns/50Mhz

Launch Clock

10ns


20ns/50Mhz

Launch Clock Capture Clock


U74

U18 Let’s Adda Suspected

Bridging Fault

Must Identifythe Suspect

Bridging Nodefrom Layout

20ns/50Mhz

1

0->1


20ns/50Mhz



U74


Bridging Fault

Node Must beIndependent

and not directlyAffect Test

20ns/50Mhz

1

0->1

I


20ns/50Mhz



U74


Bridging Fault

Suspect Nodeis now calleda Constrained

Node20ns/50Mhz

1

0->1


20ns

20ns/50Mhz



Suspect NodeConstrained

to 1

PASS

U74

U18

0->1

1

1

0->1

20ns/50Mhz


15ns

20ns/50Mhz




to 1

PASS

U74

U18

0->1

1

1

0->1

20ns/50Mhz


10ns

20ns/50Mhz




to 1

PASS

U74

U18

0->1

1

1

0->1

20ns/50Mhz


20ns/50Mhz




to 15ns

F

FAIL

U74

U18

0->1

1

1

0->1

20ns/50Mhz


20ns/50Mhz



Log theCaptureTiming

5ns

F

FAIL

U74

U18

0->1

1

1

0->1

20ns/50Mhz


20ns/50Mhz



Now Let’sChange

the Constraint

U74

U18

1

0->1

20ns/50Mhz


20ns

20ns/50Mhz




to 0

PASS

U74

U18

0->1

0

1

0->1

20ns/50Mhz


15ns

20ns/50Mhz




to 0

PASS

U74

U18

0->1

0

1

0->1

20ns/50Mhz


20ns/50Mhz




to 010ns

F

FAIL

U74

U18

0->1

0

1

0->1

20ns/50Mhz


20ns/50Mhz



Log theCaptureTiming

10ns

F

FAIL

U74

U18

0->1

0

1

0->1

20ns/50Mhz


20ns/50Mhz



Note theTiming

Difference10ns

F5ns

F

FAIL

Since the same test failed at 2different timings with only theconstraint being different, then

there is an interaction

U74

U18

0->1

1/0

1

0->1

20ns/50MhzPotential Bridgeor

Crosstalk

Bridging Explained (1)Critical Paths: the more critical the path, the more sensitive it is to timing – find the most critical path that contains the suspected bridge.

Independence: the constrain node can have no direct bearing on the outcome of the test in a fault-free circuit – it cannot re-converge into the exercise or observe part of the path. It may be necessary to select a less critical path to meet this condition.

Murphy: a highly resistive bridge may exist and may not fail the test. Use leakage testing as an additional clue.

Bridging Explained (2)

More Clues: Repeat the test using the constrained node for the path delay transition and hold the path delay node to the constrain values – this works best if the constrained node can also be associated with a critical path.

Layout Rules: nets with 90 degree bends, high mutual capacitance, and long routes or high fanoutare good candidates.

In-Line Resistance Debug with AC Scan

U74

Begin with a RouteNode in a Critical Path

Identify a problem either throughLayout Extraction or from a FailedTest that was Traced to the Gate


U74

U18

Investigate theSuspected Path

fromSTA


U74

via

U18Extract the Point-to-PointNet from Layout

Note from Path Filethe Primary Endpoint

(Observe Point)Identify Structures

Such as Vias

D Q


U74

via

U18Extract the Point-to-PointNet from Layout I

Assign the Pathto be Independent


U74

via

SuspectOpen Via

U18I


U74

via

U18I


U74

via

U18I

Extract WholeNet fromLayout

OtherLogic


U74

via

U18I

ForwardFanout

Analysis

Forward TraceOther Stemsthrough theirLogic to their

Observe Points

Note theirEndpoints

OtherLogic


U74

via

U18I

…and AssignDependence

and Independence

I

D

II

ID

Only Independentnets are Valid

for Consideration

OtherLogic


U74

via

U18I

I

D

II

ID

Create MultiplePath Faultsfor ATPG

Each IndependentNet becomes aPath Delay Test

OtherLogic


U74

via

U18I

I

D

II

ID


0->1

ApplyTransition

OtherLogic


U74

via

U18I

I

D

II

ID


0->1

ApplyTransition

PASS

PASSPASS

PASS

FAILIf Some Fail

and Some Passthen this Isolatesto the Net Stem

In-Line Resistance Explained (1)Critical Paths: the more critical the path, the more sensitive it is to timing – find the most critical path that contains the suspected resistance.

Independence: the fanout stems must be independent of each other and not re-convergent to themselves.

Fanout: this technique only works with nets that have fanoutto multiple endpoints. It does not work with single-connection nets, or with nets that have fanout that is all re-convergent.

In-Line Resistance Explained (2)More Paths: Some nets feed logic that has fanout further forward in the cone of logic and the net may resolve to multiple endpoints. Create multiple PDelay vectors for those nets.

More Clues: in-line resistances do not exhibit leakage current.

Layout Rules: nets with multiple via crossings, complex vias, long routes and high fanout are good candidates.

Putting it all TogetherGenerating More Comprehensive Vectors:Couple Layout Extraction, Static Timing Analysis, and AC Scan to produce vectors that have a higher probability of detecting Bridges, Opens, and other delay causing defects.

Conducting Debug: Coupling Layout Extraction and Static Timing Analysis to help steer AC Scan vector generation for isolation (location) or resolution (type of defect).

Putting It All TogetherEndpoints

PathsMore Critical

Mor

e C

ritic

al

LeastSlack

MostSlack

PathDelay

TransitionDelay

Stuck-AtMore Criti

cal

Match nodes andnets to more criticalpaths in target box

Putting it All Together

VectorsPaths

PhysicalPathMath

Endpoint + Next

Path Description

Path FaultVector Status

False PathAnalysis

Analyze if ATPG-Untestable


• End Point Rules• Socket Control• Path Translate• Analysis Enable

• End Point Rules• Socket Control• Path Translate• Analysis Enable• Path Filter

Net/GateRating

Nets and Gates

LayoutExtraction

Path Description

Any Questions

Summary & Conclusions

AC Scan is a Structural Test Technique: it is proven, automated, more economical, and can be used to debug and diagnose nanometer designs.

AC Scan is almost identical to DC Scan: in implementation the only difference is the clocking.

The AC space can be fully covered: by transition delay and path delay vectors.

Summary & Conclusions

AC Scan is fully supported: by all major ATPG tools available today.

AC Scan can be used to target DSM and nm design effects: with additional information from static timing analysis and the layout.

Desktop Structural Testers with AC Scan support: can reduce cost in time, effort, and $$

Gratuitous Plug

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Focus On Structural Test: AC Scan - SiliconAid · PDF fileFocus On Structural Test: AC Scan....

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