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Spacer Lithography for Reduced Variabilityin MOSFET Performance

Prof. Tsu-Jae King Liu

Electrical Engineering & Computer Sciences Dept.University of California at Berkeley

Graduate Student: Ms. Xin Sun

FLCC Seminar

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Outline

• Introduction– MOSFET scaling– Lithography challenges

• Spacer Lithography

• Device Simulation Study

• Summary and Future Work

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Improvements in IC performance and cost have been enabled by the steady miniaturization of the transistor

IC Technology Advancement

Better Performance/Cost

Market Growth

2000 2005 2010 2015 20201

10

100

GA

TE

LE

NG

TH

(n

m)

YEAR

LOW POWER HIGH PERFORMANCE

International Technology Roadmap for Semiconductors

Transistor Scaling

Investment

SMIC’s Fab 4 (Beijing, China)Photo by L.R. Huang, DigiTimes

YEAR: 2004 2007 2010 2013 2016

HALF-PITCH: 90nm 65nm 45nm 32nm 22nm

PITCH

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The Bulk-Si MOSFET

• Current flowing between the SOURCE and DRAIN is controlled by the voltage on the GATE electrode

Substrate

Gate

Source Drain

Metal-Oxide-Semiconductor Field-Effect Transistor:

GATE LENGTH, Lg

OXIDE THICKNESS, Tox

JUNCTION DEPTH, Xj

M. Bohr, Intel DeveloperForum, September 2004

Desired characteristics:• High ON current• Low OFF current

• “N-channel” & “P-channel” MOSFETs operate in a complementary manner“CMOS” = Complementary MOS |GATE VOLTAGE|

CU

RR

ENT

VT

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VT Roll-Off

• |VT| decreases with Lg

– Effect is exacerbated by

high values of |VDS|

• Qualitative explanation:

– The source & drain p-n junctions assist in depleting the Si underneath the gate. The smaller the Lg, the greater the percentage of charge balanced by the S/D p-n junctions:

M. Okuno et al., 2005 IEDM p. 52

Large Lg: S D

Small Lg: DS

n+n+

VG

p depletion region

xj

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Sub-Threshold Leakage

• Leakage current varies exponentially with VT

• S ≥ 60mV/dec at room temperature, due to thermal distribution of carriers within energy bands– typically 80-100 mV/dec for a bulk-Si MOSFET

log ID

VG

IOFF, high VT

VDD

IOFF, low VT

ION, low VT ION, high VT

S

0

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Parametric Yield

• High-performance processors are speed-binned– Faster chips = more $$$

(These parts have smaller Lg)

• Leakage is exponentially dependent on VT = f(Lg)

• Since leakage is now appreciable, parametric yield is being “squeezed” on both sides

TOOSLOW

TOOLEAKY

smaller Lgate

Tighter control of Lg will be needed with scaling!

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The Sub-Wavelength Gap

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Achieving Sub-Wavelength Resolution

courtesy M. Rieger (Synopsys, Inc.)

Design

Mask

Wafer

250nm250nm 180nm180nm

OPCOPC

90nm and below90nm and below

PSM

0°

180°

PSMPSM

0°

180°

0°

180°

OPC0°

180°OPCOPCOPC

0°

180°

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Geometrical Regularity for Improved Yield

• A geometrically regular layout should be used to improve the fidelity of printed sub-wavelength features.– All MOSFETs are oriented

along the same direction– Gate lines are placed at

regular spacings

L. Pillegi et al., 2003 DAC p. 782

Configurable logic block layout

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Mask Cost ConsiderationsMask cost escalates with technology advancement!

It will eventually be more cost effective to use multiple lower-cost masks to define the most critical layer (gate)

<

(minimum half-pitch)

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Outline

• Introduction

• Spacer Lithography– Process flow– Application to gate patterning

• Device Simulation Study

• Summary and Future Work

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Spacer Lithography Process

gate dielectric

poly-Si gate layer

a-Si

1. Deposit & pattern sacrificial layer

Note that pitch is 2 that of patterned layer!

hard mask (SiO2)

Lg,min

gates

Si

gate dielectric

poly-Si gate layer

2. Deposit mask layer (e.g. Si3N4)

a-Sihard mask (SiO2)

Si

gate dielectric

poly-Si gate layer

3. Anisotropically etch mask layer

a-Si

hard mask (SiO2)

spacers

Si

4. Remove sacrificial material; Etch hardmask and poly-Si

gate dielectric

Si

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2n lines after n iterations of spacer lithography!

1st Spacers 2nd Spacers 3rd Spacers

High-Density Feature Formation

Photo-lithographically defined

sacrificial structures

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Y.-K. Choi et al., IEEE Trans. Electron Devices, Vol. 49, p. 436, 2002

Spacer vs. Resist Lithography

• Spacer lithography yields superior CD uniformity

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Gate Patterning using Spacer Lithography

1. Define fine-line features in a hard-mask layer using spacer lithography

• regular geometry (lines and spaces)

• Lg < pitch P ≤

2. Pattern fine-line features (to remove hard-mask where gate lines are not desired)

• minimum feature size > P

• alignment tolerance = P Lg

3. Define large features in a resist layer using photolithography

• minimum feature size P

• alignment tolerance >Lg

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Spacer Gate Patterning Benefits

• Provides fine-line gate electrodes oriented in parallel and laid out on a regular grid– Minimizes feature variations for improved yield– Facilitates RET to achieve smallest possible feature sizes

tight control of Lg high parametric yield

• Note that the geometrically regular mask (Step 1) can be used for multiple chip designs, to save cost

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Lg

Lg

Gate formation by spacer lithography

uniform Lg

Achieving Uniform Gate Length

Fin formation by conventionallithography

non-uniform Lg

Y.-K. Choi et al., IEDM Technical Digest, pp. 259-262, 2002

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Outline

• Introduction

• Spacer Lithography

• Device Simulation Study– Approach– Initial results

• Summary and Future Work

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Approach

• Use 3-D device simulations (Sentaurus Device) to investigate the benefits of spacer gate lithography – nominal Lg < 40nm

• Sources of variation include:– Lg variations

– line-edge roughness (LER)– statistical dopant fluctuations (SDF)

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EUV Resist LER Data from AMD

0 200 400 600 800 100032

34

36

38

40

42

Filt

ered

LW

R (

nm

)

Line Position (nm)

Average CD = 37.9nm

Standard Deviation = 1.7nm

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RTA: 1000°C 10s Spike: 1100°C 1s Flash: 1300°C 1ms

S/D ext. implant: 3E14 As+ cm-2 @ 3keV

Trend toward diffusion-less anneal increased junction roughness

Impact of S/D Implant Anneal Conditions

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Device Simulation: Methodology

LER Generation

Structure Generation

Device Simulation

Wchannel = 50nm

Lg = 37nm

Xj = 20.4nm

Tox = 1.2nm

Nbody = 2.2E18cm-3

Assume S/D junction follows LER profile.

Sentaurus 3D Device simulation

Collect statistical distributions of ION and IOFF

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Simulated MOSFET Structures

Resist Lithography Spacer Lithography

Plan View(gate electrode)

Isometric View Plan View(gate electrode)

Isometric View

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Initial Results

1.00 1.02 1.04 1.06 1.08 1.100.01

0.02

0.03

0.04

0.05

Conventional Spacer Litho.

ION

(mA/um)

I OF

F (u

A/u

m)

Smaller spread in IOFF vs. ION is seen for spacer gate lithography

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Outline

• Introduction

• Spacer Lithography

• Device Simulation Study

• Summary and Future Work

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Summary• Tighter control of Lg will be needed with transistor

scaling; however, this becomes more difficult as the “sub-wavelength gap” increases

• Spacer lithography provides for better CD control, and will eventually be a more cost-effective approach than conventional resist lithography for patterning gate electrodes

• LER effects on MOSFET performance can be mitigated by spacer gate lithography

Future Work• Assess the relative impacts of various sources of

variability (line-width variations, LER, SDF)