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Fixed point to floating point conversion

I.  Objectives: To design fixed point to floating point encoder and experiment with simulation,

synthesis and implementation features of the Xilinx Project navigator. Specifically, the

objectives of this lab are: 1.  To try out basic building blocks of VHDL behavioral description especially processes.2.  To learn how to translate problem specification into VHDL code.

3.  To consolidate understanding of the development board and to learn different techniques

of utilizing its resources.4.  To consolidate test bench writing skills.

II. 

Submission: Email solution of “Exploratory and Mandatory Exercises” section given at the

end of this lab manual to aatifshahbaz@pafkiet.edu.pk   by next Monday. Email subject

format should be Lab01_XXXX_YYYY_ZZZZ ( Where Xs, Ys, and Zs are student IDs of

the group). 

III. 

Background:Lectures on VHDL.

IV. 

Procedurea.  Refer to attached pages of a reference book and read and understand the concept of Floating

 point encoder. Briefly it is:

1.  A combinational circuit to convert an 11-bit unsigned binary integer B into a 7-bit

floating point number M,E, where M and E are 4-bit mantissa and 3-bit exponentrespectively.

2.  The numbers have the relationship B= M.2E + T where T is the truncation error, 0 ≤

T < 2E

.

 b.  Decide the conversion logic

c.  Decide about the input/outputs of the design. This is a very important step in system

modeling, consider the system as a black-box and decide its inputs and outputs.

d. 

Hint! For determining I/Os draw the block diagram considering design specification and board’s facilities/limitations (especially multiplexed lines for four seven-segment displays)

e.  Create the project with appropriate entity

f.  Make use of both sequential and concurrent statements.

g.  Compile code and correct all syntax errors. 

College of Engineering

KIET

Advanced Digital

System Design 05

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Simulation:h.  Write a test bench and simulate the design.

i.  Observe outputs on the wave window of simulator and convince yourself that your design iscorrect.

 j.  Write a file-based test bench and verify the design

Synthesis and Implementationk.  Using constraints make sure that higher eight bits of fixed point number are entered through

slide switches and the output is displayed on three 7-segment displays. Some sample inputand outputs are:

Input : Output

“10011010101”  9 E 7

“10111010100”  b E 7“00111111111”  F E 5

l.  Seeing the sample I/Os you may reconsider your decision of I/Os in step C above!

m. 

As is obvious from the above examples, for mantissa the 7-segment decoder will have to beextended to include equivalent binary numbers from 10-15 to be displayed as A, b, C, d, E,

F – note some of the alphabets are lower case.

n.  Also note that displaying three 7-segment displays simultaneously takes some ingenuity.

Make use of the code given at the end of this document. Make sure you have the appropriateentity and signal declarations. Help will be given during lab as well!

o.  Follow the instructions of programming Spartarn-3 FPGA board.

 p.  Using slide switches for inputs and observing outputs on the 7-segment displays, prove thatyou have correctly implemented the design.

Exploratory Exercises:1.

 

For clock division use DCM (Digital Clock Manager) and instantiate a DCM in

your design.

2.  Hint! Use only required ports (may be just one) and leave the rest as “open” in the port mapping. For further details and guidance read through DCM manual 

3.  Write a basic design to explore and demonstrate many uses of DCM.

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Code for Clock division:

-- clock division block--divides the clock of 50MHz by 64K i.e. down to ~780 Hz

-- to avoid operating seven segment displays at high frequencies (in MHz range)

 process (clk50) begin

if clk50'event and clk50 = '1' then

khertz_count <= std_logic_vector(unsigned(khertz_count) + 1) ;if khertz_count = "1000000000000000" then

khertz_en <= '1' ;

khertz_count <= (others => '0') ;

elsekhertz_en <= '0' ;

end if ;

end if ;end process ;

Hint!

To try out these single process or multi-process design files, you will have to create appropriate entities and place the code in the architecture body and declare required signals or variables.

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-- This block shows an example to illustrate multiplexing output to more than one 7-segments

-- This block shows how to multiplex output to different 7-segments

 process (khertz_en, ChangeDigit) begin

if khertz_en'event and khertz_en = '1' thenChangeDigit <=std_logic_vector(unsigned(ChangeDigit) + 1);else

ChangeDigit <= ChangeDigit;

end if ;

case ChangeDigit is

when "00" => SSgSel <= "0111" ; curr <= BCDOut(11 downto 8);--curr <=OutPutToSSG1;

when "01" => SSgSel <= "1011" ; curr <= BCDOut(7 downto 4);--curr <= OutPutToSSG2;

when "10" => SSgSel <= "1101" ; curr <= BCDOut(3 downto 0);--curr <=OutPutToSSG3;when others => SSgSel <= "1110" ; curr <= CandyCount; --curr <=OutPutToSSG4;

end case;

--Binary to seven-segment decoder

case curr is --.gfedbca

when "0000" => ssg <= "11000000" ;when "0001" => ssg <= "11111001" ;

when "0010" => ssg <= "10100100" ;

when "0011" => ssg <= "10110000" ;

when "0100" => ssg <= "10011001" ;when "0101" => ssg <= "10010010" ;

when "0110" => ssg <= "10000010" ;

when "0111" => ssg <= "11111000" ;when "1000" => ssg <= "10000000" ;

when "1001" => ssg <= "10010000" ;

when "1010" => ssg <= "10001000" ;

when "1011" => ssg <= "10000011" ;when "1100" => ssg <= "11000110" ;

when "1101" => ssg <= "10100001" ;

when "1110" => ssg <= "10000110" ;when "1111" => ssg <= "10001110" ;

when others => ssg <= "11000000" ;

end case ;

end process ;