FINAL REPORT

HIGH BIT RATE MASS DATA STORAGE DEVICE

SUBMITTED UNDER

CONTRACT NAS 8-28959

TO

NATIONAL AERONAUTICS & SPACE ADMINISTRATIONGEORGE C. MARSHALL SPACE FLIGHT CENTER

HUNTSVILLE, ALABAMA

DOCUMENT TM-329-165

FEBRUARY 23, 1973

LEACH CORPORATIONCONTROLS DIVISION

717 N. CONEY AVENUEAZUSA, CALIFORNIA 91702

https://ntrs.nasa.gov/search.jsp?R=19740019548 2020-03-23T11:10:23+00:00Z

PREFACE

This report has been prepared in accordance with data requirement

description MA-061 of Contract NAS8-28959 for a High Bit Rate

Mass Data Storage Device manufactured for GMSFC by Leach Corporation.

R. E. CroweProgram Manager

Director of Engineering

- i -

TABLE OF CONTENTS

Page Number

SECTION I CONTRACTURAL WORK REQUIREMENTS 1

SECTION II SUMMARY OF THE ACCOMPLISHMENTS AND 2ASSESSMENT AGAINST THE SCOPE OF WORK

SECTION III DETAILED TECHNICAL INFORMATION 2

Figure 1 - HDDR II Mass Data Storage System 4

Figure 2 - HDDR II Mass Data Storage System, 5Recorder Cover Open

Figure 3 - HDDR II Mass Data Storage System, 6Rear View

Figure 4 - HDDR II Mass Data Storage System, 7Rear Cover Open

Figure 5 - Double Density Waveforms 8

Figure 6 - Generation of Sync Word 11

- ii-

SECTION I CONTRACTURAL WORK REQUIREMENTS

1.1 Scope of Work

The scope of work is defined in exhibit "A" of Contract NAS8-28959.(See Appendix A of this report).

Exhibit "A" of Contract NAS8-28959 consists of three basic parts:

(a) Technical Requirements

(b) Delivery Requirements

(c) Data Requirements

1.2 Technical Requirements

The technical requirements are per GMSFC specification GC110467as modified by Leach Proposal 732639 and Leach letter dated 6/27/72.(See Appendix B of this report)

The technical requirements are, briefly: A device which can recordand reproduce a 10 Mbs BI-0-L signal for 30 minutes continuouslywith an error rate of less than 10-0 in a laboratory environment.

1.3 Delivery Requirements

The delivery of the device is required within six months afteraward of contract (December 29, 1972) and the final reportdue thirty (3) days later (January 29, 1973).

1.4 Data Requirements

The data requirements are per DRL 308, Contract NAS8-28959and consists of monthly letter progress reports, this final report(TM 329-165) and the operation and maintenance manual to besubmitted with the end item.

-1-

SECTION II SUMMARY OF THE ACCOMPLISHMENTS ANDASSESSMENT AGAINST THE SCOPE OF WORK

2.1 Technical Performance

The High Bit Rate Mass Storage Device as tested per LeachATP 204411 exceeds the contractural technical performancerequirements as described in Section 1.2 of this report.

2.2 Delivery Requirements

The hardware was shipped on February 19, 1973, Way BillNo. 075405362, approximately 30 days behind schedule.

SECTION III DETAILED TECHNICAL INFORMATION

3.1 Design Principles

The basic design principles which led to the Leach "HD 103Feasibility Model" (the forerunner of this device) areexplained in Appendix C, "Technical Discussion and DoubleDensity Codes".

The High Bit Rate Mass Storage Device was based on theLeach developed "HD 103 Feasibility Model". The logicimplementation was changed for reduced IC package count.

3.1.1 Design and Functional Description

The following is a detailed discussion describing the designand function of the High Bit Rate Mass Storage Device. Theapplicable schematics are attached to this report. The Leachsupplied instruction manual also contains this material. Thefunctional description of the MTR-7114 tape recorder iscontained in a standard manual concerning the recorder only.

-2-

3.1.1.1 DESCRIPTION

The HDDR-II Mass Data Storage System consists of a Leach MTR 7114

Recorder/Reproducer a wire- wrapped, integrated circuit flat plane and

necessary power supplies for the flat plane. These units, with intercon-

necting cables and control panel are enclosed in a common housing

mounted on casters. Refer to Figure 1, Figure 2, Figure 3 and Figure 4.

The description of the MTR 7114 Recorder/Reproducer can be found in

the manual for that unit. The purpose of this discussion is to describe

the electronics used in the HDDR-II double density decoding and

encoding techniques.

3.1.1.2 THEORY OF OPERATION

The following paragraph is a discussion of the double density recording

and reproducing techniques. Shown in Figure 5 is a binary representation

of a SOM signal. This SOM signal may be toggled off either the positive

or negative toggle. In Figure 5, it is shown coming off the positive

toggle; divided by 2. This is the double density wave form. After it has

been toggled off the SOM signal, all of the binary information is still

maintained in the double density wave form. The code is listed under

the double density wave form as being either a 2, 3, or 4. If there is one

full bit width between the transitions of the double density wave form

this is called a 2. If there is 1-1/2 bit widths between transitions, it is

called a 3. If there are 2 bit widths between transitions, it is called a 4.

This code has one characteristic which allows a parity detection and is

also used to generate a sync word for purposes of deskewing. This

characteristic is the fact that the data can never generate an odd number

of 3's between 4's. Thus, the sync word used in the HDDR-II Mass Data

Storage System is a pattern 4, 3, 4, 3. This pattern cannot be generated

-3 -

FIGURE 1. HDDR - II MASS DATA STORAGE SYSTEM

-4-

FIGURE 2. HDDR-II MASS DATA STORAGE SYSTEM, RECORDER COVER OPEN

-5-

FIGURE 3. HDDR-II MASS DATA STORAGE SYSTEM, REAR VIEW

-6-

FIGURE 4. HDDR-II MASS DATA STORAGE SYSTEM, REAR COVER OPEN

-7-

BINARY I I I 0 0 0 I 0 I 0 0

s I -L i I _ - J -- IF-] _J IDOUBLEDENSITY i

CODE 2 2 3 4 2 3 3 3 3

00

FIGURE 5

DOUBLE DENSITY WAVEFORMS

by the data, therefore the data can never generate a false sync. The

sync word is discussed further in the text.

3.1.1.3 ENCODER

The block diagram for the HDDR-II Mass Data Storage System is on Dwg.

204448 located in Appendix "D". Refer to it during this discussion, and

also to the schematics on Dwg. 204257. Referring to the block diagram on

the HDDR-II twelve-channel recorder encoder, there are clock and data

selection gates. These are used first to determine whether the recorder is

in the record mode or in the playback mode. This is determined by means

of the record indicate signal from the MTR 7114 recorder. If it is in the

record mode, the only clock that can be selected is the bit clock along with

the BI-0-L data. If in the playback mode, the clock that is selected is

either the external clock or the 10MHz internal clock as determined by

the clock select switch. In the record mode, the clock select switch has

no effect. The data polarity switch simply inverts the incoming BI-O-L

data. The output of these clock and data selection gates form a signal

which is the ANBC clock, which is the incoming 10MHz clock and the

NRZL 10MHz data. This is the data after it has been converted from

BI-0-L. These circuits are shown on page 2 of the schematic 204257.

Continuing to refer to the block diagram and page 2 of the schematic,

the ANBC clock is divided by 50 and outputted as a servo reference.

This servo reference is fed to one of the tracks of the recorder to servo

the recorder and to provide an initial dejittering of the data coming off

tape. Also, it will keep the packing density constant for various incoming

clock frequencies. The ANBC signal is divided by 12 and this output is

called "enable strobe", referred to on the block diagram and schematic

as ES. This term, ES, is used on page 3 of the schematic in the 12-bit

serial-to-parallel converter. It is also used again on page 17 of the

schematic in the parallel-to-serial converter of the output data after

it has been played back. The ES term is further divided by 128. Several

-9-

of the terms from the 128 divider are used in the buffer address control,

and on the decoder buffer read address.

After the term has been divided by 128, it is fed to the phase- lock

voltage controlled oscillator. This VCO generates the system bit clock,

called SBC, and this clock is approximately 14.2 MHz. SBC is divided

by 16 and shown on the schematic and block diagram as VCO 16. This

is the record frequency before it is divided by 2 for the double density

wave form. The VCO 16 term is divided by 8 and divided by 17 and

fed back to the VCO input. The two inputs to the voltage controlled

oscillator are phase locked at the same frequency. The VCO 16 signal

is 17/16 times greater than the ES signal. This 17/16 ratio allows the

insertion of the 8 - bit sync after the 128 bits of data.

Refer to page 3 of the schematic. Found here is the 12- bit parallel-

to- serial converter in the 16 x 12 encoder buffer. The 16 x 12 encoder

buffer is achieved by using three random access memories, each of

which is a 4 x 16 encoder buffer. The buffer address control provides

the control of the incoming data address and it also controls the address

of the outgoing data from the encoder buffer. The purpose of the encoder

buffer is to allow the insertion of the sync word. Refer to Figure 6. The

sync word, referred to as the sync toggle, is generated on page 2 of

the schematic and is designated by the term ST. This sync toggle goes

to page 4 of the schematic

After every 128 bits of data, the data coming out of the encoder buffer

is disabled for 8 bits. However, the data going into the buffer, at a

slower rate, continues into the buffer uninterrupted. The output of the

data, being disabled, allows the sync generator to generate its sync

word; on the double density code the sync word is 4, 3, 4, 3. Also in

the sync word is another bit of information which is a superfluous bit

added to get the ratio of 136 to 128, which is the same as 17/16. The

NRZL data is converted to SOM and then mixed with the sync toggle.

After this, it is passed through a divide- by- 2 D- type flip- flop which

-10-

ST LYhK 'K

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DOUBLE IDENSITY

CODE 2 4 4 4

FIGURE 6

GENERATION OF SYNC WORDREFERENCE: PAGES 2 AND 4 OF 204257

converts it to double density. It is then phase equalized and sent to one

of the twelve record tracks.

3.1.1.4 DECODER

The playback signal is capacitively coupled to a zero crossing detector.

Refer to pages 18, 19 and 20 of the schematic. The zero crossing detector

drives the high/low level detector which drives a lamp, indicating the

playback signal is too high or too low. These lamps are self explanatory

and are found on the front panel. The zero crossing detector is passed

to a transition detector that outputs a pulse for every transition, whether

it is positive or negative. The output pulse of the transition detector

is referred to on the schematics as FT3. This pulse is synchronized with

the SBC clock and is exactly one SBC clock wide. The transition detector

is used to reset a counter which drives the aperture detector. The

transition detector and counter are found on pages 5 through 16 inclusive

of the schematic. The aperture detector and the aperture- to- NRZL

converter and deskew/dejitter buffer are also found on pages 5 through

16 of the schematic. The counter is used to drive the aperture detector.

The aperture detector outputs the 2, 3, or 4 as used in the double density

symbolic language. These 2's, 3's and 4's are sent to what may be called

an aperture- to- NRZL converter. This is actually the heart of the

decoding process.

The aperture- to- NRZL converter has four basic outputs. (1) The 3's

parity output. This output detects whenever there are an odd number of

3's between 4's, which are not part of the sync word. In the event of a

3's parity error, the bit error lamp on the front panel will illuminate for

approximately 1/10 of a second. (2) The playback data output. This

output is NRZL data and still contains the sync word as part of it.

(3) The playback clock output. This playback clock inherently has a

lot of jitter. Even without flutter in the recorder, the playback clock

will have jitter due to decoding from a 2, 3 or 4 to NRZL data.

(4) The sync detector output. The sync detector zeros the deskew/dejitter

- 12 -

buffer write address. Thus, all 12 channels will have the same

read addresses, because the decoder buffer read address is the

same for all 12 channels. Thus, the sync detector by zeroingthe write address control, facilitates a deskew operation. Since

the information is clocked out of the buffer at the ANBC clock rate,it is also a dejitter buffer. The output of the random access memory(which is the 256 x 1 buffer) inherently has many slivers. These

slivers, or spikes, come at predictable times and thus can be

eliminated by proper clocking through a D-type flip-flop. This

is the desliver circuit found on page 17. All twelve channels

come to page 17 where they are deslivered and sent to a parallel-

to-serial converter. The parallel-to-serial twelve-channel con-verter accepts NRZL data from all twelve tracks and converts it to

NRZL serial data. It is then converted to BI-0-L data with a

clock output. It can be seen that this system allows a high densityrecording. The outputs are deskewed/dejittered Bi-0-L informationat 10 MHz. It should be kept in mind that during playback only,the same clock may be entered into the system that was used in

recording. Normally, this will be 10MHz, crystal controlled,internal clock. However, if another frequency is used, then an

external clock must be used and that external clock must be the

same clock that was used as the bit clock during record.

3.1.1.5 Calculations

Not applicable

3.1.1.6 Unique Procedures or Techniques DevelopedFor the Contract

Unique techniques were previously developed on the Leach HD 103feasibility model and applied during the construction of the device.These are described in Appendix C.

3.1.1.7 Operation Instructions

Operation instructions are contained in the instruction manualsfurnished with the equipment. Additional copies may be madeavailable on request.

3.2 Design Evaluation

3.2.1 Summary of Test Results

The error rate test summarizes a digital system's performance.Using a repeatative pattern, the measured error rate was7.9 in 108 compared to the 10- 6 error rate specified.

- 13 -

3.2.2 Description of Tests

Tests were run on the equipment per Leach LTP 204411 whichdescribes the purpose, procedures, and gives the detailedtest data. This procedure is Appendix D.

3.2.2.1 Evaluation of Test Data

The test data consisted of three basic sets of measurements:

1) Compliance to data and clock timing relationships.

2) Jitter between output data and clock measurements

3) Error rate data

3.2.2.1.1 Data and Clock Timing Relationships

These relationships were verified by paragraphs 3.1 and 3.2of the ATP to be within the Figure 2 tolerances (ATP)

3.2.2.1.2 Jitter Measurements

This measurement showed no discernable jitter on the 2nsscale of the 7704A scope.

This was to be expected because of the following:

1) The measuring equipment contributed negligible"apparent" jitter.

2) The data was being clocked out of the outputdejitter/deskew buffer by the same clock beingcompared to the data.

3) The data was further buffered by a SN. 74S74 veryhigh speed flip-flop before the output line driver.

4) The clock jitter was negligible.

-14-

3.2.2.1.3 Error Rate

The error rate data using the 16 bit repetative pattern specifiedin the ATP was 7.9 x 10-8.

Much testing during the pre-ATP was done with a 1 megabitrandom code. The equipment performance was not as goodwith this pattern, but was still within the 10-6 requirement.

During the pre-ATP phase, two important items wereapparent:

1) The heads should be cleaned every time the tapeis changed.

2) 3M type 971 tape provided better performance.The MTR-7114 was set up to use this tape, and theroll used for the ATP was sent with the device.

Analysis of the test data shows that the device exceeds allperformance requirements.

3.2.2.2 Problem Areas

During the course of development of this equipment, threegeneral problem areas were apparent. These were: (I) Thephase locked VCO and (2) High speed operation of conventionalcounter IC's and (3) Timing problems.

The first two problems were inter-related because the counterswere used around the loop, such that when the counter beganto miss counts the VCO was driven to a higher frequencycausing the counter tostop entirely.

A change in counter types and a faster method of decoding thecount was used to circumvent the problem.

A limitation to the VCO to prevent very high oscillation frequencieswas also implemented.

The timing problems were numerous, but were generally solvedusing Schottky high speed logic rather than a complete redesignof the circuit.

- 15 -

During the pre-ATP phase when all external panels werein place, a heat problem which resulted in the recorderequalizer changing characteristics was apparent. This, ofcourse, caused the error rate to increase as a function oftime.

This problem was solved by adding a blower to the bottomof the cabinet, and by removing a rear panel from therecorder.

Because the recorder is completely enclosed by the device'scabinet, the removal of this panel does not jeopardize operationof the equipment, and is not noticeable.

These problem areas, plus the required extensive debug of thelogic plane caused delivery to be extended approximately45 days.

3.3 Conclusions and Recommendations

This contract proved the feasibility of a high data rate massstorage device in a compact package for use in a laboratoryenvironment.

More development work will be required to reduce the size,weight and power for spacecraft applications.

- 16 -

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NOTES: UNLESS OTHERWISE SPECIFIED / I N EX AAOssEMVAL SEDON RG ES

REVISIONS

ZONE LTR DESCRIPTION DATE APPROVED

D DTABLE I

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FOR P FTS- LIST SEE PL204447 AND APPLICABLE DASH NO.

QTY fTEM PART OR NOMENCI TURE OR

REQD NO. IDENTIFYING NO. DESC R IPTION MATERIAL SPECIFICATION

_ _ _LIST OF MA ERIALS OR PARTS LISTUNLESS OTHERWISE SPECIFIED CONTRACT NO. CORPORATION

- - DIMENSIONS ARE IN INCHES . - LEACHTOLERANCE / DRAWN 1123173 717 NORTH CONEY AVE. AZUSA CAFORNIA( MARK ITEM 6 PER LEACH STD 201179-009 FRACTIONS ._xx / CHECKED I

WITH APPLICABLE NOMENCLATURE AS ANGLES- I.XXX / DESIGN CA LE INPUTA SHOWN PER TABLE I. MATERIAL ENGINEER ) A

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NOTES: UNLESS OTHERWISE SPECOFIED N/A U/O APPLICATION RFACE ROUGHNESS SCALE NOW E SHEET OF I

4 3 2

8 7 4 3 I2REVISIONS

CLOC, ZONI LIR DESCRIPTION DATE APPROVED

.F.LEI 1 Jn'' NRE-LS 50 SERVO 12- BIT SERIAL TO PARALLEL Ei.5 IN w REFERENCE ANBC

D RECORD IlnF (E- - UF

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(I--L (IO MI-iA" DATA) ADDRESS (12 CHANELS)

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- SBC VCO IG(14.2 MI-) (REF FREQUENCY)

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-* NE CONVERTER PB CLK

SYNC

HI-LO LEVEL DETECTION

DETECTOR 2"

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4 ADDRESS CONTROL DE-JITTER CIRCUIT DATAHI LO BUFFER

HDDR-TI DECODER (TYPICAL; I CHANNEL OF 12)

RN-L-L SERIAL DATA

WR7-L TO BI-0-L -T-PLUTPARALLEL

TO

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(12 CHANNELS)

OT ITEM PART OR NOMENCLATURE ORRE NO. DENTIYING NO DESCRIPTION MATERIAL SPECIFICATION ZONE

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MATERIAL ENGINEER MASS DATA STORAGE

RELEASE SYSTEMFINISH DESIGN APPROVAL SIZE I CODE IDENT NO. DWG NO. REV

QTY QTY NEXT ASSEMBLY USED ON DESIGN APPROVALD 9661 2 444NOTES ULESS OTWESIGISEN APPROVALSECIIEDNOTES UNLESS OTHER SE SPECIFIED

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FOR PARTS LIST SEE PL 204 495- 0014. ALL RESISTOR VALVES ARE IN OHMS :5%, 1/8 W.

3. REFERENCE DESIGNATIONS ARE ABBREVIATED: D IDENTIFYING NO. NO CPTE OR MATERIAL SPECIFICATON

PREFIX WITH UNIT NO. AND APPLICABLE t LIST OF MATERIALS OR PARTS LISTSUBASSEMBLY DESIGNATION. UNLESS OTHERWISE SPECIFIED CONTRACT NO. CORPORATION

DIMENSIONS ARE IN INCHES CONTROLS DIVISIO

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.

APPENDIX A

Contract NAS8-28959Leach Corporation

EXHIBIT "A"

SCOPE OF WORK

A. Technical Requirements

See ~44~4e6d Specification GC110467 for technical requirements for a highbit rate mass storage device, except referenced MIL-STD-480 and MIL-STD-454 arenot applicable and compliance to MSFC-STD-421A shall only be required as applicable.

B. Technical Controls

The design, technical approach and status of the effort shall be presentedin written and verbal form for review and approval by the MSFC, TechnicalRepresentative. The first presentation should be made two months (or earlierif ready) after the effective date of the contract and subsequent presentationsshould be made at two-month intervals throughout the contract period.

C. Delivery Schedule

1. Delivery of the High Bit Rate Mass Storage Device shall be within six(6) months after award of contract.

2. Delivery of all reports and data shall be as specified on DataRequirements List (DRL) No. 308 and as elsewhere specified in this contract.

3. The final summary report shall be delivered not later than seven (7)months after award of contract.

D. Data Requirement Statement of Work

1. General:

The contractor shall furnish all data identified and described in theData Requirements List No. 308 (hereinafter called DRL), attached hereto andmade a part of this contract. Such data shall be prepared in accordance withthe Data Requirement Description (hereinafter called DRD) referenced in theDRL for each line item of data such that the intent and objective of the DRDis satisfied.

Insofar as practical, contractor internal documents will be used tosatisfy the data requirements specified on the DRL and will not be retyped orreprinted unless authorized.

Nothing conltained in the DRL shall relieve the contractor fromfunrnishing d.ata calletd [or by, or under the ;iuthority of, other provisionsit tile contract whichl is not ident i tled iand described in the DRLI.

Contract NAS8-28959Leach Corporation

EXHIBIT "A" (CONT'D)

2. Identification of Data:

All data items delivered, except drawings and microfilm, shall betypewritten and clearly marked on the cover with the contract number, theDRL number, the DRL line item number and response number (i.e., 3rd monthlyreport, 0003). Documents that satisfy the requirements of more than oneDRL line item shall reflect all applicable line item numbers.

3. Title Page for Reports:

All reports shall be submitted under a title page showing the following

information:

a. Contractor's name and address, including segment generating the

report.b. Title of report, including period covered, when applicable.

c. Author(s)

d. Type of report and contract number.

e. Date of publication.

f. Prepared for George C. Marshall Space Flight Center, MarshallSpace Flight Center, Alabama 35812.

4. Reports Distributiont

All reports (except to DCASO) shall be addressed to NationalAeronautics and Space Administration, George C. Marshall Space FlightCenter, Marshall Space Flight Center, Alabama 35812 to the codes and inthe quintities as shown on the page of this Exhibit "A" entitled DistributionList for Reports and Data. A list of the reports distribution made by theContractor shall be attached to the reports forwarded to A&TS-PR-M.

2

APPENDIX B

ASPC PORM 411 (VERTICAL) (AUGi S 73ee6)NOTICE- Whom Government drawings a cifications. or other date are used for any purpo e other then in connection with a definitely related Gov-ernment procurment operation. the Unlted States Government thereby Incurs no responsibility nor obligation whatsoever; and the fact that thoGovernment may have formulatod. furnished. or In any way supplled the saId drawings specificationa or other date ta not to be regarded by I -p0loialn or otherwise as In any manner licensing the holder or any other person or corporation, or conveying any rights or permission to manu-facture, use, or sell any patented Invention that may In any way be rolated thereto.

APPLICATION PART No. MF REVISIONS

NEXT ASSY USED ON SYM DESCRIPTION DATE APPROVAL

A HIGH BIT RATE

MASS DATA STORAGE DEVICE,

SPECIFICATION FOR

UNLESS OTHERWISE SPECIFIED ORIGINAL DATE GEORGE C. MARSHALLmMNeSIONS ARE IN INCHES OF DRAWINGTOLERFANCEs ONa DRAFTSMAN I CECKER SPACE FLIGHT CENTERFRACTIONS DECIMALS ANGLES

TRACER CHECKER NATIONAL AERONAUTICS

ATERIAL ENGINEER ENGINEER AND SPACE ADMINISTRATION

SUBMITTED HUNTeVILLE, ALAIAMA

NEAT TREATMENT

_WG

FINAL PROTECTIVE FINISH SCALE

UNIT WT A SHEET 1 O

M6FC FORM 422-8 (VERTICAL) (NOVEM, 1962) CONTINUATION SHEET

REVIS IONS

SYM DESCRIPTION DATE APPROVAL

1. SCOPE

This specification defines the systenm design and performance requirements,

physical characteristics and limitations, and acceptance criteria for a High Bit Rate

Mass Data Storage Device.

1. 1 Purpose - The purpose of the High Bit Rate Mass Data Storage Device is to store

(record), or dump (playback or reproduce) serial digital pulse code modulated data at

a rate of ten (10) megabits per second continuously for a minimum time period of

thirty (30) minutes. The storage media containing the stored information (such as a

reel of magnetic tape) shall be removable from the device by simple manual means.

The storage media will be required to maintain the integrity of the stored information

as a separate entity until such time as it shall be reinstalled in a mass data storage

device for non destructive playback of the stored data. The device will be required

to playback or reproduce the data within the storage media at a serial digital rate of

ten (10) megabits per second bi-phase level PCM waveform.

The High Bit Rate Mass Data Storage Device is ultimately intended for use in Space

Stations to fulfill a requirement for bulk storage of digital data in a form which can be

removed from the Space Station and returned to ground operations. The hardware

supplied under this specification is intended for concept verification purposes and for

Space Station Sub-System Breadboard integration to verify the intended concept of

operation as a part of the Space Station Subsystem.

2. APPLICABLE DOCUMENTS

The following documents of the exact issue shown, form a part of this specification

to the extent specified herein. In the event of conflict between the documents referenced

herein and the contents of this specification, the contents of this specification shall be

considered a superseding requirement.

SPECIFICATIONS

Federal

Military

MIL-D-1000 Drawings, Engineering and Associated Lists

George C. Marshall Space Flight Center

MSFC-SPEC-331 Enclosures, Modular, Shielded, Radio

Frequency Interference, Specification for

CODE DWGIDENT NC SIZE GC 110467

A cHrT

ASPFC FORM 422-8 (VERTICAL) (NOVE R 1962) CONTINUATION SHEET ..

SRE VSIONS

SYM DESCRIPTION DATE APPROVAL

STANDARDS

Military

MIL-STD-1472 Human Engineering Design Criteria

for Military Systems, Equipment

and Facilities

MIL-STD-454 Standard General Requirements for

Electronic Equipment

MS-33586A Metals, Definition of Dissimilar

MIL-STD-100A Engineering Drawings Practices

MIL-STD-480 Configuration Control - Engineering

Changes, Deviations, and Waivers

George C. Marshall Space Flight Center

MSFC-STD-421A Electrical Support Equipment, General

Design Requirements for

MSFC-STD-Z75A Marking of Electrical Ground SupportEquipment, Front Panels, and Rack

Title Plates

George C. Marshall Space Flight Center (MSFC) Documents

MSFC-PPD-600 Electrical Preferred Parts, Volume I

and Volume II

CODE DWGIDENT NC SIZE GC 110467

A SHEET 3

MSFC FORM 422-8 (VERTICAL) (NOVEA ' 1962) CONTINUATION SHEET

REVIS 1IONS

SYM DESCRIPT ION DATE APPROVAL

3. REQUIREMENTS

3.1 Physical - Limitations on weight, dirmensions, and volume shall not be

imposed on the equipment.

3. 2 Maintainability - System equipment designs shall incorporate maintainability

features that will permit accomplishment of all necessary maintenance and repair with

a minimum expenditure of manpower and elapsed time. The requirements of

paragraph 5. 9 of MIL-STD-147Z shall be used as a design guide for incorporation of

these maintainability features.

The following maintainability requirements shall apply to system equipment:

a. System equipment shall be designed for 100% replacement capability

at the subassembly or component level or by functional substitution.

b. System equipment shall be designed to permit easy access for scheduled

maintenance and repair.

c. Access for maintenance shall be accomplished with minimum disconnection

of good equipment.

d. Repair, replacement, and assembly tasks shall minimize exposure to hazards.

3. 3 Operational Availability - System equipment shall have, as a minimum, a useful

life of five (5) years combined storage and service under the environment specified

herein.

3. 4 Safety - System equipment shall be designed to incorporate personnel and

equipment safety features specifi(ed h(,rein.

3. 5 Personnll/Opelraor Safety - System eqiliponnt dlsigns shall incorporate methods

to protect operating and se rvicing personnIel fronm accidental contact with electrical

potentials and shall not embody nmechanical features which may reasonably be

expected to cause injury during normal operation or because of malfunctioning of

equipment. Equipment chassis, enclosures, and frames shall be electrically

connected to the facility grounding grid at the nearest point. The length of projecting

and overhanging edges shall be held to a minimum and all projecting edges and

corners shall be rounded.

3. 5.1 Equipment Safety - System equipment shall be designed for protection from

overvoltage/undervoltage and transients as specified in MSFC-STD-421A.

3. 6 Environment - System equipment shall be designed to withstand the environments

specified in the following paragraphs.

3.6.1 Natural Environment - Natural eni nr-viients shall be as specified in MSFC-STD-

421Aand as shown in the following pafa'raphs: CODE DWG

IDENT NC SIZE GC 110467

A SHEET 4

M FC FORM 422-8 (VERTICAL) (NOVEM 1 1962) CONTINUATION SHEET

REVIS IONS

SYM DESCRIPTION DATE APPROVAL

3. 6. 1. A i bienLt 'lempe ratuIre - Systen e(lilllenl shall Ibe ((lesigned to withstand the

amnbient tcnmiperatures spe cified below.

Low Temperature High Temperature

Extreme Extreme

Non-Operating - 24 0 C (-10 0 F) + 52 0 C (+ 125 0 F)

and Storage

Operating + 4 0 C (+ 400F) + 43 0 C (+ 1100F)

3. 6. 1. 2 Relative Humidity - System equipment shall be designed to withstand the

conditions of relative humidity specified below:

a. Operating: Uip to 60%

b. Non-Operating: Up to 95%

3. 6.1. 3 Altitude - System equipment shall be designed to withstand the altitude

conditions specified below:

a. Operating: Sea level to approximately 5, 000 feet above

b. Non-Operating: Sea level to approximately 10, 000 feet above and storage

3.6.1.4 Vibration - System equipment shall be designed to withstand the vibration

environment specified below:

a. Operating: No requirement

b. Non-Operating: 0. 2 G peak 10 to 100 hz sinusoidal

3. 6. 2 Induced Environment - Induced environments shall be as specified in the

following paragraphs.

3.6.2. 1 Electromagnetic Interference - System equipment, when installed in enclosures

conforming to Specification MSFC-SPEC-331 or in an otherwise environment of equal

electromagnetic control, shall operate as specified when operating either independently

or in conjunction with other equipment with which there are electrical connections, or

which may be installed nearby; and shall not, in itself, be a source of interference

w hich might adversely affect the operating of other equipment. Interference control

shall be considered in the basic design of system equipment. The design shall be such

that, before interference control components are applied, the amount of inference

internally generated and propagated shall be the miniinmum achievable.

;~'L I DWG

IDENT NC SIZE GC 110467

A SHEET 5

MSFC FORM 422-8 (VERTICAL) (NOVEl 1 1962) CONTINUATION SHEET

REVISIONSSYM DESCRIPTION DATE APPROVAL

3.6. 3 Transportability - System equipment shall be designed to withstand the

normal handling, and transportation environments when packaged for delivery.

3.6.4 Storage - System equipnment shall be designed to withstand storage for periods

of up to five years under the environment specified as non-operating in paragraph

3.6.1.

3.7 System Design and Construction Standards - Design and construction standards

used in off-the-shelf hardware or hardware previously developed on other Government

contracts shall be acceptable provided the equipment is compatible with the performance

and environmental criteria as specified in this specification. The design and

construction standards specified herein shall apply to system equipment that must be

developed.

3.7.1 General Design and Construction Requirements - System equipment shall be

designed in accordance with the general requirements of MSFC-STD-4Z21 and as

specified in the following paragraphs.

3.7.1.1 Materials, Parts and Processes - Materials, parts and processes shall be of

the highest quality compatible with the technical requirements specified herein. Standard,proven and economical parts shall be specified to the maximum extent consistent with

reliability, maintainability and performance requirements.

3.7.1.2 Standard and Commercial Parts - Standard and commercial parts shall be usedwhere applicable if compatible with the performance and environmental criteria specified

herein. Where standard or commercial parts are not available, maximum utilizationshall be made of parts referenced in MSFC-PPD-600.

3. 7. 2 Electrical Design and Construction Requirements

3. 7. 2. 1 Primary Power - System equipment shall be designed to operate and maintainspecified performance from power sources supplying the following ac voltages. ACvoltages shall be provided by the facility and shall be 60 hz industrial type power.

CODE DWGIDENT N SIZE GC 110467

A SHP'FT

MSFC FORM 422-8 (VERTICAL) (NOVE R 1962) CONTINUATION SHEET

R EVISIONSSYM DESCRIPTION DATE APPROVAL

AC Voltages Specification

1. 115 volts RMS, 60 hz Industrial

2. 120 volts RMS, 60 hz Industrial

3.7. 2.2 Transient Suppression - Transients shall be suppressed as required for

equipment protection and radio frequency interference suppression. In application

of suppressors, the operation of associated circuit elements shall not be unduly

affected. Transient protection shall be provided in solid-state switching circuits,

and so packaged that the switching and protection circuits cannot be separated.

3. 7. 2. 3 Grounding and Shielding - Grounding and shielding of system equipment shall

meet the following requirements:

3.7.2. 3.1 Equipment Ground - Equipment chassis, enclosures, frames, and

neutrals of ac power sources shall be electrically connected to the facility grounding

grid at the nearest point.

3.7.2.3. 2 Shields - Shields over individual conductors shall be grounded at one point.

Shields shall not be used as signal or power return conductors. Any shielding system

shall consist of a network without closed loops, and shall be isolated from ground

potential except at the single point of connection to ground.

3. 7. 2. 4 Wiring and Cabling - System and equipment cabling and chassis assembly

wiring shall be in accordance with MSFC-STD-421A paragraph 5.7. 8.

3. 7. 3 Mechanical Design and Construction Requirements - Where practicable,

mechanical design of system equipment shall be in accordance with MSFC-STD-421A,

paragraph 5. 8.

3. 7. 4 Moisture and Fungus Requirements - System equipment shall be designed so

that the materials comprising its makeup are basically not nutrients for fungus.

However, the use of materials vh ich are not moisture or fungus resistant is not

prohibited in hermetically sealed assemblies. Fungus inert materials are listed

in MIL-STD-454, requirement 4.

CODE DWGIDENT NC SIZE GC 110467

A SHEET 7

MilCFFO.M 4iZ2-8 (VEN ,CALi NOVEM r - 102) CONTINUA. ION HEET

REVISIONSSYM DESCRIPTION DATE APPROVAL

.7. 5 Corrosion of Metal Parts - Metals used shall be of a corrosion-resistance typesuitably treated to resist corrosive conditions likely to he m et in manufacture, assembly,

testing, servicing, storage or normal service use. Unless suitably protected againstelectrolytic corrosion, dissimilar metals, as defined in MS 33586, shall not be used indirect physical contact.

3.6. 6 Contamination Control - Cleanliness of assembled electronic equipment shall

be maintained in accordance with good commercial practice.

3.7.7 Interchangeability and Replaceability - All system equipment, and componentsand subassemblies thereof, designed for replacement as the mode of repair shall bedesigned to be interchangeable. Interchangeable items shall be as defined in MIL-STD-100A.

3. 7. 8 Identification and Marking - Identification markings for electrical equipmentshall be legible and permanent, and shall be in accordance with MSFC-STD-275A.Vertical racks shall be identified by rack title plates. Marking shall be in accordance

With MSFC-STD-275A. Each connector of a cable assembly shall be identified byapplication of a suitable tag containing the complete reference designation of the cable

connector and that of its mating connector.

3.7.9 Workmanship - All system equipment shall be constructed in a thoroughly

workmanship-like manner. Particular attention shall be given to neatness and

thoroughness of soldering, marking of parts and assemblies, wiring, welding, and

brazing, plating, riveting, finishes, machine operations, screw assemblies, and

freedom of parts from burrs and sharp edges, or any other damage or defect that

could make the part or equipment unsatisfactory for the operation or function intended.

The requirements of MIL-STD-454, Requirement 9 shall apply.

3. 7.10 Human Performance - System equipment shall incorporate the human

engineering design parameters to allow optimum human factors practice to be

utilized in the validation of the man/machine relationship. The human engineering

design criteria specified in MIL-STD-1472 shall be used as guidelines in the design

of system equipment.

CODE DWG

IDENT NC SIZE GC 110467

A SHEET 8

MSFC FORM 422-8 (VERTICAL) (NOVEM" 1962) CONTINUATION SHEET

REVISIONSSYM DESCRIPTION DATE APPROVAL

3. 7. 11 Requirements for Bulk Data Storage - Bulk data storage requirements shall be

satisfied by a High Bit Rate Mass Data Storage Device (Subsystem) having the character-

istics described in the following paragraphs.

3. 7. 11.1 Subsystem Interface - The Mass Data Storage Subsystem will interface with a

Data Terminal Interface Unit.

3. 7. 11. 2 Input Data Format - The mass data storage subsystem shall accept a data

input signal which will be a serial Bi-Phase Level Pulse Code Modulated (PCM) wave-

train of 10 megabits per second. The input data will not be continuous. Discontinuities

will occur where the input PCM wavetrain will terminate and the input will remain at

0. 0 volt dc. potential (or ground potential) for periods of 5 seconds or longer. The input

circuit shall accept a standard TTL logic level compatible signal.

3. 7.11. 3 Input Data Rate - The mass data storage subsystem shall be capable of

recording input data at a rate of 10 megabits per second continuously for a minimum time

period of 30 minutes.

3. 7.11.4 Input Clock - A 10 megahertz per second clock input signal will be available.

The clock signal will be a 10 megahertz per second square wave 50% duty cycle and will

be in synchronization with all record data to the mass data storage subsystem. The input

clock signal circuitry shall be TTL logic level compatible.

3. 7.11. 5 Output Data Format - The mass data storage subsystem shall be capable of

reproducing the recorded data at a 10 megabit per second rate. The output waveform shall

be a serial Bi-Phase Level PCM waveform. The output circuit shall produce a TTL

logic level compatible signal.

3. 7.11. 6 Output Clock- The mass data storage subsystem shall generate an output clock

signal during reproduction of stored data which will be in synchronization with the data

being reproduced. The clock signal shall be a 10 megahertz per second square wave,

50% duty cycle. The output circuitry supplying the clock signal shall produce a TTL

logic level compatible signal.

3. 7. 11. 7 Output characteristics -

3. 7.11. 7. 1 Bit-to-Bit Jitter - Any reproduced output data bit period shall be within

0. 25% of the preceding bit period.

3. 7. 11. 7. 2 Cumulative Jitter - The cumulative jitter shall be less than +2. 0% of a

nominal bit period for any 400 bit sequence where referenced to the first bit or any

bit within the 400 bit sequence.

3. 7. 11, 7.3 Short Term Bit Error Rate - The bit error rate from input to output shall

not exceed one error in 106 bits during any 1. 0 second period of output data. Apparent

errors due to bit slippage, lost bits, repeated bits, and failure to stay in synchronization

shall not be exempt from error rate determination.

CODE DWGIDENT NC SIZE GC 110467

A SHEET q

SMSFC FORM 422.8 (VERTICAL) (NOVEI : 1962) CONTINuATION SHEET

R EVI SIONS

SYM DESCRIPTION DATE APPROVAL

3. 7. 11. 8 Tape Interchangeability - Magnetic tapes recorded on a given mass data storage

subsystem shall be capable of being reproduced on a similar subsystem with no degrad-

ation in performance or fidelity.

3. 7. 11. 9 Tape Quality - The mass data storage subsystem shall be capable of perform-

ing to the required specifications with Scotch No. 888 or equivalent tapes of 1 inch

normal width.

3. 7. 11. 10 Tape Reels - The mass data storage subsystem shall accept either precision

or non-precision reels of 14 inch diameter conforming to NAB Standards without modi-

fication or readjustment and meet all applicable specifications.

3. 7. 11. 11 Controls - The mass data storage subsystem shall have the following controls:

o Power ON/OFF

o Record

o Reproduce (playback)

o Fast Forward

0 Rewind

o Stop

A capability for both local and remote operation of the above control functions is re-

quired. The subsystem shall include the capability to recognize and execute the above

commands from signals. received. The signal input circuitry shall be compatible with

TTL logic levels.

3. 7. 1112 Operation Status Indications - The mass data storage subsystem shall have the

following status indications and signals:

o Record Mode

o Reproduce Mode

o Rewind Mode

o Fast Forward Mode

o Stop

o Tape Supply at Beginning

o End of Tape

CODE DWGIDENT NC SIZE GC 110467

A SHEET 10

MSFC FORM 422-8 (VERTICAL) (NOVE N 1962) CONTINUATION SHEET E V

REVISIONSSYM DESCRIPTION DATE APPROVAL

o Record Ready (Record command has been initiated, and subsystem is

up to speed and ready for data)

o Reproduce Ready (Reproduce command has been given and subsystem is

up to speed and producing valid output data)

The above status signals shall be available for both local and remote operation of the

subsystem. Locally, the status signals shall be displayed appropriately on the control

panel of the subsystem. Remote status indications will be by individual output signals.

The output signals shall be compatible with TTL logic levels.

3.7.11.13 Starting/Stopping Operation - Starting shall be by manual local operation or by

remote command. Stopping shall be by local manual operation, or by remote command,

or by automatic end-of-tape sensing or tape break sensing by the tape transport. End-of-

tape sensing will automatically stop the tape transport before tape runout at either the

beginning or end of the tape supply. The transport shall be equipped with a fail-safe

emergency braking system which shall operate automatically in the event of power failure.

3. 7. 11.14 Start/Stop Time - To be determined.

CODE DWGIDENT NC SIZE GC 110467

A qI-IFrT 11

27 June 1972

Purchasing OfficeGeorge C. Marshall Space Flight CenterMarshall Space Flight Center, Alabama 35812

Attention: W. L. Troupe

Subject: Contract NASB-28959

Gentlemen:

Enclosed is three (3) copies of the subject contract (proposed) which have been signedby Leach Corporation indicating our acknowledgement of the terms of the negotiatedagreement. Although Leach Proposal 732639 was not specified as a part of thecontract, compliance with Specification GC 110467 will be in accordance with rages2-1 through 2-7, Folder 1, of the Contractor's IPposal, with these exceptions calledout in Exhibit "A" of the Contract.

It is our understanding tht the International system of units is required for use on alltechnical reports, publications and visual presentations, however, that system of unitsis not required on the drawings or in the Opeeation and Maintenance Manual to besupplied with the High Bit Rote Mass Data Storage Device.

Leach Corporation is very pleased to have this opportunity to participate in anotherof the important programs at the George C. Marshall Space Flight Center.

Please direct all communications to the undersigned who has been given the fulladministrative responsibility for the contract on behalf of Leach Corporation.

Very truly yours,

LEACH CORPORATIONControls, Lfvsion

R. GouletteC tract Administrator

RG mm

Enc losures

Leach Proposal 732639 25 Apri l 1972

TECHNICAL PROPOSAL

SECTION I

CONTENTS:

1.0 Introduction

2.0 Specification Compliance

3.0 System Description

4.0 Summary Specifications

Appendix A Operation and Maintenance Manual Publication 203273

1.0 INTRODUCTION

Leach Corporation , Controls Division, offers the Model MTR-7114-1

Magnetic Tape Recorder/Reproducer System with HDDR -II digitalelectronics in response to NASA-MSFC RFQ 8-1-2-40-23068 and

Equipment Specification GC-110467. This technical proposaldescribes the equipment offered.

Leach supplied a high bit rate digital data system to the U.S. Air Forceover a year ago, which has been in regular use in an airborne environ-ment. This equipment is capable of reading and writing 24M bitsper second, using 12 parallel tracks on a standard IRIG 14 track

MTR-7114. The system proposed to NASA is a modification of theAir Force System, capable of handling 10M bits per second andwith improved performance. The pir Force unit is presentlyexhibiting an error rate of I in 10 or better in an aircraftenvironment.

The following sections describe the design approach, and include asan appendix the Operation and Maintenance Manual for the Air Forcerecording system.

1-1

2.0 SPECIFICATION COMPLIANCE

Leach has analyzed the NASA-MSFC Equipment SpecificationGC-110467 in detail and compared our offered equipment.The following paragraphs are numbered to match GC-110467.

2.1 SCOPE

Accepted

2.2 APPLICABLE DOCUMENTS

Specifications

Federal

Military

MIL-D-1000 Drawings, Engineering & AcceptedAssociated Lists

George C. Marshall Space Flight Center

MSFC-SPEC-331 Enclosures, Modular,Shielded, Radio FrequencyInterference, Specifica-tion for

The Leach MTR-7114-1 recorder, and HD103 high density encoder/decoder mounts in a standard RTMA 19-inch panel opening rack.Although this proposal does not include the racks, we assume ourequipment will fit the MSFC racks.

Standards

Military

MIL-STD-1472 Human Engineering DesignCriteria for MilitarySystems, Equipment andFacilities

MIL-STD-454 Standard General Require-ments for ElectronicEquipment

2-1

Since the recorder is off-the-shelf and the HD103 is a modificationof an existing design, we assume this design specification does notapply.

MS-33586A Metals, Definition of AcceptedDissimilar

MIL-STD-100A Engineering Drawing Practices Accepted

MIL-STD-480 Configuration Control -Engineering changes, devia-tions, and waivers.

Since relatively little design effort is required, conformance to thisspecification is not included in this proposal.

George C. Marshall Space Flight Center

MSFC-STD-421A Electrical Support Equipment,General Design Requirementsfor

Since the recorder is off-the-shelf and the HD103 is a modification of anexisting design, we assume this design specification does not apply.

MSFC-STD-275A Marking of Electrical Ground AcceptedSupport Equipment, FrontPanels, and Rack Title Plates

George C. Marshall Space Flight Center (MSFC) Documents

MSFC-PPD-600 Electrical Preferred Parts, AcceptedVolume I and Volume II

2-2

3.0

3.1 PHYSICAL

Accepted

3.2 MAINTAINABILITY

Since the Leach MTR7114 recorder is an off-the-shelf unit, we assumethe requirements of paragraph 5.9 MIL-STD-1472 do not apply.

Subparagraphs a, b, c, and d are accepted.

3.3 OPERATIONAL AVAILABILITY

Accepted with limitations as detailed under 3.6.4.

3.4 SAFETY

Accepted with comments noted below.

3.5

3.5.1 Equipment Safety

The MTR7100 is an off-the-shelf design following best commercialpractice.

3.6 ENVIRONMENT Accepted

3.6.1 Natural Environment Accepted

3.6.1.1 Ambient Temperature Accepted

3.6.1.2 Relative Humidity Accepted

3.6.1.3 Altitude Accepted

3.6.1.4 Vibration Accepted

3.6.2.1 Electromagnetic Interference

The MTR7114-1 recorder was designed to meet MIL-STD-222. It isbeing operated in many areas requiring EMC control.

2-3

3.6.3 Transportabi lity Accepted

3.6.4 Storage

Tape recording equipment may require bearing relubrication if stored5 years without operation.

3.7 SYSTEM DESIGN AND CONSTRUCTION STANDARDS

Accepted as modified by subsequent paragraphs.

3.7.1 General Design and Construction Requirements

The equipment is designed to "best commercial practice", and may notmeet all applicable paragraphs of MSFC-STD-421A.

3.7.1.1 Materials, Parts and Processes Accepted

3.7.1.2 Standard and Commercial Parts Accepted

3.7.2.1 Primary Power Accepted

3.7.2.2 Transient Suppression

The MTR7114-1 and HD103 may not meet the MSFC interpretation.

3.7.2.3 Grounding and Shielding Accepted

3.7.2.3.1 Equipment Ground Accepted

3.7.2.3.2 Shields Accepted

3.7.2.4 Wiring and Cabling

The MTR7100 recorder is designed to "best commercial practice" and maynot meet all the subparagraphs of MSFC-STD-421A, paragraph 5.7.8.

3.7.3 Mechanical Design and Construction Requirements Accepted

3.7.4 Moisture and Fungus Requirements Accepted

3.7.5 Corrosion of Metal Parts

An exception is required to this paragraph for all magnetic tape recorders,since the head pole pieces are not protected and are subject to corrosionwhen the equipment is left unused in a corrosive environment.

2-4

3.6.6 Contamination Control Accepted

3.7.7 Interchangeability and Replaceability Accepted

3.7.8 Identification and Marking Accepted

3.7.9 Workmanship Accepted

3.7.10 Human Performance

Within the constraint that the proposed equipment is very compact andcontains many controls and adjustments, MIL-STD-1472 will be usedas a guideline during design of the HD103.

We assume that MIL-STD-1472 does not apply to the MTR7114, whichis an existing standard Leach product.

3.7.11 Requirements for Bulk Data Storage

Accepted within the clarifications and exceptions listed below.

3.7.11.1 Intersystem Interface Accepted

3.7.11.2 Input Data Format Accepted

3.7.11.3 Input Data Rate Accepted

3.7.11.4 Input Clock Accepted

3.7.11.5 Output Data Format Accepted

3.7.11.6 Output Clock Accepted

3.7.11.7 Output Characteristics

Accepted with limitations noted below.

3.7.11.7.1 Bit-to-Bit Jitter

The tolerance of .25% calls for a maximum jitter of .25 ns, which will be

2-5

extremely difficult to measure and impossible to obtain withconventional techniques.

The data will be dejittered by an output buffer, and clockedout of the parallel-to-serial converter with a crystal derived clock

having a stability of one part in 106

All logic will be implemented with Schottky clamped TTL logic.Thus the jitter will be a function of the repeatability of this logicand not the tape recorder.

The jitter should be less than 3 ns.

3.7.11.7.2 Cumulative Jitter

Based on the above discussion, the jitter should be less than 3 nsover a 400-bit sequence.

3,7.11.7.3 Short Term Bit Error Rate

Since the tape is not certified to be error free with the proposedrecording technique, some tape selection will be necessary to meetthis error specification. In carefully reviewing this specificationin conjunction with the proposed system, it can be seen that missingor extra clocks constitute the most serious errors since they cause lossof synchronism in the parallel-to-serial converter and erroneouspositioning of data in the deskew buffers.

This would cause loss of an entire block of 128 x 12 bits, if itoccurs near the start of the block.

Thus, tape with dropouts ranging into the noise floor would have tobe culled from the usable tape supply.

The data recovery system will recover data with 20 dB dropouts readily,and provided a minimum amount of tape selection is done, the pro-posed system will meet the required error rate.

3.7.11.8 Tape Interchangeability Accepted

3,7.11.9 Tape Quality

3M971 high energy tape is recommended in lieu of 3M888. Type 971 isreadily available.

2-6

3.7.11.10 Tape Reels Accepted

3.7.11.11 Controls

The MTR7100 has a compatible control system with this paragraph, exceptthat both forward and reverse record and playback operation is obtainable.The command nomenclature is slightly different.

The remote control function must be implemented with open collectordrivers for the record, forward, reverse, fast forward, fast reverse,and stop functions. TTL compatible power ON/OFF remote functionis not available.

3.7.11.12 Operation Status Indications

Status indications are grounds, intended to provide a ground for a 28Vremote indicator lamp.

3.7.11.13 Starting/Stopping Operation Accepted

3.7.11.14 Start/Stop Time

The start/stop time of the standard Leach MTR7114-1 is 6 seconds, at120 ips and approximately 3 seconds at 60 ips, the proposed operationalspeed.

2-7

3.0 SYSTEM DESCRIPTION

By examining certain key requirements, it is possible to narrowdown the alternatives to the design quickly. The tape reel speci-fication along with the tape type indicates a requirement toavoid a rotating head machine or a high-speed flangeless realapproach such as the Newell concept. A more conventional IRIG14-inch reel instrumentation recorder is desired.

Since the record time is stated as 30 minutes continuous and becauseof the nature of the data, a track switching technique with tapereversals at each end is undesirable. This leaves us with a 14-inchNAB reel machine operating at a maximum tape speed of 60 ips toprovide 30 minutes record time.

The per track bandwidth is the next major recorder parameter to bechosen. This parameter will then, in turn, set the tape width ateither 1/2 or 1-inch.

Error rate as a function of maintenance is the real limitation to taperecorder packing density.

A desirable, although not necessarily mandatory, feature of theequipment is to be able to operate within the error rate specificationof no more than 10 errors in any one second period over a reasonableperiod of time, measured in days or weeks rather than hours.

Thus the packing density per tape track should be as low as possible,but consistent with IRIG standard track widths and spacing; "doubledensity" coding such as HDDR-II code should be used on tape toreduce the density as much as possible consistent with machine-to-machine compatibility. Because of these factors, a 14-track systemis selected with data recorded on 12-tracks, one servo track and onespare track on a standard 14-track IRIG interlace 1-inch tape system.Choice of this configuration will allow tapes to be played back onstandard wideband equipment. A data packing density of slightlymore than 14K bits/inch/track can be achieved.

Leach Corporation and others have delivered equipment operatingsuccessfully at higher packing densities and at less than the specifiederror rate. The configuration of the recorder has now been definedto be a wideband I-inch tape, 14-inch reel machine with a standard14-track IRIG head configuration.

3-1

Furthermore, it is desirable that the tapes could be reproducedon any IRIG Group II wideband machine suitably equipped with aformat converter as a physically external "black box".

This approach has been used successfully with the Leach HD102converter up to 16.6 K bits/inch and data rates up to IM bit/sec/track. The converter operates with any direct record widebandrecorder having phase equalization, with no special adjustmentsrequired.

We propose to satisfy this requirement with a new converter anda standard Leach Wideband recorder, the model MTR7114.Operation of the converter is as follows:

The serial input is first applied to a serial-to-parallel converter,the outputs of which drive 12 identical encoder/decoder channels.(Refer to Figure 1.)

Each of these channels contains the necessary electronics forencoding and simultaneously decoding the analog signal off tape.

In order to maintain synchronism of the 12 channels of reproduceddata after being subjected to recorder dynamic and static tapeskew, a sync word 9 bits in length is added every 128 bits. Thesync word is used during playback to synchronize the deskew buffers,thus lining up the channels for parallel-to-serial conversion.

Since data cannot be lost when sync is inserted, the actual recordeddata rate must be higher than the 10 megabit incoming rate. Thisrate is exactly 137/128 higher and is accomplished via a phase lockloop circuit and counter.

Before being recorded, the data is converted to a double density codeand low pass filtered to remove the high frequency components whichwould "beat" with the recorder's bias frequency. On playback, thedouble-density coded signal coming from the recorder's reproduceamplifier is decoded using a Leach proprietary circuit.

A portion of the decoding circuitry is a unique digital circuit whichcompensates for the "galloping baseline" or shifting dc level pro-duced by all double density codes.

These codes, while allowing an approximate increase in packingdensity of 30% (with the same error rate) compared to biphase codes,are pattern sensitive. That is, the signal contains a DC level whichis dependent on the pattern of I's and O's.

3-2

INPUT DATA

BI L 10 Mbps LON- HDDR 11 12 DIRECT

SERIAL TO PARALLEL RECINPUT CLOCK CONVERTER ENCODER/SYNC RECORD

SC GENERATOR AMPLIFIERS10 Mpps

INPUT POWER POWER SUPPLY TIMING & CONTROL

REGULATORS FUNCTIONS

OUTPUT DATA10 Mbps BI OL

PARALLEL TO SERIAL DECODER/DESKEW 12 REPRODUCE TAPE TRANSPORT

CONVERTER . BUFFER AMPS 9200' " TAPEOUTPUT CLOCK

10 Mpps

HDDR II SYSTEM

LOCAL CONTROL

PANEL & STATUS . CONTROL LOGICINDICATOR

REMOTE CONTROL

IPOWER INPUT __ POWER SLPPLY &

REGULATORS

Figure 1. SYSTEM BLOCK DIAGRAM MTR 7114-1"IDE BAND RECORDER

To successfully decode the zero crossings of the analog signal

from the tape requires a compensation circuit to recognize the

shifting DC level.

It is this circuit that Leach Corporation has developed, and a

patent is pending.

The sync code is detected and used to control the counter and

control circuit, which determines the time at which the buffer

register begins the load cycle. Data blocks of 128 bits enter

the buffers at a different time, but are unloaded at the same time

through use of a crystal controlled clock and associatedcounter/control circuit.

The sync word is automatically discarded during the load operation

of the buffer, and in order to maintain the data input rate (less

sync) equal to the output rate (which is controlled by the crystal),the tape recovered clock is phase locked through the recorder

servo to the buffer unload crystal controlled clock. Short term

jitter is, of course, removed from the data by the deskew buffer.

The output of the 12-channels is applied to a parallel-to-serialconverter which is reset every 128 incoming bits to preclude a

data skew condition from continuing indefinitely.

The data conversion unit is self-contained and requires 10-1/2inches of panel space. Channel modules containing the

electronics are plug-ins, for ease of maintenance. Modular

power supplies are included in the main frame as well as the"housekeeping" electronics such as the crystal-controlledoscillator, which is common to all channels.

A complete description of a similar system developed for the

Air Force is presented in Appendix A.

3-4

4.0 SUMMARY SPECIFICATIONS

4.1 INPUT

4.1.1 Data Rate 107 bits/sec

4.1.2 Format Biphase TTL compatible

4.1.3 Clock 107 pulses/sec

50% Duty cycleTTL compatible

4.2 TRANSFER AND STORAGE REQUIREMENTS

4.2.1 Record Time 30 minutes

4.2.2 Bit-to-Bit Jitter Data bit period shall bewithin 3% of the precedingbit period (3 ns)

4.2.3 Cumulative Jitter Less than +3.0% bit periodfor any 400 bit sequence(+ 3 ns nominally)

4.2.4 Error Rate One in 106 for any 1 secondperiod of time

4.3 OUTPUT CHARACTERISTICS

4.3.1 Data Biphase level TTL compatible

4.3.2 Data Rate 107 bits/sec

4.3.3 Output Clock Synchronous with the data -TTL compatible

4-1

4.4 TAPE HANDLING CHARACTERISTICS

4.4 1 Interchangeability Shall be capable of playbackon similar equipment

4.4.2 Tape Type 3M888 or 3M971

4.4.3 Tape Reels NAB Standard 14 inch diameter

4.4.4 Load/U n load Caplanar reels

4.4.5 Controls

Record

Reproduce

Fast Forward

Rewind

Stop

Remote Control

ALL ABOVE SIGNALS FROM TTL COMPATIBLE CONTROLLER.

4.4.6 Status Signals

Record mode

Reproduce mode

Rewind mode

Fast forward mode

Stop

Tape Supply at BOT

E.O.T.

Record Ready

Reproduce Ready

Remote Indications

ALL ABOVE SIGNALS FROM RECORDER SHALL BE TTL COMPATIBLEIN ADDITION TO LOCAL.

4-2

4.5 POWER 115-120V 60 HzIndustrial Power

4.6 ENVIRONMENT - OPERATING

4.6.1 Temperature +40OF to +1100F

4.6.2 Humidity Up to 60%

4.6.3 Altitude Up to 5000 ft

4-3

APPENDIX C

TECHNICAL DISCUSSION

ON

DOUBLE DENSITY CODES

Prepared by

LEACH CORPORATION/CONTROLS DIVISION717 North Coney AvenueAzusa, California 91702

(213) 334-8211

1072

DOUBLE DENSITY

Summary

Double-density codes are compared with bi-phase codes in density

attainable, bandwidth required, complexity in decoding, and start-

of-record synchronization. A little information theory proves that

the logical extensions of double-density to triple-or quadruple-

densities are not recoverable by any decoder means. Error detection

received special emphasis because double density codes are especially

pattern sensitive. Means for both acceptance and quick look error

detection are suggested. Described is a double-density code, HDDR II,

and means for decoding that compare favorably with other known means.

A "performance additive" is a feedback technique that compensates

for the galloping baseline that plagues all double-density schemes.

Breadboard tests of the described scheme show performance at 30.0 kbpi

with error rates less than 1 in 10 typical. At these densities the

magnetic tape must be very clean. It is recommended that potential

customers for any type of double-density equipment be warned to insist

that demonstration test patterns properly exercise potential gallopin

baseline problems.

General

Double-density codes are so named because they require a maximum of

one transition per bit compared with two transitions for bi-phase. Just

as there are different bi-phase codes, so there are different double-

density codes. Figure 1 displays the common codes from each family.

A bi-phase code is recognized by noting either one or two units of delay

between transitions. Also, groups of "ones" contain even numbers of

"ones". Double-density codes utilize two, three, and four units of delay

with an even number of "threes" between "fours".

-1-

BINARY 0 0 0 1 0 0 0

J ij TJ L K

BI-H _1 -- IASE-L-_r_BI-PHASE-M

(HDDR) -

HDDR II.I -..---

MILLER, i _-_ - ._ _-

DELAY (1)

MILLER (2)

(1) Miller, Wood, Delay are surprisingly all the some although different descriptions and

mechanizations are used by their originators. It is merely Bi-phase L toggled.

(2) Transitions occur on the end of every "zero" and in the center of every "one" except

"ones" immediately preceded by "zeros".

FIGURE 1

Doublk:-dlcnsity and bi-phase are names of families of codes. There

is generally too much emphasis laid on the merits of an individual code

within a family. People tend to speak of SOM or Miller codes as though

the individual codes determined the performance attainable. The per-

formcnce, of course, is determined by t' e decoder which solves the

problems of the family of codes. A particular code mjy be easier to

instrument with a given decoder than another code but these problems

are generally not significant. For example, the HDDR decoder comprising

a one - bit delay and exclusive OR gate is a "matched'-filter" detector

of all bi-phase codes. It will optimally decode not just SOM but the other

members as well (with suitable post-detection digital conversion logic).

DENSITY ATTAINABLE

Although only half as many transitions are required, nowhere near double

the density can be attairned with double-density codes. There are three

limitations at work here. In order of decreasing significance, they are:

choice between three delays instead of two; galloping baseline; no known

"matched filter" or other optimum detector.

Extra Delay Choices

The information is contained in the delays between transitions. If double-

density codes were operated at twice the density of bi-phase, the "eye

openings" in the playback waveform would be half as wide as bi-phase.

Signal to noise ratio would have to be 6 db greater to compensate. Also,

the ordinarily troublesome pattern-sensitive phase shifts of the recorder

and equalizers would have to be twice as good. These sources of error

have already been optimized for bi-phase, thus, double-density must

come down considerably from twice density.

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Go oping Base i ne

Double-density codes have a DC component that is not preserved through

playback. Different bit patterns produce different DC magnitudes. The

worst offender would be a "four", "two", "four", "two", .... pattern. In

this case, the DC component would be -33.3% of the 0-peak signal vol-

tage. Figure 2 shows a 3,3,3,3,2,4,2,4,2,4 pattern after ioss of its

DC component.

\1

FIGURE 2

The envelope and the ideal zero-crossing threshold (dashed line) have

shifted up exponentially. The shape of the envelope shift and its final

value are functions of the low frequency response of the recorder. More

precisely, if a 33% DC shift occurred in the waveform, the playback

envelope would equal a 33% step function minus the recorder's step function

response.

i.e., .EL

Using a fixed threshold detector, the envelope shift in the above waveform

has a strong tendency to make "threes" of the "twos" and "fours". This

effect is lessened by reducing the density and allowing the resulting har-

monics to make more vertical transitions through the threshold (Figure 3).

FIGURE 3

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io qu,ntiiutvely ussess this problem it would be necessary to relate its

effect on closing the "eye openings" of the waveform and then calculating

the necessary signal-to-noise ratio increase to maintain the same error rate.

The packing density would then be reduced a calculable amount to provide

this signal-to-noise ratio increase. "Eye opening" closure is measured by

calcula*ing the time displacement of zero crossings made by a finite slope

shifting up and down 33 1/3%. The slope is a function of the upper fre-

quency response of the recorder and equalizer; but increasing high frequency

response by equalizer adjustments also decreases the signal-to-noise ratio

which must be accounted for.

All these calculations seem beyond the scope of this report, therefore, a

quantitative evaluation will be abandoned.

No Optimum Detector

Codes in general are created with redundancies or self-checks often quite

by accident. The entropy or unpredictableness is thus less than maximum.

An optimum detector will utilize these redundancies to most efficiently re-

duce the error rate. The human brain, for instance, effectively uses word

redundancy by listening more to phrases than to individual words. Aperture

detectors classify transitions by the length of time from the last transition.

They have no memory of previous classifications and, thus, throw away the

redundancy or, at best, use it only to detect errors. This writer knows of no

double-density detector that properly utilizes the double-density redundancy.

The extent of such loss may be calculated. Entropy is measured in bits of

information (Shannons) per bit of data. The entropy of a digitally encoded

signal as measured by an optimum detector is one Shannon per bit. A double-

density aperture detector will measure a higher value. Random bi-phase data

contains 1.5 transitions per data bit. Double-density, therefore, contains

0.75 transitions per bit. With each transition, the aperture detector decides

whether it is a "two", "three", or "four". To determine the information con-

tent per decision, the a-priori probabilities of "twos","threes", and "fours"

must be known.

-5-

Look oi thte bi-phse M and HDDR li waveforms in Figure 1. Suppose

the last transition occurred at a bit cell boundary. Then for aon HDDR II

"two" to occur requires an NRZ "one" to have occurred, and the probability of

this is 1/2. A "three" requires a "zero" followed by a "one"---probability

of 1/4. A "four" requires a "zero" fol.wed by a "zero"--- probability

of 1/4. Now assume the last transition occurred in the midale of the cell

boundary. A "two" requires a "one" --- probability of 1/2. A "three"

requires a "zero"---. Now every bi-phase M cell boundary contains a

transition but only half the mid-points do. Therefore, HDDR II transitions

occur twice as often at cell boundaries than at mid points.

Thus, the a--priori probabilites are:

"twos" (2/3) (1/2) + (1/3) (1/2) = 1/2

"threes" (2/3) (1/4) + (1/3) (1/2) = 1/3

"fours" (2/3) (1/4) + (1/3) ( 0 ) = 1/6

Although we used bi-phase M and HDDR II, the same relations hold for bi-

phase -L and the double-density codes derived therefrom by merely referring

to NRZ changes instead of "ones" and "zeros". Obviously, changes from

zero to one and vice-versa are equally probable.

Now the average information per transition is:

1/2 log2 2 + 1/3 log 2 3 + 1/6 og92 6 = 1.459 Shannons

And the entropy is found by multiplying by the transitions per bit:

(0.75) (1.459) = 1.094 Shannons per bit

Thus, an aperture detector yields a 9.4% loss. Stated another way; since

the redundancy is not utilized for error correction, a code with 9.4% fewer

transitions could just as well been used for a 9.4% increase in packingdensity.

-6-

Total Effect

Since the galloping baseline problem is too hard to quantitatively

assess, the total effect will have to be sought empirically. An

aperture defector was built and tested against HDDR performance.

Performance testing shows that the double-density aperture detector

performed 75% better than did HDDR.

TRIPLE AND QUADRUPLE DENSITIES

As a further exercise of the simple information theory in the previous

section, consider triple density. Here, some bi-phase code is divided

by three for an average transition density of 0.5 per bit. Dividing

bi-phase by three yields transition lengths of 3, 4, 5 and 6. Assume

the lengths equally a-priori probable (thus assuming maximum infor-

mation per transition). The entropy, there is:

(0.5) (4) (1/4 log24 ) = 1 Shannon per bit

This is the minimum possible entropy for a code to have and still be recover-

able by any means. Less than this value indicates a loss of one-to-one

correspondence between data and signal space; but, the maximum information

condition of equally likely transitions lengths had been assumed. If this is

true, then an average transition has length (3 + 4 + 5 + 6)/4 = 4.5. Now

-7-

the transition density is 0.5, therefore 2.25 units per data bit are required;

but, as data bits are 2 units long, the transitions are obviously not equally

likely and the average information is less than maximum. Thus, the entropy

is less than the minimum value necessary for recovery by any means.

Even simplet is quadruple-density. Here transitions of 4,5,6,.7 and 8 occur

with a density of 0.375. Assuming the transitions equally likely again for

maximum information, the entropy is:

(0.375) (5) (1/5 log92 5) = 0.87 Shannons per bit

Again an unrecoverable code.

BANDWIDTH

Spectral densities are easier to measure than calculate. The bi-phase and

double-density spectra for one million bit pseudo-random sequences are

plotted in Figure.4.

1.0

Doub e-Den ity

0.8 -

0.6

Bi-Ph se

0.4

0.2

00 0.2 0.4 0.6 0.8 1.0 1.2 1.4

Normalized Bit Rate

FIGURE 4

-8-

The hiqnest low-frequency response required to pass these sigials without

appreciable error increase can be estimated by adding various RC high-pass

networks between the recorder and the playback detector. Bi-phase thus

appears to require low-frequency response of 0.4 times the bit rate. A

value for double-density is harder to come by because of pattern sensitivity.

However, using a 106 bit pseudo-random sequence, a 2 KHz maximum low-

frequency response appears necessary for a 900 K bit/sec data rate at 30 ips.

Oddly, this value appears optimum --- decreasing the cutoff point slightly

increases the errors. This phenomenon likely suggests that the existing 400 Hz

low end response of the tape recorder has a step function response not as

suited for decoding as the simple RC filter. Lowering the RC cutoff brings the

recorder cutoff into view and could thus be accentuating the galloping base-

line problem.

ERROR DETECTION

Pattern Sensitivity

Double-density error detection is evolving into a fine art. The unusual pat-

tern sensitivity of double-density is forcing this state of affairs. It has be-

come increasingly obvious that there is no absolute worst-case pattern inde-

pendent of equalization. Although certain patterns are undoubtedly harder

to recover than others, no outstanding worst-case pattern emerges. When a

pattern seems to be a candidate for this honor, it always turns out that a

playback equalizer adjustment or a change in the value of coupling capacitance

to the decoder reduces the errors considerably.

The use of long pseudo-random (PR) codes appear to be the only way to set up

the equalizer and certain other components in the system to ensure the best

average adjustments. The PR codes should be at least many times longer than

the ratio of bit rate to system low-frequency response. A million bits seems

just adequate for general use. Using the equalizer settings for the PR code,

worst case patterns can then be investigated.

-9-

Bit errors in the magnetic recording industry are getting increasingly

difficult to define. One innovation, apparently spawned in the computer

:~dustry, is to ignore "recoverable" erro. or errors that are not repeated.

or successive passes of the same record. Showing even greater ingenuity,

some digital recording manufacturers are claiming immunity from media

imperfections (dropouts). For example, in the Orion report of the Wood

code, only "corrected" errors are reported. "Corrected" errors are those

that remain after errors that occur in the same area of the tape are sub-

tracted. Presumably the next step would be to combine these two innovations

of definition and leave the manufacturer with no responsibility whatever for

errors accrued on his equipment.

Unfortunately, this state of affairs is unlikely to come about and the manu-

facturer must reassess his responsibility in this area. Obviously there is

no way to wiggle out of dropout induced errors. Dropouts are part of the

a-priori conditions of real tape and the manufacturer must build his equip-

ment to best perform with real tape. To claim dropout immunity so as to

stress "theoretical" performance of decoding equipment is to admit failure

of the theory employed to handle the statistical properties of dropouts.

Comparisons between decoding equipments must be made during dropout

conditions for, obviously, the prime value of a decoder is its ability to

function through dropouts. But neither is this an open and shut case, for

supposing one reel of tape were available and this tape had one big hole

in it. Obviously, the value of statistical interpretation is being lost in

attempting to characterize this one dropout.

Clearly, customers can be hurt more by one type of error than another.

It may mean nothing to a user to back up and try to recover errors. Also,

the distribution of errors may be important. A burst of 1000 errors is more

acceptable to some users than 1000 single errors equally spaced. Other

users are only hurt by burst errors. Another distinction is the clock-slip

type of error; loss of sync can be devastating to some users. Therefore, the

industry can continue to expect certain customers to weight certain types

of errors in acceptance test procedures.

-10-

Ihe need for a standard error definition still exists, however. Obviously,

each bit by bit deviation from a known pattern should be recorded as an

eror; but what about loss of sync due to clock slip? This is not so obvious.

How long should it take to recover sync? During sync loss every bit is

rmeaningles:t to the user but the error detector signals errors randomly (a

function of the auto-correlation properties of the test pattern). Is this

satisfactory'? The time to recover sync is a function of the length of the

test pattern length. Should short patterns be rewarded this way? Double-

density decoders in particular require very long sequences for adequate

exercise. This emphasizes the stress placed on errors due to sync slip.

How can a standard error definition be generally accepted when it requires

the specification of the test pattern?

A Possible Solution

No solution will satisfy every aspect of the' problem, but there is one

technique that appears superior to the rest. This solution rests on the

possibility of resynchronizing a 2 N -1 bit PR sequence in N bits after loss

of sync. The normal methods of resynchronization including the delay and

compare technique popular at Leach, require as many bits to resync as are

bits in the pattern. With the new technique, however, a 220-1 ( one million)

bit PR sequence can be resynchronized in 20 bits. This is accomplished

as follows. The 220-1 bit sequence is generated for recording by exclusive

ORing the 17th and 20th bits of a 20 bit shift register and feeding that signal

back into the input of the register.

STo record

The playback waveform is the input to a similar generator as shown in Figure 5.

As soon as the register is full, the exclusive OR gate outputs the proper sequence

in sync with the playback sequence. A bit by bit comparison is accomplished

with exclusive OR gate A. A single bit error results in three pulses from this

gate; one immediately, one seventeen bits later and one twenty bits later. It

-11-

Loe.s no good to divide the pulses by three to obtain the true error count

because error bursts would then be miscounted by a factor of three. Instead,

a third generator is employed (in feedback mode) and gate B compares the

output of this generator with the playback sequence to obtain the true error

count . The third generator is synchronized by transferring the contents of

register C into register D if ever an error is detected at gate B simultaneous

with no error at gate A.

Playback - Playback Clock

P2ybc . - z To O

Data ....0

RegistersA

B0

-- 1 Errors

(accept inputs)

FIGURE 5

PR sequences are becoming more popular for testing. The recent HP PR

sequence noise generator Model 3722A and HP binary sequence generator

and processor Model 1930A are excellent responses to the demand for PR

testing. In fact, the Model 1930A comes very close to fulfilling the recording

-12-

industries needs. Unfortunately, error detection synchronization on this

model is implemented by a front panel push button (or can be arranged for

automatic synchronization but with three times the output errors). Other

minor problems make the Model 1930A an unattractive purchase for error

detection.

Although the long PR sequence approach is attractive from several angles it

will not, of course, guarantee that no other pattern can be found that generates

more errors. The long PR sequence comes closer to actual real world operating

conditions and should be readily accepted in spite of this possible shortcoming.

The long PR sequence offers an attractive means to comparing equipment of

different manufacturers since it displays such a wide variety of bit combinations.

Worst Case Patterns

The worst case pattern is the one that gives the greatest number of errors to a

particular decoder. It is difficult to tell which of many patterns actually

deserves this title, so there come to be many "worst case" patterns. The

quotation marks indicates the use of worst case to mean more than one possible.

"Worst case" patterns are characterized by strong DC components coupled

with a certain degree of randomness. A "worst case" pattern for one double-

density decoder is therefore a likely "worst case" pattern for another double-

density decoder design.

Some care must be exercised is specifying "worst case" patterns by their NRZ

data components alone. The reason is that there are often two double-density

realizations of each NRZ pattern depending on whether the initial transition

corresponds to a mid cell or cell boundary transition. When NRZ patterns are

specified it should be done so assuming the first transition to occur at a cell

boundary. This will be called "normal phase". When reverse phase is required,

it should be so indicated. When setting up a pattern generator to a given

sequence, the resulting double-density pattern should be checked on the scope

to verify proper phasing. Power to the generator can be interrupted or the

sequence reset from another pattern if the phasing needs to be bumped to the

other state. Phasing a test pattern, of course, has nothing to do with normal

-13-

opehltion of the decoder, it is only necessary when repeated results must

be obtained from certain "worst case" patterns and ensures that the desired

DC components will be obtained. Following are the two states of a certain

20 bit sequence.

NRZ Sequence 1 1 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1 1 1 0

HDDRII(Normalphase) 2 2 3 2 2 3 3 3 3 2 2 3 3 2 2 3

HDDRII (Reverse phase) 2 3 2 2 2 4 2 4 2 2 2 4 2 2 2 3

The normal phase pattern spends half of the time at each polarity for a re-

sultant zero DC component. The reverse phase pattern favors one polarity

60% of the time showing a strong DC component. Some NRZ sequences cycle

from normal to reverse phases at each completion of the fundamental NRZ

pattern.

Twenty bit patterns are favored over other lengths for testing "worst case"

conditions because the standard means for checking errors (using a 20 bit delay

and compare) results in sync recapture after 20 bits --- exactly the same as

the PR tester described above. Thus, direct error comparisons can be made

between the two types of sequences.

Quick Look Detection

Opposed to the more formal acceptance type of error detection, double-density

is blessed with a "quick look" capability. This capability originates in the

slight information redundancy of the codes expressed in the restriction that an

odd number of "threes" can't occur between "fours". If a flip-flop is toggled

by "threes" and reset by "fours", the state of the flip-flop just prior to being

reset must always be true. If not,an error has occurred. In the HDDR II de-

coder, to be discussed, this flip-flop is in the' circuit already for other reasons

so it remains only to sense the state of it prior to reset and thus control a visible

indicator. Fortunately, all errors involve the parity of "threes"; i.e., if in-

coming "twos" or "fours" are misread, they will be misread as "threes" unless

a very gross problem occurs. The only way to sneak an error past this detector

-14-

is to get an even number of errors between "fours" or to arrange the incoming

data to not have any "fours".

The advantage of quick look detection, obviously, is that it is pattern in-

sensitive. it is thus convenient for the user to monitor this detector while

receiving real-time data.

SYNCHRONIZATION

There are two sync problems --- data and frame. Data sync refers to the bit

pattern necessary to initiate an ambiguous data detection. For bi-phase M

this pattern consists of one or more zeros (which are found often enough in

real-world data that no special consideration is given it). Double-density

codes require a "four" in the signal for data sync. The Miller, Wood, or

Delay codes generate "fours" only from 101 data patterns. HDDR II generates

"fours" from 000 patterns and modified Miller requires 010 patterns. Whether

this decreased probability of immediate recovery after sync loss is a problem

or not is something only the potential user can answer.

Frame sync, of course, signals the major events of beginning and end of

frames or records. Frame sync is generally unique, thus employing some

signaling means orthogonal to the data signal. HDDR successfully uses zeros

at two-thirds frequency to signal frame sync. Double-density codes could

similarly use "sixes" (six units delay between transitions).

On playback, an aperture could be sensitive to the receipt of "sixes" thus

signaling frame sync. Both schemes require, unfortunately, the interruption

of data during frame sync. The question arises as to the applicability of the

redundancy of double-density codes for frame sync instead of error detection.

Unfortunately, such reworking of the code to capture this effect upsets the

data sync capability.

AN HDDR II DECODER

An aperture decoder was constructed to decode HDDR II. The schematic is

shown in Figure 6. A synchronous counter counts externally supplied 16X

clock pulses and is reset by every incoming transition. A network of gates

-15-

~. 6

-rEE' I '

I CO PENATO

- --- r ,) ~**

-- t I gyMi$2~IJO~ c a , 4

!i i

I _

I.I I' t i

I. II II II I

I

senses the state of the counter and opens three apertures corresponding to

the three anticipated delays between transitions. The timing is shown in

Figure 7.

Count 0 4 8 ,2 16 20 24 28 32

"twos"

"threes"

"fours"

FIGURE 7

The incoming transition, just prior to resetting the counter, is "ANDed" with

the three apertures resulting in a pulse from one of the three gates representing

the decision for a "two", "three", or "four". Refer to Figure 8. Knowing

the last duration between transitions is obviously insufficient to determine the

NRZ data. It is necessary to additionally know whether the previous tran-

sition was generated from a bi-phase cell boundary transition or from a mid-

cell transition. It is obvious on observation that "boundary" transitions occur

whenever an even number of "threes" has followed a "four". Similarly "mid-

cell" transitions occur after an odd number of "threes". Thus, a flip-flop keeps

track of parity by being toggled with "threes" and reset by "fours".

Thus there are six possible conditions to decode--the three possible durations

between transitions and the two parities of "threes". For each of these con-

ditions, a data "one" may or may not be appropriate immediately, one cell

later, or two cells later. Clock pulses are similarly required at various times.

Table 1 indicates the appropriate timing of data "ones" and clock pulses to

decode HDDR II. Eight-bit shift registers A and B provide the indicated half

and one bit delays of clock pulses while registers C and D delay the data "ones"

by half and one bits. Finally, the D flip flop lengthens the pulses corresponding

to data "ones" and provides the NRZ data output.

-17-

CONDITIONS DATA "ONE" NRZ CLOCK

Transition "Threes" 1/2 bit I bit 1/2bit IbitDuration Pority Now delay delay Now delay delay

Two Even X X

Two Odd X X

Three Even X

Three Odd X X X

Four Even X X

Four Odd X X

Table 1

TEST RESULTS

Leach MTR7000 transport (one inch) was used in all tests. Tape speed was30 ips (the decoder synchronous counter would not permit faster operation).Using 3M 880 tape, tests were first run to determine the optimum amountof comparator feedback. This is summarized in Figure 8,

0 ~"worst case"500 -200

100 106 bit PRRelative

X 1000 201 0 0

5

2

'normal phase"0.5

0.2

0 4 8 12 16 20 24 28 32(Feedback (%)

FIGURE 8

-18-

Test Results (Cont'd)

The equipment was optimized and equalized for the long PR sequence

and subsequently tested at four percent intervals. Then a "worst

case" 20-bit pattern was substituted and tested without reequalization.

This pattern is the one given previously in Section 3.8.4 (the "reverse

phase" pattern). Also, for comparison, the "normal phase" of the pattern

was tested. All tests were run at 33 kbpi to ensure plenty of errors.

The "normal phase" of the pattern has no DC component, thus no

improvement could be expected using feedback. Twelve to sixteen

percent feedback appears to be a reasonable setting for general use.

Next, tests were run at different densities using 3M 888 tape except

for two tests run with Leach LC-5 tape. For each tape type, the

transport was reequalized for optimum performance at 33 kbpl using

the long PR sequence. Tests at each density used 2000' of tape. The

same 2000' were used on both tape types.

-19-

APPENDIX D

LTP NO. 204411

ORIG. DATE 1/9/73

PAGE 1 OF 8

LEACH CORPORATION

CONTROLS DIVISION

717 CONEY AVENUE

AZUSA, CALIFORNIA

ACCEPTANCE TEST PROCEDURE

HDDR-II

HIGH BIT RATE MASS DATASTORAGE SYSTEM

PREPARED BY R. E. CROWE ~- i - '

REVISIONS

REV. BY DATE CHANGE PAGES AFFECTED

SOlRM NO. L- .

1.0 SCOPE

This Acceptance Test Procedure (ATP) in conjunction with LeachLTP 203333B for wideband tape recorder MTR 7000 series willdemonstrate compliance to GMSFC specification GC110467 asmodified by Leach Proposal 732639 and Leach letter dated 6/27/72,Subject Contract NAS8-28959.

1.1 The following requirements of GC 110467 will be verified by inspectionand/or analysis:

3.1 Physical

3.2 Maintainability

a. Parts replacement

b. Accessability

c. Connection of good equipment

d. Minimum hazard

3.3 Operational Availability

3.4 Safety

3.5 Personnel/Operator Safety (Modified)

3.5.1 Equipment Safety (Modified)

3.6 Environment

3.6.1 Natural Environment

3.6.1.1 Ambient Temperature

3.6.1.2 Relative Humidity

a. Operating

b. Non-operating

-2-

3.6.1.3 Altitude

a. Operating

b. Non-operating

3.6.1.4 Vibration

a. Operating

b. Non-operating

3.6.2.1 Electromagnetic Interference (Modified)

3.6.3 Transportability

3.6.4 Storage (Modified)

3.7 System Design and Construction Standards (Modified)

3.7.1.1 Materials, Parts, and Processes

3.7.1.2 Standard and Commercial Parts

3.7.2.1 Primary Power

3.7.2.2 Transient Suppression (Modified)

3.7.2.3 Grounding and Shielding

3.7.2.4 Wiring and Cabling (Modified)

3.7.3 Mechanical Design and Construction Requirements

3.7.4 Moisture and Fungus Requirements

3.7.5 Corrosion of Metal Parts (Modified)

3.7.6 Contamination Control

3.7.7 Interchangeability and Replaceability

3.7.8 Identification and Marking

-3-

3.7.9 Workmanship

3.7.10 Human Performance (Modified)

3.7.11.8 Tape Interchangeability

3.7.11.10 Tape Reels

3.7.11.11 Controls (Modified)

3.7.11.12 Operation Status Indications (Modified)

2.0 TEST SET-UP

The test set-up will be per Figure 1

All equipment except for Tektronix Model 7704A oscilloscope (whichis leased equipment)and special test jigs will be in current certificationper Leach calibration lab procedures.

3.0 TEST PROCEDURE

The following test procedure will be used to verify the requirementsof GMSFC specification GC110467 paragraphs 3.7.11.2, 3.7.11.3,3.7.11.4, 3.7.11.5, 3.7.11.6, 3.7.11.7.1, 3.7.11.7.2, 3.7.11.7.3,3.7.11.9

3.1 Input Data Format and Data Test

Verify that the output of the pattern generator is operating in synchronismwith the 10Mb ±1% clock and that the format is bi-phase level as definedin Figure 2, using the Tektronix Model 7704A oscilloscope.

3.2 Input Clock

Verify that the phase relationship between the input clock and inputdata is per Figure 2, using the Model 7704A Tektronix scope.

3.3 Recording Time

Using an appropriate timing device, verify that the recording timeexceeds 30 minutes at the tape speed used for recording the 10Mbserial PCM data.

-4-

3.4 Output Data Format

Using the Model 7704A Tektronix scope, verify that the output signalis of the format in Figure 2, and that the output clock is of the correctphase.

3.5 Output Bit-to-Bit and Cummulative Jitter

Using the Model 7704A Tektronix scope, measure the bit-to-bit jittercummulative jitter of the crystal controlled 10Mb output clock, over400 clock pulses. Noter This data will be used to compare with theoutput data measured jitter. Add a second trace to the scope showingthe data. Repeat the measurement and record. The net difference isthe "uncorrectable" jitter.

3.6 Error Rate Test

3.6.1 Load the recorder with a pre-selected roll of 3M 971 tape.

3.6.2 Connect the equipment as shown in Figure 1.

3.6.3 Put the recorder in the record/reproduce mode and when up to speed,reset the error counter.

3.6.4 Continue recording for 30 minutes.

3.6.5 At the end of this time, record the number of errors. Divide thisnumber by (107) (60) (30) = 1.8 x 1010 to get the average errorrate. It shall be less than 10-6

-5-

10Mb Clock 16 Bit Pattern Error CounterGenerator and and

(HP 651A Osc.) --- Err-e. a Error Det. Frequency Meter

Special Test Jig HP Model 5302A

10 Mbps Clock NRZ to10Mbps BIO-L BIO-L Con-

verterSpecial TestJig )

INPUT

High Bit Rate

Mass Data Storage Device

Tektronix Model 7704AOscilloscope with

7A16A, 7A12, 7B71,10Mbps Data 7B70 Plug-ins

Output

EQUIPMENT TEST SET-UP

FIGURE 1

-6-

BI -L (ARBITRARY PATTERN)

CLOCK

SCLO CK LEADS DATA BY 10-30

FIGURE 2

ATP 204411

DATA SHEET

Verify Tolerance

3.1 OK See Figure 2

3.2 OK See Figure 2

3.3 3 O0 Minutes 30 Minutes Minimum

3.4 OK See Figure 2

Measurements

3.5

A. Short TermBit-to-Bit (Clock) ns N/A

B. 400 Bit Cummulative Ao(Clock) ns ,. $UFVAA 1 N/A

JiTTEi .C. Short Term

Bit-to-Bit (Data) ns N/A

D. 400 Bit Cummula-tive ns N/A

C-A j N 5 sC4E. A 0o 3 ns Maximum

D - B T rrE- 3 ns Maximum

3.6 Error Rate

A = No. of Errors/30 Min. I -/-2

A1.8 xl O O 7 ? ,- (lO) irs 10- 6 Maximum

-16 -73