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IMPLEMENTATION OFIMPLEMENTATION OF
DIGITAL PHASE LOCK DIGITAL PHASE LOCK LOOPLOOP
USING VHDLUSING VHDLImplementation of Phase Lock Loop using VHDL 1
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Group Members:Krunal Nandu – 0823125Sonali Desai – 0823142
Bhargav Shah – 0823144
Under the Guidance of:
Prof. (Mrs.) ANUDEEPA S. KHOLAPURE
Implementation of Phase Lock Loop using VHDL 2
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ContentsContents• Introduction to Phase Lock Loop • Why FPGA(Field Programmable Gate
Array)?• MATLAB Modeling & Simulation Results• VHDL – An Introduction• System Generator Block – Code
Conversion Process• Xilinx Synthesis• Hardware Simulation Results• Conclusion & Future Scope
Implementation of Phase Lock Loop using VHDL 3
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Introduction to PLL Introduction to PLL (Phase Lock Loop)(Phase Lock Loop)
Implementation of Phase Lock Loop using VHDL 4
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Implementation of Phase Lock Loop using VHDL 5
DPLL-Digital Phase Lock Loop Block
Diagram:
PFD : Phase / Frequency Detector VCO: Voltage Controlled Oscillator
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APPLICATIONS OF Phase Lock
Loops:• Clock Distribution• Frequency Synthesizers• AM Detection• FM Detector• Cell Phone Transceivers
Implementation of Phase Lock Loop using VHDL 6
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Implementation of Phase Lock Loop using VHDL 7
Clock Distribution:
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Implementation of Phase Lock Loop using VHDL 8
FREQUENCY SYNTHESIZERS:
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Implementation of Phase Lock Loop using VHDL 9
AM DETECTION:
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Implementation of Phase Lock Loop using VHDL 10
FM TRANSMITTER:
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Implementation of Phase Lock Loop using VHDL 11
FM DETECTOR:
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Why FPGA (Field Programmable
Gate Array)?
Implementation of Phase Lock Loop using VHDL 12
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Need of FPGA: COMPARISON OF LARGE SCALE
INTEGRATED CIRCUITS
Implementation of Phase Lock Loop using VHDL 13
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FPGA Architecture:
Implementation of Phase Lock Loop using VHDL 14
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FPGA vs. Microcontrollers:
• Microcontrollers are based on CPU architecture. As all CPUs, they execute instructions in a sequential manner.
• FPGAs are programmable logic and run in a parallel fashion.
• Microcontrollers have on-chip peripherals that also execute in parallel with their CPU. But they are still much less configurable than programmable logic.
Implementation of Phase Lock Loop using VHDL 15
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Advantages of FPGA• Time to Market• Performance• Cost• Reliability• Maintenance
Implementation of Phase Lock Loop using VHDL 16
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DPLL Block Diagram
Implementation of Phase Lock Loop using VHDL 17
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Phase Detection Circuit
Implementation of Phase Lock Loop using VHDL 18
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MATLAB Digital Phase Lock Loop Model
Implementation of Phase Lock Loop using VHDL 19
Delay:Latency = 5 (Z-5)
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Input Waveform
Implementation of Phase Lock Loop using VHDL 20
Input Waveform Characteristics:
Amplitude = 1v Period = 2sec
% Duty Cycle = 50
Phase delay = 0sec
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Input Delayed Waveform
Implementation of Phase Lock Loop using VHDL 21
Input Delayed Waveform Characteristics:
Phase Delay = 5sec
% Duty Cycle = 50
Period = 2sec
Amplitude = 1v
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Output Waveform
Implementation of Phase Lock Loop using VHDL 22
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Error Signal
Implementation of Phase Lock Loop using VHDL 23
Error Signal is low when there is a mismatch in phase of both inputs.
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VHDL – An VHDL – An IntroductionIntroduction
Implementation of Phase Lock Loop using VHDL 24
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Implementation of Phase Lock Loop using VHDL 25
Introduction• Hardware description languages (HDL)
o Language to describe hardwareo Two popular languages
• VHDL: Very High Speed Integrated Circuits Hardware Description LanguageoDeveloped by DOD from 1983o IEEE Standard 1076-1987/1993/200xoBased on the ADA language
• Verilogo IEEE Standard 1364-1995/2001/2005oBased on the C language
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Implementation of Phase Lock Loop using VHDL 26
Applications of Hardware Description Language
• Model and document digital systemsoDifferent levels of abstraction
• Behavioral, structural, etc.• Verify design• Synthesize circuits
oConvert from higher abstraction levels to lower abstraction levels
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Implementation of Phase Lock Loop using VHDL 27
Built-in Datatypes• Scalar (single valued) signal types:
o bito booleano integero Examples:
• A: in bit;• G: out boolean;• K: out integer range -2**4 to 2**4-1;
• Aggregate (collection) signal types:o bit_vector: array of bits representing binary numberso signed: array of bits representing signed binary numberso Examples:
• D: in bit_vector(0 to 7);• E: in bit_vector(7 downto 0);• M: in signed (4 downto 0); --signed 5 bit_vector binary number
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Implementation of Phase Lock Loop using VHDL 28
Input-Output specification of circuit
my_ckt
A
B
S
X
Y
Example: my_ckt Inputs: A, B, C Outputs: X, Y
VHDL description:
entity my_ckt is port (
A: in bit; B: in bit; S: in bit; X: out bit;
Y: out bit);
end my_ckt ;
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RTL Design Flow Chart
Implementation of Phase Lock Loop using VHDL 29
RTL : Register Transfer Level
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XiLiNX SysGen : XiLiNX SysGen : System GeneratorSystem Generator
Implementation of Phase Lock Loop using VHDL 30
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SysGen Design Flow Chart
Implementation of Phase Lock Loop using VHDL 31
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SysGen Toolbox in SIMULINK
Implementation of Phase Lock Loop using VHDL 32
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SysGen– Code Conversion
Implementation of Phase Lock Loop using VHDL 33
System Generator Block Parameters:
Compilation = HDL Netlist
Synthesis Tool = XST
HD Language = VHDL
FPGA Clock Period = 100ns
Simulink System period = 1s
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Spartan3 XC3S400 FPGA Trainer Kit:
Implementation of Phase Lock Loop using VHDL 34
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XC3S400 Specifications
Implementation of Phase Lock Loop using VHDL 35
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XiLiNX XiLiNX SynthesisSynthesis
Implementation of Phase Lock Loop using VHDL 36
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Xilinx Project Navigator Xilinx Project Navigator WindowWindow
Implementation of Phase Lock Loop using VHDL 37
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Implementation of Phase Lock Loop using VHDL 38
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RTL Schematic of the VHDL Code
Implementation of Phase Lock Loop using VHDL 39
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VHDL Design Summaryd_pll_cw Project Status Report
Project File: d_pll_cw.xise • Parser Errors: No Errors
Module Name: d_pll_cw • Implementation State:
Programming File Generated
Target Device: xc3s400-5pq208 • Errors: No Errors
Product Version: ISE 12.3 • Warnings: 32 Warnings (29 new)
Design Goal: Balanced • Routing Results: All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
• Timing Constraints: All Constraints Met
Environment: System Settings • Final Timing
Score: 0 (Timing Report)
Implementation of Phase Lock Loop using VHDL 40
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Conclusion & Future Scope
• The Digital PLL Model Using MATLAB & VHDL was successfully implemented on the FPGA kit.
• The input waveform seen on the CRO is tracked by the Digital PLL and it produces an output waveform with similar frequency characteristics.
• Although some amount of jitter is visible in the output waveform, we can further refine the same using high precision function generators and oscilloscopes.
Implementation of Phase Lock Loop using VHDL 41
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The work of design, simulation and layout is challenging and interesting. We learned a lot in this process, not only the knowledge about VHDL, but also the importance of teamwork. We felt excited when the simulation results are the same as what we expected, when our design passed the Synthesis process and especially when the programming window showed “PROGRAMMING SUCCEEDED”.
Implementation of Phase Lock Loop using VHDL 42
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Observation TableSr. No. Voltage Input Signal
FrequencyOutput Signal Frequency
1 3V 100 Khz 100 Khz2 3V 500 Khz 500 Khz3 3V 1 Mhz 1 Mhz4 3V 10 Mhz 10 Mhz
Implementation of Phase Lock Loop using VHDL 43
The lock in time of our model is very quick because of the simplicity of the design. If we design a more complex PLL, the lock-in time may be shorter.
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References• [1] A. Demir, E. Liu, A. Sangiovanni-Vincentelli, and I. Vassiliou.
Behavioral simulation techniques for phase/delay locked systems. Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 453-456, May 1994.
• [2] Crawford, Advanced Phase-Lock Techniques using Simulink, Artech House, 2008.
• [3] Douglas Perry, VHDL by Example, 4th Ed. 2004.• [4] F. Gardener, Phase Lock Techniques, Wiley Interscience
publications, 1979.• [5] Karris, Circuit Analysis with MATLAB Computing and Simulink/
SimPowerSystems Modeling, Orchard Publications 2009• [6] R.E. Best, Phase-Locked Loops - Design, Simulation, and
Applications, 4th Ed., McGraw-Hill, 1996.• [7] Volnei A, Pedroni, MIT Press, Circuit Design With VHDL, 2004.• [8] Xilinx Inc., "Spartan3E Starter Kit Board User Guide," UG230 vl.0,
Mar. 2006.• [9] Xilinx Inc., "Spartan3E FPGA Family: Complete Datasheet," DS312,
May. 2006.Implementation of Phase Lock Loop using VHDL 44
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THANK YOU!THANK YOU!
Implementation of Phase Lock Loop using VHDL 45