Final Exam Review - University of California, Berkeley · · 2009-12-15Overview of Course Circuit...
Transcript of Final Exam Review - University of California, Berkeley · · 2009-12-15Overview of Course Circuit...
EE40EE40
Final Exam ReviewFinal Exam Review
Prof Nathan CheungProf. Nathan Cheung12/01/2009
Practice with past examshttp://hkn.eecs.berkeley.edu/exam/list/?exam_course=EE%2040
Slide 1EE40 Fall 2009 Prof. Cheung
Overview of Course
Circuit components:R C L sources
Circuit analysis:Laws: Ohm’s, KVL, KCLR, C, L , sources
I-V characteristicsenergy storage/dissipation Equivalent circuits (series/
parallel Thevenin Norton)parallel, Thevenin, Norton)Superposition for linear circuitsNodal analysisM h l iMesh analysisPhasor I and V
First-order transient excitation/analysis:Second Order RLC circuits
Slide 2EE40 Fall 2009 Prof. Cheung2
Bode Plots
Overview of Course
Logic gates; Combinatorial logic (sum-of-products, Karnaugh maps), sequential logic etcsequential logic etc.
Semiconductors Devicespn-diodes (many types) FETs (n-channel, p-channel, CMOS)( , p , )
Useful Diode and FET circuits:Useful Diode and FET circuits: Amplifiers: op-amp (negative feedback), rectifiers; wave shaping circuits
Slide 3EE40 Fall 2009 Prof. Cheung3
Diode Circuit Analysis by Assumed Diode States
•1) Specify Ideal Diode Model or Piecewise-Linear Diode Model
ID (A) ID (A)
reverse biasforward bias
VD (V)reverse bias
forward bias
•2) Each diode can be ON or OFF
VD (V)VDon
•3) Circuit containing n diodes will have 2n states•4) The combination of states that works for ALL di d ( i t t ith KVL d KCL) ill b th
Slide 4EE40 Fall 2009 Prof. Cheung
diodes (consistent with KVL and KCL) will be the solution
Example Problem: Perfect Rectifier Model
Sketch V t versus ViSketch Vout versus Vin
Slide 5EE40 Fall 2009 Prof. Cheung
Suggested problem: What if there is a 0.6V drop when diodes are on ?
Diode with Capacitor Circuit (e.g.Level Shifter)
- VC + VIN VC
VOUT
+
VIN
+
C t
VIN(min)--
V (t)= V (t)+ V (t)VOUT 1 3
VOUT (t)= VC(t)+ VIN(t)t
2Finds out what happens to VCwhen VIN changes
1) Diode =open, VC(t)=0, VOUT (t)= VIN(t)2) Diode =short, VC(t)= -VIN(t) , VOUT(t)=0
when VIN changes
Slide 6EE40 Fall 2009 Prof. Cheung
3) Diode =open, VC(t)= -VIN(min), VOUT(t)= VIN(t)-VIN(min),
Example: Diode with RL Circuit
Sketch i(t)
Answer
L/R 0 05
Note: i(t) is continuous
Slide 7EE40 Fall 2009 Prof. Cheung
τ = L/R = 0.05 msec
Load-Line AnalysisWe have a circuit containing a two-terminal non-linear element “NLE”, and some linear components.
Then define I and V at the NLE terminals (typically associated signs)
First replace the entire linear part of the circuit by its Thevenin equivalent.
Then define I and V at the NLE terminals (typically associated signs)
ID
1V+
250KNon-linear element
9µA1M
D
+2V
200K
S
NL
D ID
VDS+ -1V-
S
element - 2VSE -
Slide 8EE40 Fall 2009 Prof. Cheung
Example of Load-Line Analysis (con’t)
And have this connected to a linear
Given the graphical properties of two terminal non-linear circuit (i.e. the graph of a two terminal device)
D IDAnd have this connected to a linear (Thévenin) circuit Whose I-V can also be graphed on the same axes (“load line”) +
2V200K
S
NL
D ID
VDS+ -on the same axes ( load line )
Application of KCL, KVL gives circuit solution
- 2VSE
200K The solution
ID (µA)10
IDDNL +
- 2VThe solution !
LE S
Slide 9EE40 Fall 2009 Prof. CheungVDS(V)1 2
Example : Voltage controlled Attenuator
VC and RCDetermines rd atdQ point of diode
Slide 10EE40 Fall 2009 Prof. Cheung
Example : Voltage Controlled Attenuator
The large capacitors and DC bias source are effective shorts
Slide 11EE40 Fall 2009 Prof. Cheung
for the ac signal in small-signal circuits
Three-Terminal Parametric Graphs
ID (µA)103-Terminal
Device
IDDG
VGS = 3
S
VGS+-
VGS = 2
VGS = 1
VDS(V)1 2Concept of 3-Terminal Parametric Graphs:
We set a voltage (or current) at one set ofWe set a voltage (or current) at one set of terminals (here we will apply a fixed VGS, IG=0)
and conceptually draw a box around the device ith l t t i l iwith only two terminals emerging so we can
again plot the two-terminal characteristic (here ID versus VDS).
Slide 12EE40 Fall 2009 Prof. Cheung12
But we can do this for a variety of values of VGSwith the result that we get a family of curves.
Graphical Solutions for 3-Terminal DevicesIID (µA)
10VGS = 3
IDG
++V
D200K
VGS = 2
VGS = 1
- +-
V2V
SWe can only find a solution for
First select VGS (e.g. 2V) and draw ID vs VDS for the 3-Terminal device.
VDS(V)1 2ID (µA)
one input (VGS) at a time:
Now draw ID vs VDS for the 2V -200KΩ Thevenin source.
D (µ )10
The solution !
The only point on the I vs V plane which obeys KCL and KVL is ID = 5µA at VDS = 1V.
!
Slide 13EE40 Fall 2009 Prof. Cheung13VDS(V)1 2
KVL is ID 5µA at VDS 1V.
SOLVING MOSFET CIRCUITS: STEPS
1) Guess the mode of operation for the transistor. (We will learn how to make educated guesses).
2) Write the ID vs. VDS equation for this guess mode of operation.
3) Use KVL, KCL, etc. to come up with an equation relating ID and VDS based on the surrounding linear circuit.
4) Solve these equations for ID and VDS.
5) Check to see if the values for ID and VDS are possible for the mode you guessed for the transistor. If the values are possible for the mode guessed, stop, problem solved. If the values are
Slide 14EE40 Fall 2009 Prof. Cheung
g , p, pimpossible, go back to Step 1.
CHECKING THE ANSWERS
NMOS 1) VGS > VT(N) in triode or saturationVGS ≤ VT(N) in cutoffTriodeSaturationCut-off
•2) VDS < VGS – VT(N) in triode VDS ≥ VGS – VT(N) in saturationDS tov V+0
GSvTriodeCut-off
toVDS ≥ GS T(N)
PMOS1) VGS < VT(P) in triode or
PMOS saturationVGS ≥ VT(P) in cutoff
2) VDS > VGS – VT(P) in triode Triode Saturation Cut-off ) DS GS T(P)
VDS ≤ VGS – VT(P) in saturation
DS tov V+ 0GSv
toV
Slide 15EE40 Fall 2009 Prof. Cheung
DS to to
Example Problem : MOSFET Circuit
Slide 16EE40 Fall 2009 Prof. Cheung
Example Problem : MOSFET Circuit
Find VGS such that VDS=2V
AnswerGuess Saturation Mode
Check: V (=2V) > V -V (=1 5-0 5=1V)
Slide 17EE40 Fall 2009 Prof. Cheung
VDS(=2V) > VGS-VT (=1.5-0.5=1V)MOSFET indeed is in saturation mode
Example Problem : MOSFET Circuit
Find small-signal model parameters
=10-5 Siemens
Slide 18EE40 Fall 2009 Prof. Cheung
How do you guess the right mode ?
Often, the key is the value of VGS.
(We can often find VGS directly without solving the whole circuit )(We can often find VGS directly without solving the whole circuit.)
I
VGS ≤ VT(N)
IDVGS = VT(N) + εb bl i
ID
VGS ≤ VT(N)
definitely cutoffprobably saturation
VDS VDSVGS - VT(N) = ε
Slide 19EE40 Fall 2009 Prof. Cheung
How do you guess the right mode ?
t i d d t ti d
When VGS >> VTH(N), it’s harder to guess the mode.
I triode mode saturation modeID
VGS - VTH(N)
If ID is small, probably triode mode
Slide 20EE40 Fall 2009 Prof. CheungVDS
EXAMPLE
1.5 kΩ1) Since VGS > VTH(N), not in cutoff mode. Guess saturation mode.
D
ID+
2) Write transistor ID vs. VDS:( )V1V310250II 26
tDsaD −•== −
G +
VDS
+_4 V
( )mA1
tDsaD
=
S
_+_3 V
3) Write ID vs. VDS equation using KVL:
04Ω Ik1 5VGIVEN: VTH(N) = 1 V, K= 250 µA/V2
0V4 =+•Ω DDS Ik1.5-V-
Slide 21EE40 Fall 2009 Prof. Cheung
K 250 µA/V , λ = 0 V-1.
EXAMPLE
1.5 kΩ4) Solve VDS:
D
ID+
ID = 1mA VDS = 2.5 V
5) Check:G +
VDS
+_4 V
5) Check:
ID and VDS are correct sign, and V ≥ V V i d i
S
_+_3 V
VDS ≥ VGS-VT(N) as required in saturation mode.
GIVEN: VTH(N) = 1 V, ½ W/L µ C = 250 µA/V2
Slide 22EE40 Fall 2009 Prof. Cheung
½ W/L µnCOX 250 µA/V , λ = 0 V-1.
WHAT IF WE GUESSED THE MODE WRONG?
1) Since VGS > VTH(N), not in cutoff mode. Guess triode mode.
D
1.5 kΩ2) Write transistor ID vs. VDS:
GID
++4 V
ID = 2·250·10-6(3 – 1 – VDS/2)VDS
VDS_+
_
3 V3) Write ID vs. VDS equation using
KVL:S
_3 V
GIVEN: VTH(N) = 1 V, 0V4 =+•Ω DDS I k 1.5-V-
Slide 23EE40 Fall 2009 Prof. Cheung
TH(N)K= 250 µA/V2, λ = 0 V-1.
WHAT IF WE GUESSED THE MODE WRONG?
1.5 kΩ4) Solve for VDS with quadratic
equation by combining 2) and 3):
D
ID+VDS = 4 V, 2.67 V
G +
VDS
+_4 V 5) Check:
VDS > VGS – VT(N) = 2VN ith l lid i t i d d !
S
_+_3 V
Neither value valid in triode mode!Guess is incorrect.
GIVEN: VTH(N) = 1 V, K 250 A/V2
Slide 24EE40 Fall 2009 Prof. Cheung
K= 250 µA/V2, λ = 0 V-1.
Another Perspective
In this circuit, the transistor delivered a constant current IDSATto the 1 5 kΩ resistor
This circuit acts like a constant current source, as long as the transistor remains in saturationto the 1.5 kΩ resistor. transistor remains in saturation mode.IDSAT does not depend on the tt h d i t if t ti
D
1.5 kΩattached resistance if saturation is maintained.
GID
++4 V
VDS_+
_
3 VIDSAT 1.5 kΩ
Slide 25EE40 Fall 2009 Prof. Cheung
S_3 V
Another Perspective
IDSAT does depend on VGS; one can adjust the current supplied by adjusting V
The circuit will go out of saturation mode if• VGS < VT(N) oradjusting VGS. VGS < VT(N) or• VDS < VGS – VT(N)
This can happen if VGS is too
D
RL
This can happen if VGS is too large or too small, or if the load resistance is too large.
GID
++VDD
VDS_+
_
VIDSAT RL
Slide 26EE40 Fall 2009 Prof. Cheung
S_VGS
ANOTHER EXAMPLE
1.5 kΩ1) What is VGS?No current goes into/out gate.VGS = 3 V by voltage division2 kΩ
G
DID+
4 V
VGS 3 V by voltage division.Guess saturation (randomly).
2) Write transistor I vs V :
2 kΩ
+
VDS
_4 V 2) Write transistor ID vs. VDS:
6 kΩ( )V 1V 310250II 26
tDsaD −•== −
S
_
3) Write ID vs. VDS equation using
6 kΩmA1=
GIVEN: VTH(N) = 1 V, K= 250 µA/V2, λ = 0 V-1
KVL:0V4 =+•Ω DDS I k 1.5-V-
V =2 75V consisitent with saturation mode
Slide 27EE40 Fall 2009 Prof. Cheung
λ = 0 V 1.Effectively the same circuit as previous example: only 1 voltage source in this case
VDS=2.75V consisitent with saturation mode
The CMOS Inverter: Current Flow
VOUT
N: off
N: satP: sat ii
VDD
N: offP: Triode C
SG
VDD
N: satP: Triode
A B D EI
S
D
G
VOUTVIN
N: TriodeP: sat
A B D EG S
D
VIN0
N: TriodeP: off
P: sat
Slide 28EE40 Fall 2009 Prof. Cheung
VINVDD00
Another CMOS Example: The LATCH
VDDVDD Data (VIN) is written to the internal node (V )
CLK CLKinternal node (VOUT_INT) when the clock is low. VOUT remains frozen.
VOUT VOUT_INT VIN
OUT
When the clock is high.The (inverted) internal node voltage is written to V The internal node
CLK CLK
VOUT. The internal node VOUT_INT remains frozen
Slide 29EE40 Fall 2009 Prof. Cheung
THE LATCH
VDDVDD When CLK is low the left-hand transistors conduct. The
CLK CLK right-hand transistors are open.
VOUT INT is charged to VIN.0 V VDD
VOUT VOUT_INT VIN
OUT_INT g IN
VOUT remains the same; there is no charging path.
CLK CLK
V 0 V
Slide 30EE40 Fall 2009 Prof. Cheung
VDD 0 V
THE LATCH
VDDVDD When CLK is high, the right-hand transistors
CLK CLK conduct. the left-hand transistors are open.
VDD 0 V
VOUT VOUT_INT VIN
p
VOUT is changed to VOUT INT.
CLK CLKVDD0 V
VOUT_INT remains the same; there is no charging path
Slide 31EE40 Fall 2009 Prof. Cheung
VDD0 V there is no charging path.
CONCEPT OF STATE
VDDVDD A latch stores a “1” or “0”.
CLK CLK The stored value is known as the “state”.
CurrentState
NextStateVIN
This is one of the basic elements neededbasic elements needed to make a “state machine” (covered in
CLK CLK
(EE 20 and CS 61C).
Slide 32EE40 Fall 2009 Prof. Cheung
LATCH AS GATEKEEPER
A signal may have to go through a complex system of gates, with paths of different delays: possibility of false output!
Combinatorial Logic Sequential ElementP t h i
Slide 33EE40 Fall 2009 Prof. Cheung
Signal propagates all the way through Includes our logic gates: NAND, NOT, etc.
Prevents changes in output until signaled
Amplifier EfficiencyPower Supply A
Load
SourcePi = (10-3V)2/105Ω
LoadSource =10-11 W
Load(8 )2/8
Amplifier
P0 = (8V)2/8Ω=8 W
Power Supply BPower SuppliesPs = 15W+7.5W
= 22 5 W= 22.5 WAmplifierP = 22 5W+10-11W-8WAmplifier Efficiency η
Slide 34EE40 Fall 2009 Prof. Cheung
Pd = 22.5W+10 W-8W= 14.5 W= 8/22.5 =36%
Differential Signal and Common Mode Signal
Redefine the inputs in terms of two other voltages:1. differential mode input vid ≡ vi1 – vi2
2 d i t ( + )/22. common mode input vicm ≡ (vi1 + vi2)/2
so that( /2) d ( /2)vi1 = vicm + (vid/2) and vi2 = vicm - (vid/2)
iidd vAvAv += icmcmiddo vAvAv +
ff “common mode gain”
“differential mode gain”
Slide 35EE40 Fall 2009 Prof. Cheung
Common Mode Rejection Ratio
dAlog20)dBin(CMRR =
cmAlog20)dBin(CMRR =
ExampleExample
•Differential signal from sensor = 1mV (peak).g (p )We want outputs signal > 1V implies Ad> 1000•Common mode signal =100V (from power line).We want common mode signal < 0.1V impliesAcm <10-4
Therefore CMRR needs to be > 20log(107)= 140dB
Slide 36EE40 Fall 2009 Prof. Cheung
Therefore CMRR needs to be > 20log(107)= 140dB
Offset Voltage, Offset Current, and Bias Current
GivenVoff=2mVI 100 AIB= 100nAIoff= 20nAAcm=1Ad=100Both input terminals to ground
Use superpositionterminals to ground through 100kΩresistors
Slide 37EE40 Fall 2009 Prof. Cheung
Vo = Ad(Vvoff+VIoff)+ Acmvicm= 100(0.001667+0.001667)+1(0.01)=0.3343V