Filename: “AET_ch5”

Model Structure

Models consists of an Entity Declaration and Architecture Body.

1.1 Entity Declaration

The Entity Declaration names entity and defines interface between entity and its environment. The syntax is:

ENTITY entity_name IS[GENERIC (generic_list);][PORT clause;]

END [entity_name];

Generic_list specifies static information to be communicated to a model from its environment for all architectures.

PORT clause indentifies ports used by entity to communicate with its environment. Its syntax is:

PORT (name_list: mode type;….; name_list: mode type);

Name_list identifies objects, can be QUANTITY, TERMINAL or SIGNAL.

SIGNAL objects use the MODE IN, OUT, INOUT ande BUFFER --default objects QUANTITY objects can use IN and OUT. It represents analog variable. TERMINAL objects have no direction mode. It represents node that satisfies conservation law,

such Kirchoff’s law, conservation of energy.

Mode type indentifies direction of data flow through port. The allowable modes are:

IN --flow is into entity, can be read but not updated within the model OUT --flow is out of entity, can be updated but no read within the model INOUT --flow may be either in or out, can be both read and updated within the model BUFFER --flow is out of entity, but its value can be read internally. In SIMPLORER

transformed --to INOUT

Example:

ENTITY and_gate ISPORT(a, b : IN BIT; q: OUT BIT); --a, and b are SIGNALs

END and_gate;

1.2 Architecture Body

Architecture body establishes relationship between inputs and outputs of design. The syntax is:

ARCHITECTURE arch_name OF entity_name IS--declaration statements;

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BEGIN--concurrent statements;

END [arch_name];

Example:

ARCHITECTURE arch_and_gate OF and_gate ISBEGIN

q <= a AND b;END arch_and_gate;

1.3 Example of INOUT Mode Type

Synthesis of asynchronous circuit from a given state transition table.

Q(t+1)Q(t)y1y2

x=0Y1Y2

x=1Y1Y2

00 00 0101 01 1010 10 1111 11 00

Where x is the input, y1y2 is the present state, and Y1Y2 is the next state. Convert the table to a table lookup as follows:

xy1y2 Y1Y2000 00001 01010 10011 11100 01101 10110 11111 00

When implementing this if we don’t distinguish the present state from the next state by using the same state variables y1y2 for both, then the state variables will both appear as input as well as output of the state machine, INOUT ports are required. The VHDL implementation is given below:

Using the “IEEE.STD_LOGIC_SIGNED” package

1. LIBRARY IEEE;2. USE IEEE.STD_LOGIC_1164.ALL;3. USE IEEE.STD_LOGIC_SIGNED.ALL;4. 5. ENTITY asyn_ctr IS6. PORT(x:IN STD_LOGIC; y1, y2:INOUT STD_LOGIC);7. END asyn_ctr;8. 9. ARCHITECTURE arch_asyn_ctr OF asyn_ctr IS

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10. TYPE array_2d IS ARRAY(0 TO 7, 0 TO 1) OF STD_LOGIC;11. BEGIN12. PROCESS(x, y1, y2)13. VARIABLE mem : array_2d := ((‘0’,’0’), (‘0’,’1’),(‘1’,’0’),(‘1’,’1’),14. (‘0’,’1’), (‘1’,’0’), (‘1’,’1’), (‘0’,’0’));15. BEGIN16. y1 <= mem(CONV_INTEGER(‘0’x&y1&y2),0);17. y2 <= mem(CONV_INTEGER(‘0’&x&y1&y2 ),1);18. END PROCESS;19. END arch_asyn_ctr;

Using the “IEEE.STD_LOGIC_UNSIGNED” package,

20. LIBRARY IEEE;21. USE IEEE.STD_LOGIC_1164.ALL;22. USE IEEE.STD_LOGIC_UNSIGNED.ALL;23. 24. ENTITY asyn_ctr IS25. PORT(x:IN STD_LOGIC; y1, y2:INOUT STD_LOGIC);26. END asyn_ctr;27. 28. ARCHITECTURE arch_asyn_ctr OF asyn_ctr IS29. TYPE array_2d IS ARRAY(0 TO 7, 0 TO 1) OF STD_LOGIC;30. BEGIN31. PROCESS(x, y1, y2)32. VARIABLE mem : array_2d := ((‘0’,’0’), (‘0’,’1’),(‘1’,’0’),(‘1’,’1’),33. (‘0’,’1’), (‘1’,’0’), (‘1’,’1’), (‘0’,’0’));34. BEGIN35. y1 <= mem(CONV_INTEGER(x&y1&y2),0);36. y2 <= mem(CONV_INTEGER(x&y1&y2 ),1);37. END PROCESS;38. END arch_asyn_ctr;

Using Karnaugh map to the above state transition table one can simplify the next state equations to:

Y1 = y1* NOT(y2) + y2 * (x XOR y1)Y2 = x XOR y2

Its corresponding VHDL implementation is given below:

ARCHITECTURE arch2_asyn_ctr OF asyn_ctr ISBEGIN

y1 <=( y1 AND NOT(y2)) OR (y2 AND (x XOR y1));y2 <= x XOR y2;

END arch2_asyn_ctr;

Autologic VHDL, however requires that INOUT ports to be bi-directional ports driven by tri-state drivers. They can be driven internally or externally and must be of the kind BUS.

SR Flip Flop Example:

s r q Q

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0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 X1 1 1 X

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_SIGNED.ALL;

ENTITY srff ISPORT(s,r : IN STD_LOGIC; q : INOUT STD_LOGIC);

END srff;

ARCHITECTURE t_srff OF srff IS TYPE array_1d IS ARRAY(0 TO 7) OF STD_LOGIC; BEGIN PROCESS(s, r, q)

VARIABLE x: STD_LOGIC;VARIABLE y: STD_LOGIC_VECTOR(3 DOWNTO 0);VARIABLE mem : array_1d:=('0','1','0','0','1','1','X','X');

BEGINy:='0' & s & r & q;x:=TO_INTEGER(y);

q <= mem(x); END PROCESS;END t_srff

Karnaugh map can be used to obtain an optimum hardware implementation.rq

s 00 01 11 100 0 1 0 01 1 1 X X

Q = s + r’q = s + (r + q’)’

Figure 1 shows two possible implementations using OR gates or NAND gates.

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Figure 1 SR Flip Flop implementation: (a) with OR gates, (b) with NAND gates.

1.4 Example of BUFFER Mode Type

Buffer ports are simply out ports whose value can be read internally. They are used when you have values that are calculated and used internally, but are also being passed to the outside world. Instead of BUFFER port, you can achieve the same results using an OUT port with an intermediate signal.

The following VHDL codes yield the same hardware synthesis:

Implementation 1:

1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 4 ENTITY buff_port IS5 PORT(i1, i2: IN BIT; o1: BUFFER BIT; o2: OUT BIT);6 END buff_port; 7 ARCHITECTURE arch_buff_port OF buff_port IS8 BEGIN9 o1 <= NOT i1; --o1 is being outputted10 o2 <= i2 AND o1; --o1 is being read11 END arch_buff_port;

Implementation 2:

1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 4 ENTITY buff_port IS5 PORT(i1, i2: IN BIT; o1: OUT BIT; o2: OUT BIT);6 END buff_port; 7 ARCHITECTURE arch_buff_port OF buff_port IS8 SIGNAL temp: BIT;9 BEGIN10 temp <= NOT i1;11 o1 <= temp; --o1 is being outputted12 o2 <= i2 AND temp;13 END arch_buff_port;

Both yield the following synthesized circuit:

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Figure 2. Hardware implementation of internal signal that is also outputted.

Another example, implementing a D-type flip flop without using Buffer data type:

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff ISPORT(d, clk : IN STD_LOGIC:='X';

q : OUT STD_LOGIC:='X'; qb : OUT STD_LOGIC:='X');

END dff;

ARCHITECTURE arch_dff OF dff ISBEGIN

PROCESS(clk)BEGIN

IF(clk'EVENT AND clk='1')THENq <= d;qb <= NOT d;

END IF;END PROCESS;

END arch_dff;

Figure 3. DFF coding that resulted in two flip flops.

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Using temp signal and out ports:

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff ISPORT(d, clk : IN STD_LOGIC:='X';

q : OUT STD_LOGIC:='X'; qb : OUT STD_LOGIC:='X');

END dff;

ARCHITECTURE arch_dff OF dff ISSIGNAL tmp : STD_LOGIC;

BEGINPROCESS(clk)BEGIN

IF(clk'EVENT AND clk='1')THENtmp <= dq <= tmp;qb <= NOT tmp;

END IF;END PROCESS;

END arch_dff;

Figure 4. DFF coding that resulted in three flip flops.

Note each signal assignment is implemented by a dff.

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff ISPORT(d, clk : IN STD_LOGIC:='X';

q : BUFFER STD_LOGIC:='X'; qb : OUT STD_LOGIC:='X');

END dff;

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ARCHITECTURE arch_dff OF dff ISBEGIN

PROCESS(clk)BEGIN

IF(clk'EVENT AND clk='1')THENq <= d;qb <= NOT q;

END IF;END PROCESS;

END arch_dff;

Figure 5. DFF coding that resulted in two flip flops.

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff ISPORT(d, clk : IN STD_LOGIC:='X';

q : BUFFER STD_LOGIC:='X'; qb : OUT STD_LOGIC:='X');

END dff;

ARCHITECTURE arch_dff OF dff ISBEGIN

PROCESS(clk)BEGIN

IF(clk'EVENT AND clk='1')THENq <= d;

END IF;END PROCESS;qb <= NOT q;

END arch_dff;

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Figure 6. DFF coding that resulted in one flip flop, the desired code.

To achieve a single dff implementation the qb signal must be moved out of the process. That is its assignment is not sensitive to clk but only to changes in q. Hence it is implemented as the negation of q.

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff ISPORT(d, clk : IN STD_LOGIC:='X';

q, qb : OUT STD_LOGIC:='X');END dff;

ARCHITECTURE arch_dff OF dff ISSIGNAL q_temp: STD_LOGIC;

BEGINPROCESS(clk)BEGIN

IF(clk'EVENT AND clk='1')THENq_temp <= d;

END IF;END PROCESS;q <= q_temp;qb <= NOT q_temp;

END arch_dff;

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY dff ISPORT(d, clk : IN STD_LOGIC:='X';

q, qb : OUT STD_LOGIC:='X');END dff;

ARCHITECTURE arch_dff OF dff ISBEGIN

PROCESS(clk)VARIABLE q_temp : STD_LOGIC;

BEGINIF(clk'EVENT AND clk='1')THEN

q_temp := d;END IF;q <= q_temp;qb <= NOT q_temp;

END PROCESS;END arch_dff;

These are both implemented with one dff as shown above.

1.5 Concurrent Statements

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Concurrent statements are executed concurrently the order of their presentation is irrelevant. A model’s architecture is made up of one or more concurrent statements. Each concurrent statement represents a unit of functionality. The concurrent statements are:

BLOCK Statement PROCESS Statement ASSERTION Statement Concurrent Signal Assignment Statement Concurrent Procedure Call Component Instantiation Generate Statement BREAK statement --New in VHDL-AMS Simultaneous Statements --New in VHDL-AMS

1.5.1 BLOCK Statement

A BLOCK statement groups related concurrent statements. The order of the concurrent statements does not matter, because all statements are always executed together. If a guard expression appears after the reserved word BLOCK, a Boolean variable GUARD is automatically defined and set to the boolean value of the guard expression. GUARD can then be tested within the block, to perform selected signal assignments or other statements only when the guard condition evaluates to TRUE.

Syntax:

[label_name:]BLOCK [(guard expression)]

Local declarationsBEGIN

Concurrent statementsEND BLOCK [label_name];

Example:

--D Latch Transfer D input to Q output when Enable = ‘1’B1:BLOCK (Enable =’1’)

Q <= guarded D AFTER 5ns;END BLOCK B1;

1.5.2 PROCESS Statement

A PROCESS statement contains sequential statements but is itself a concurrent statement within an architecture. The sequential statements in the process are executed in order until suspended. Statements within a PROCESS are executed in the order they are written. Each PROCESS represents a block of logic, and all PROCESSes execute in parallel. Of course, if the simulator is running on a single processor, they actually execute in turn, but the observed effect from a simulation point of view is that they execute in parallel. In VHDL, a process is activated when a signal in its sensitivity list changes. The process sensitivity list is equivalent to WAIT ON statement. If WAIT ON statement is used in a process, the signals used on the WAIT statement may not appear on the sensitivity list.

Syntax:

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[label_name:]PROCESS [(sensitivity list)]

Local declarationsBEGIN

Sequential statementsEND PROCESS [label_name];

Example 1:

PROCESS (a, b)BEGIN

q <= a AND b;END PROCESS;

Is equivalent to:

PROCESSBEGIN

q <= a AND b;WAIT ON a, b;

END PROCESS;

Example 2: Modeling Concurrency

Figure 7.

The modeling of logic circuits has a requirement that the model must include provision for concurrency of execution, since logic signals flow in parallel. Figure 7 illustrates this concept. Three logic blocks are shown. If one assumes that input set 1 and input set 2 are activated simultaneously, logic block 1 and 2 will be activated together. Logic block 3 will be activated as soon as either of the outputs from logic block 1 (q1) or logic block 2 (q2) change. While signals are propagating their way through block 3, new input signal changes can be propagating their way through block 1 and 2. Thus signal flow can take place through all blocks simultaneously. In VHDL, usually each process statement represents a block of logic, and all processes execute in parallel. Figure 7 is coded as follows:

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1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 4 ENTITY conc_model IS5 PORT(a1, b1, a2, b2 : IN BIT; q : OUT BIT);6 END conc_model;7 8 ARCHITECTURE arch_conc_model OF conc_model IS9 SIGNAL q1, q2 : BIT;10 BEGIN11 logic_block1: PROCESS(a1, b1)12 BEGIN13 q1 <= a1 AND b1;14 END PROCESS logic_block1;15 16 logic_block2: PROCESS (a2, b2)17 BEGIN 18 q2 <= a2 NOR b2;19 END PROCESS logic_block2;20 21 logic_block3: PROCESS (q1, q2)22 BEGIN23 q <= q1 XOR q2;24 END PROCESS logic_block3;25 END arch_conc_model;

Note that the sensitivity list for the process contains the input signal set for the logic block. Each process is activated when a signal in its sensitivity list changes. Since the process represents a physical system, it cannot execute the signal assignment in zero time. Without the delay specification in the signal assignment, we say that the process executes in “delta” time, a value of time that is infinitesimally small but greater than zero. Its value corresponds to one simulation cycle. Fundamentally, a simulation model consists of a set of processes. During the execution of a simulation cycle, all processes whose inputs have changed since the last cycle are evaluated. Signal outputs from those processes are scheduled to occur at later simulation times. Once all processes have been executed, the simulation cycle is complete. The next simulation cycle starts the next time a signal input to a process changes.

The above implementation is equivalent to the implementation shown below. Each process is replaced by a single signal assignment statement. This is possible because each process models a simple gate. In other words, each signal assignment can be considered as a process with the sensitivity list consisting of the signals on the right hand side of the signal assignment.

1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 4 ENTITY conc_model5 PORT(a1, b1, a2, b2 : IN BIT; q : OUT BIT);6 END conc_model; 7 8 ARCHITECTURE arch_conc_model OF conc_model IS9 SIGNAL q1, q2 : BIT;10 BEGIN11 q1 <= a1 AND b1;12 q2 <= a2 NOR b2;13 q <= q1 XOR q2;14 END arch_conc_model;

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1.5.3 Assignment Statement Execution

The execution of signal assignment depends on whether it is in a concurrent statement section or within the sequential statement section inside a process. To understand this, let us look at an example.

PROCESS (r, s)BEGIN

a <= x AND y; -- statement S1b <= a OR z; -- statement S2

END PROCESS;

If S1 and S2 are not within a process, S1 is executed whenever x or y changes; S2 is executed whenever a or z changes. Within the process statements S1 and S2 are both executed when a change occurs on r or s. The right-hand side of these statements will use the present values of x, y, z, and a to compute the value of a and b.

1.6 GENERATE Statement

Generate statements provide the ability to describe regular and/or slightly irregular structures by automatically generating component instantiations instead of manually writing each instantiation. There are two kinds of generate statements: iteration and conditional. An iterate generate statement is also called a for generate statement; a conditional generate statement is also called an if generate statement. The for generate statement is similar to a for loop statement. There are two syntax for generate statement:

Syntax 1GenLabel: --Iterate generate labelFOR i IN 7 DOWNTO 0 GENERATE

--sequential statements

END GENERATE GenLabel;

Syntax 2 GenLabel: --conditional generate label

IF (condition) GENERATE--sequential statements

END GENERATE GenLabel;

LIBRARY work;USE work.all;LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;

ENTITY compare8 IS

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PORT (a, b : IN BIT_VECTOR(7 DOWNTO 0);c_in : IN BIT_VECTOR(1 DOWNRO 0);c_out : OUT BIT_VECTOR(1 DOWNTO 0));

END compare8;

Manual Structural Modelling

ARCHITECTURE man_struct OF compare8 ISCOMPONENT bit_compare

PORT(a, b, c_in1, c_in0: IN BIT; cc_out1, c_out0: OUT BIT));

END COMPONENT;SIGNAL c_int1, c_int0: BIT_VECTOR(7 DOWNTO 1);FOR ALL : bit_compare USE ENTITY work.bit_compare(logic);

BEGINC7: bit_compare PORT MAP(a(7), b(7), c_in(1), c_in(0), c_int1(7), c_int0(7));C6: bit_compare PORT MAP(a(6), b(6), c_int1(7), c_int0(7), c_int1(6), c_int0(6));C5: bit_compare PORT MAP(a(5), b(5), c_int1(6), c_int0(6), c_int1(5), c_int0(5));C4: bit_compare PORT MAP(a(4), b(4), c_int1(5), c_int0(5), c_int1(4), c_int0(4));C3: bit_compare PORT MAP(a(3), b(3), c_int1(4), c_int0(4), c_int1(3), c_int0(3));C2: bit_compare PORT MAP(a(2), b(2), c_int1(3), c_int0(3), c_int1(2), c_int0(2));C1: bit_compare PORT MAP(a(1), b(1), c_int1(2), c_int0(2), c_int1(1), c_int0(1));C0: bit_compare PORT MAP(a(0), b(0), c_int1(1), c_int0(1), c_out(1), c_out(0));

END man_struct;

Generated Structural ModellingARCHITECTURE gen_struct OF compare8 IS

COMPONENT bit_comparePORT(a, b, c_in1, c_in0: IN BIT; c

c_out1, c_out0: OUT BIT));END COMPONENT;SIGNAL c_int1, c_int0: BIT_VECTOR(7 DOWNTO 1);

BEGINCASCADE: --Iteration generateFOR i IN 7 DOWNTO 0 GENERATEINPUT_CASE:IF (i=7) GENERATE

C7: bit_compare PORT MAP (a(i), b(i), c_in(1), c_in(0), c_int1(i), c_int0(i));END GENERATE INPUT_CASE;

NORMAL_CASE:IF(i<=6 AND i>=1) GENERATE

CX: bit_compare PORT MAP(a(i), b(i), c_int1(i+1), c_int0(i+1), c_int1(i), c_int0(i));END GENERATE NORMAL_CASE;

OUTPUT_CASE:IF(I=0) GENERATE

C0: bit_compare PORT MAP (a(I), b(I), c_int1(I+1), c_int0(I+1), c_out(1), c_out(0));END GENERATE OUTPUT CASE;END GENERATE CASCADE;

END gen_struct;

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1.7 BREAK Statement

BREAK statement indicates explicitly the occurrence of discontinuities in a VHDL-AMS.

Bouncing Ball Example1:

LIBRARY IEEE;USE IEEE.ENERGY_SYSTEMS.ALL; --need this one to use GRAV =9.81 m/s**2USE IEEE.MECHANICAL_SYSTEMS.ALL;

ENTITY BounceBall ISGENERIC (

Air_Res: REAL := 0.1); --1/mEND ENTITY BounceBall;

ARCHITECTURE ideal OF bounceball ISQUANTITY v: velocity; -- m/sQUANTITY s: displacement; --m

BEGIN-- Specify initial conditionsBREAK v => 0.0, s => 10.0;-- Announce discontinuity and reset velocity valueBREAK v => -v WHEN NOT s'ABOVE(0.0);s'DOT == v;IF v>0.0 USE

v'DOT == -GRAV - v**2*Air_Res tolerance "ACCELERATION";ELSE

v'DOT == -GRAV + v**2*Air_Res tolerance "ACCELERATION";END USE;

END ARCHITECTURE ideal;

BouncingBall

bounceball1

air_res := 0.0

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bounceball1.s

t [s] 0 61 2 3 4 5

BouncingBall

bounceball1

air_res := 0.1

bounceball1.s

t [s] 0 61 2 3 4 5

1.8 Simultaneous StatementsSimultaneous statements are new class of statements in VHDL 1076.1. Simultaneous statements are concurrent statements used to express Differential Algebraic Equations (DAE) that together with implicit equations describe the analog behavior of a model. The five simultaneous statements are:

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Simple Simultaneous Statement Simultaneous IF Statement Simultaneous CASE Statement Simultaneous PROCEDURAL Statement Simultaneous NULL Statement

1.8.1 Simple Simultaneous Statement

A simple simultaneous statements express relationships between quantities

Left-hand side and right-hand side must be expressions with scalar sub-elements of a floating point type

Statement is symmetrical w.r.t. its left-hand and right-hand sides Expressions may involve quantities, constants, literals, signals, and possibly user-defined

functions At least one quantity must appear in a simultaneous statement

Syntax:[label_name:]expression = = expression;

Example:

Figure 7. Battery ModelLIBRARY IEEE;USE IEEE.ELECTRICAL_SYSTEMS.ALL;ENTITY batt IS

GENERIC(factor : REAL :=1.0;v_init : REAL := 12.0);

PORT (TERMINAL p, m : ELECTRICAL;QUANTITY v_out : OUT REAL :=0.0);

END ENTITY batt;

ARCHITECTURE behav OF batt ISTERMINAL t1, t2: ELECTRICAL;QUANTITY v_ri ACROSS i_ri THROUGH p TO t1;QUANTITY v_fc ACROSS i_fc THROUGH t1 TO m;QUANTITY v_rd ACROSS i_rd THROUGH t1 TO t2;QUANTITY v_sc ACROSS i_sc THROUGH t2 TO m;QUANTITY v ACROSS p TO m;CONSTANT ri: REAL := 1.0e-2;

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CONSTANT fc: REAL := 60.0;CONSTANT rd: REAL := 4.0e-2;CONSTANT sc: REAL := 2.0e4;

BEGINBREAK v_fc => v_init, v_sc => v_init;v_ri == i_ri * ri;v_fc'DOT == 1.0/(fc * factor) * i_fc;v_rd == i_rd * rd;v_sc'DOT == 1.0/(sc * factor) * i_sc;v_out == v;

END ARCHITECTURE behav;

NOTE: The solvability of a set of equation in a mixed signal model description should satisfy the following two rules:

1. The number of equations specified in the model should be equal to the number of free quantities, through quantities, and port quantities of mode OUT.

2. Any free quantities and any port quantities of mode OUT must appear in a simultaneous equation within the architecture of the model.

In the above example:

Free quantities: (=0)Through quantities: i_ri, i_fc,I_rd,I_sc (=4)Port quantities of mode OUT: v_out (=1)

That is the total number of equations is 5, as highlighted in the VHDL-AMS code.

MyBattery+ -

batt1

i1i := -1

factor := 1.0v_init := 12.0

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Analog solver is responsible for computing the values of the quantities such that the relationships hold (subject to tolerances)

Simultaneous statements may appear anywhere a concurrent statements may appear

The order of simultaneous statements does not matter

1.8.2 Simultaneous IF Statement

A simultaneous IF statement specifies analog behavior of a system based on a set of conditions.

Syntax:[label_name:]IF condition USE

…simultaneous_statements[{ELSIF condition USE

…simultaneous_statements}][ELSE

…simultaneous_statements]END USE [label_name];

Condition specifies expression which evaluates to a BOOLEAN value (TRUE or FALSE). If the condition is TRUE, the corresponding statements after the condition are executed.

Example 1:

IF (sw_on) AND (CTRL > 0.0) USEv= = 0.0;

ELSEi = = 0.0;

END USE;

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Example 2:

LIBRARY IEEE;USE IEEE.ELECTRICAL_SYSTEMS.ALL;ENTITY VoltageLimiter IS

GENERIC (vlim: REAL);PORT ( TERMINAL ip, im, op, om: ELECTRICAL);

END ENTITY VoltageLimiter;

ARCHITECTURE behav OF VoltageLimiter ISQUANTITY vin ACROSS ip TO im;QUANTITY vout ACROSS iout THROUGH op TO om;

BEGINIF vin > vlim USE

vout == vlim;ELSIF vin < -vlim USE

vout == -vlim;ELSE

vout == vin;END USE;

END ARCHITECTURE behav;

ARCHITECTURE Good OF voltagelimiter ISQUANTITY vin ACROSS ip TO im;QUANTITY vout ACROSS iout THROUGH op TO om;

BEGINIF vin'Above(vlim) USE

vout == vlim;ELSIF NOT vin'Above(-vlim) USE

vout == -vlim;ELSE

vout == vin;END USE;BREAK ON vin'Above(vlim), vin'Above(-vlim);

END ARCHITECTURE Good;

E1 R1VLimiter

voltagelimiter1

FREQ := 1

AMPL := 5

R := 1k

E1.V [V]

t [s]

5

-5

0

-2

2

0 10.2 0.4 0.6 0.8

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R1.V [V]

t [s]

0.6

-0.6

0

-0.2

0.2

0 10.2 0.4 0.6 0.8

Example 3:

ENTITY TPH IS GENERIC (Y0 : REAL := 0.0; TS : REAL := 0.0); PORT (QUANTITY INPUT : IN REAL := 0.0; QUANTITY VAL1 : IN REAL := 1.0; QUANTITY VAL2 : IN REAL := -1.0; QUANTITY THRES1 : IN REAL := 0.0; QUANTITY THRES2 : IN REAL := 0.0; QUANTITY VAL : OUT REAL);END ENTITY TPH;

ARCHITECTURE behav OF TPH IS QUANTITY temp_val : REAL := 0.0; SIGNAL sig : REAL := VAL1; SIGNAL upper_crossing : BOOLEAN := FALSE; SIGNAL lower_crossing : BOOLEAN := TRUE;BEGIN ASSERT (THRES1 <= THRES2) REPORT "Threshold 1 should be less than Threshold 2" SEVERITY error;

upper_crossing <= input'ABOVE(THRES2); lower_crossing <= NOT input'ABOVE(THRES1);

BREAK ON upper_crossing, lower_crossing;

PROCESS BEGIN sig <= Y0; WAIT; END PROCESS;

PROCESS (upper_crossing,lower_crossing) BEGIN IF (INPUT<THRES1) THEN sig <= VAL1; ELSIF (INPUT > THRES2) THEN sig <= VAL2; ELSIF ((INPUT > THRES1) AND (sig'LAST_VALUE = VAL1)) THEN sig <= VAL1; ELSIF ((INPUT < THRES2) AND (sig'LAST_VALUE = VAL2)) THEN sig <= VAL2; END IF; END PROCESS; temp_val == sig; VAL == temp_val'ZOH(TS);END ARCHITECTURE;

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E1

R1

R := 10k

tph1Electrical2Sfg

electrical2sfg1

Sfg2Electrical

sfgelectrical1

val1 := 1val2 := -1thres1 := -0.25thres2 := 0.25

-1 * E1.V [V] R1.V [V]

t [s]

1.3

-1.3

0

-0.5

0.5

0 1.50.2 0.4 0.6 0.8 1 1.2

1.8.3 Simultaneous CASE Statement

A simultaneous CASE statement specifies analog behavior by selecting one of a number of alternatives based on the value of an expression.

Syntax:

[label_name:]CASE control_expression USEWHEN choices 1=> simultaneous_statementsWHEN choices 2=> simultaneous_statements…[WHEN OTHERS => simultaneous statements]END CASE [label_name];

Control_expression specifies a value that select one statement sequence among the list of alternatives. The expression must be of a discrete type, or of a one-dimentional array.

Choice specifies for which value of the control expression the alternative is chosen. Each choice in a case statement alternative must be of the same type as the expression.

Example:

LIBRARY IEEE;USE IEEE.MATH_REAL.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.ELECTRICAL_SYSTEMS.ALL;ENTITY scr IS

GENERIC(von: voltage:=0.7; --Turn on voltageihold : current :=0.0; --Holding currentiss : REAL := 1.0e-12); --Saturation current

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PORT(TERMINAL anode, cathode, gate:ELECTRICAL);END ENTITY scr;

ARCHITECTURE ideal OF scr ISQUANTITY vscr ACROSS iscr THROUGH anode TO cathode;QUANTITY vcntl ACROSS gate TO cathode;SIGNAL ison : BOOLEAN;CONSTANT vt: REAL :=0.0258; --thermal voltage

BEGINPROCESS

VARIABLE off: BOOLEAN := TRUE;BEGIN

ison <= NOT off;CASE off is

WHEN TRUE =>WAIT UNTIL vcntl'Above(von) AND vscr'Above(0.0);off:= FALSE;

WHEN FALSE =>WAIT UNTIL NOT(vcntl'Above(von) OR iscr'Above(ihold));off:= TRUE;

END CASE;END PROCESS;IF ison USE

iscr == iss*(exp(vscr/vt)-1.0); --requires IEEE.MATH_REAL packageELSE

iscr == 0.0;END USE;BREAK ON ison;

END ARCHITECTURE ideal;

SCR turns on if voltage across SCR is positive and control voltage is larger than the on voltage von.

SCR turns off if control voltage is below the on voltage von and current falls below the holding current ihold.

E1

scr

anod

e

cath

ode

gate

scr1

r1

E2FREQ := 1AMPL := 5

FREQ := 1AMPL := 1

r := 1k

von := 0.7ihold := 0.0iss := 1.0e-12

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-1 * E1.V [V]

t [s]

6

-6

0-2

0 20.25 0.5 0.75 1 1.3 1.5 1.8

-1 * E2.V [V]

t [s]

1.3

-1.3

0-0.5

0.5

0 20.25 0.5 0.75 1 1.3 1.5 1.8

r1.v

t [s]

4.5

-0.5123

0 20.25 0.5 0.75 1 1.3 1.5 1.8

scr1.iscr

t [s]

4.5m

-0.5m1m2m3m

0 2.10.25 0.5 0.75 1 1.3 1.5 1.8

E1

scr

anod

e

cath

ode

gate

scr1

r1

E2FREQ := 1AMPL := 5

FREQ := 1AMPL := 1

r := 1k

von := 0.7ihold := 2.0e-3iss := 1.0e-12

scr1.iscr

t [s]

4.5m

-0.5m1m2m3m

0 20.25 0.5 0.75 1 1.3 1.5 1.8

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1.8.4 Simultaneous PROCEDURAL Statement

A simultaneous procedural statement provides a sequential notation for expressing Differential and Algebraic Equations. Procedural statements are included within the architecture of a model and are not invoked with a calling mechanism.

Syntax:

[label_name:]PROCEDURAL [IS]

…subprogram declarationaBEGIN

…swquential_statementsEND PROCEDURAL [label_name];

Example:

LIBRARY IEEE;USE IEEE.MATH_REAL.ALL;ENTITY arc_cosine IS

GENERIC (ts: REAL :=0.0);PORT(QUANTITY input: IN REAL;

QUANTITY val: OUT REAL); END ENTITY arc_cosine;

ARCHITECTURE proc OF arc_cosine ISQUANTITY temp_val : REAL:=0.0;

BEGINPROCEDURALBEGIN

IF (input>-1.0) AND (input<1.0) THENtemp_val := arccos(input); --arccos requires

IEEE.MATH_REAL;ELSIF (input = -1.0) THEN

temp_val := MATH_PI; --MATH_PI requires IEEE.MATH_REAL;

ELSEtemp_val := 0.0;

END IF;END PROCEDURAL;val == temp_val'ZOH(ts);

END ARCHITECTURE proc;

sine1arc_cosine

arc_cosine1

ts := 2.0e-2ampl := 2freq := 1

25

sine1.val

t [s]

2.5

-2.5

0

-1

1

0 20.25 0.5 0.75 1 1.3 1.5 1.8

arc_cosine1.val

t [s]

3

-0.5

0.51

1.52

0 20.25 0.5 0.75 1 1.3 1.5 1.8

1.9 Sequential Statements

Sequential statements are executed in the order they are written. The sequential statements are:

WAIT Statement Variable Assignment Signal Assignment* IF Statement CASE Statement Loop Statement NEXT Statement EXIT Statement RETURN Statement NULL Statement Procedure Call*

ASSERT Statement*

* These statements execute sequentially or concurrently depends on its placement.

1.9.1 WAIT Statement

A WAIT statement suspends subprogram execution until a signal changes, a condition becomes TRUE, or a defined time period has elapsed.

Syntax:

WAIT [ON sensitivity list] [UNTIL condition] [FOR time_expression];

Example:

WAIT ON input;WAIT UNTIL ctrl > 1.5;WAIT FOR 5ns;

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1.9.2 IF Statement Provides conditional control of sequential statements. Condition in statement must evaluate to a Boolean value. Execution of statements with IF occurs when condition is TRUE. IF statements can only be used in sequential areas of the model. Syntax:

IF condition THEN -- sequential statements END IF;

IF condition THEN -- sequential statements ELSE -- sequential statements END IF;

IF condition THEN -- sequential statements ELSIF condition THEN --sequential statements -------- ELSE END IF;

Example 1: Transparent Latch Level Sensitive LatchIs a latch which is sensitive signal level and not to clock edge.

INPUTS OUTPUTD E Q(t+1)X L Q(t)L H LH H H

1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 4 ENTITY dltch IS5 PORT(d, e : IN BIT; q : OUT BIT);6 END dltch;7 8 ARCHITECTURE arch1_dltch OF dltch IS9 BEGIN

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10 PROCESS(d, e)11 IF (e = ‘1’) THEN12 q <= d;13 END IF;14 END PROCESS;15 END arch2_dltch;

In this example, the process latch is sensitive to two signals d and e. The target signal q is only assigned to when e = ‘1’. If e changes to a ‘0’, q must retain its state even if d changes. That is, the simple IF statement does not contain enough information to synthesize a combinational network. What happen to the target signal when the condition is false is not specified. Autologic VHDL assumes that the target signal will retain its old value. The result is the simple IF statement is synthesize as transparent latch.

In order for a VHDL code to be synthesized as a combinational network using an if statement, the if statement must explicitly define the behavior of all possible evaluations of the condition. The addition of the ELSE clause completes the definition of the behavior of an if statement. In this example, the synthesized result is a combinatorial 2-to-1 multiplexer.

Example 2: Multiplexer implemented as combinational circuit, using IF-THEN-ELSE1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;34 ENTITY mux21 IS5 PORT(a, b, s: IN BIT; o: OUT BIT);6 END mux21;78 ARCHITECTURE archmux21 OF mux21 IS9 BEGIN10 PROCESS(a,b,s)11 BEGIN12 IF(s=‘1’) THEN13 o<=a;14 ELSE15 o<=b;16 END IF;17 END PROCESS;18 END archmux21;

Example 3: D-Type Edge Triggered Flip-Flop with Set and Reset

INPUTS OUTPUTD S R CLK QX X H X LX H L X HL L L ^ LH L L ^ H

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1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;34 ENTITY dsrff IS5 PORT(d, s, r, clk : IN BIT; q : OUT BIT);6 END dsrff;78 ARCHITECTURE arch1_dsrff OF dsrff IS9 BEGIN10 latch: PROCESS(d, s, r, clk)11 BEGIN12 IF (r = ‘1’) THEN13 q <= ‘0’;14 ELSIF (s = ‘1’) THEN15 q <= ‘1’;16 ELSIF (clk’EVENT AND clk = ‘1’) THEN17 q <= d;18 END IF;19 END PROCESS;20 END arch1_dsrff;

Example 4: Algorithmic and_gate

1 LIBRARY IEEE, ARITHMETIC;2 USE IEEE.STD_LOGIC_1164.ALL;3 USE ARITHMETIC.STD_LOGIC_ARITH.ALL;45 ENTITY and_gate IS6 PORT(a,b:IN STD_LOGIC;c:OUT STD_LOGIC);7 END and_gate;89 ARCHITECTURE algorithm OF and_gate IS10 BEGIN11 and_process:12 PROCESS(a,b)13 BEGIN14 IF a='1' AND b='1' THEN15 c <= `1' AFTER 10 ns;

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16 ELSIF (a='0') OR (b='0') THEN17 c <= `0' AFTER 10 ns;18 ELSE19 c <= `X' AFTER 5 ns;20 END IF;21 END PROCESS and_process;22 END algorithm;

Example 5: Oscillator: switch back and forth between two states

1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;34 ENTITY clock IS5 PORT(clk,clk_bar:OUT STD_LOGIC);6 END clock;78 ARCHITECTURE algorithm OF clock IS9 BEGIN10 PROCESS11 VARIABLE switch:BIT:='0';12 BEGIN13 IF switch='0' THEN14 clk <= `0';15 clk_bar <= `1';16 ELSE17 clk <= `1';18 clk_bar <= `0';19 END IF;20 switch:=NOT switch;21 WAIT FOR 10 ns;22 END PROCESS;23 END algorithm;

Example6: one of four multiplexer

1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;34 ENTITY mux41 IS5 PORT(sel_0, sel_1, a, b, c, d: IN STD_LOGIC; out_1:OUT STD_LOGIC);6 END mux4178 ARCHITECTURE behav OF multiplexer IS9 BEGIN10 one_of_four:11 PROCESS(sel_0,sel_1,a,b,c,d)12 BEGIN13 IF sel_1='0' THEN14 IF sel_0 = `0' THEN15 out_1 <= a;16 ELSE17 out_1 <= b;18 END IF;19 ELSIF sel_1 = `1' THEN20 IF sel_0 = `0' THEN

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21 out_1 <= c;22 ELSE23 out_1 <= d;24 END IF;25 END IF;26 END PROCESS one_of_four;27 END behav;

1.9.3 CASE Statement

A CASE statement selects one of a number of alternative sequence of statements for execution based on the value of an expression. The control expression must be of discrete data type. CASE statement must include all possible values of the control expression. The OTHERS expression can be used to guarantee that all conditions are covered.

Syntax:

[label_name:]CASE control_expression IS

WHEN choice1 => Sequential statements

WHEN choice2 =>Sequential statements

WHEN OTHERS =>Sequential statements

END CASE [label_name];

Examples:

Example 1: one of two multiplexer

1 LIBRARY IEEE; 2 USE IEEE.STD_LOGIC_1164.ALL; 3 ENTITY mux21 IS 4 PORT(a, b, s :IN BIT; o : OUT BIT); 5 END mux21;

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6 ARCHITECTURE archmux21 OF mux21 IS7 BEGIN8 PROCESS(a, b, s)9 BEGIN10 CASE s IS11 WHEN ‘0’ => o <= a;12 WHEN ‘1’ => o <= b;13 WHEN OTHERS => o <= ‘X’; --or WHEN OTHERS => NULL;14 END CASE;15 END PROCESS;16 END archmux21;

Example 2: one of four multiplexer

1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 ENTITY mux41 IS4 PORT(sel_0, sel_1, a, b, c, d :IN STD_LOGIC; out_1 : OUT STD_LOGIC);5 END mux41;67 ARCHITECTURE archmux41 OF mux41 IS8 BEGIN9 one_of_four:10 PROCESS(sel_0,sel_1,a,b,c,d)11 BEGIN12 CASE sel_1 & sel_0 IS13 WHEN "00" => out_1 <= a;14 WHEN "01" => out_1 <= b;15 WHEN "10" => out_1 <= c;16 WHEN "11" => out_1 <=d;17 WHEN OTHERS => NULL;18 END CASE;19 END PROCESS one_of_four20 END example;

Example 3: one_bit_adder1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;34 ENTITY one_bit_adder IS5 PORT(a,c_in,b:STD_LOGIC;sum,c_out:OUT STD_LOGIC);6 END one_bit_adder;78 ARCHITECTURE behav OF one_bit_adder IS9 SIGNAL total:INTEGER RANGE 0 TO 4;10 BEGIN11 majority: WITH a & c_in & b SELECT12 total <= 0 WHEN "000",13 1 WHEN "100"|"010"|"001",14 2 WHEN "101"|"011"|"110",15 3 WHEN "111",16 4 WHEN OTHERS;17 adder: PROCESS(total)18 BEGIN

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19 CASE total IS20 WHEN 0 => sum <='0'; c_out <='0';21 WHEN 1 => sum <='1'; c_out <='0';22 WHEN 2 => sum <='0'; c_out <='1';23 WHEN 3 => sum <='1'; c_out <='1';24 WHEN OTHERS => sum <='X'; c_out <='X';25 END CASE;26 END PROCESS adder;27 END behav;28

`&' Concatenation symbol OTHERS indicates all unspecified elements. `|' means or NULL is a sequential statement indicating no action occurs

1.9.4 LOOP Statement

There are three types of loops: FOR, WHILE, and LOOP-EXIT. Autologic VHDL only supports theFOR loop construct.

1.9.4.1 FOR Loop

Format: [label:] FOR loop_parameter IN discrete_range LOOP --sequential_statements END LOOP [label]; Sequential statements are executed once for each value in loop parameter's range. Loop parameter is implicitly declared and may not be modified within loop or used outside loop. Implicitly declared means there does not have to be a variable declaration. The discrete_range can be

subrange of integer or enumeration type.

Example:

PROCESS(signal_a) BEGIN label_1: FOR index IN 0 TO 7 -- index is implicitly declared LOOP

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ray_out(index) <= ray_in(index); END LOOP label_1; END PROCESS;

1.9.4.2 WHILE Loop

Format:[label]: WHILE boolean_expression

LOOP -- sequential_statements END LOOP [label]; boolean_expression is evaluated before each repetition of loop.

Example:

P1: PROCESS(signal_a) VARIABLE index:INTEGER:=0; BEGIN while_loop: WHILE index < 8 LOOP ray_out(index) <= ray_in(index); index:=index+1; END LOOP while_loop; END PROCESS P1; Loop parameter is explicitly declared and can be any scalar type. If the loop parameter index in the above example is of type real, the corresponding boolean expression

would be Index < 8.0 and the increment would have to be index:=index +1.0;

1.9.4.3 LOOP-EXIT Construct

Format: LOOP -- sequential_statements -- including decision_to_quit END LOOP; Does not contain an iteration scheme specifying how loop terminates. A decision to leave loop must be made from within loop. Can be terminated from within by: EXIT, NEXT

1.9.4.4 EXIT statement

Used to break out of loops Only occurs whithin loops Format: EXIT; EXIT loop_label; EXIT WHEN boolean_expression; EXIT loop_label WHEN boolean_expression EXIT command takes effect as soon as it is executed. Statements which appear after EXIT are not

executed.

Example:

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show_loops: PROCESS(s) VARIABLE sum,cnt:INTEGER :=0; BEGIN sum:=0; cnt:=0; first:LOOP cnt:=cnt+1; sum:=sum+cnt; EXIT WHEN sum > 100; END LOOP; second:LOOP cnt:=cnt+1; sum:=sum+cnt; IF cnt>100 THEN EXIT; END IF; END LOOP; END PROCESS show_loops;

NOTE: It is necessary to reset the variable sum and cnt to zero, even if their initial value is zero. Since, the initial value is not a reset value. It occurs only the first time the loop executed. Thereafter, each time the process is entered the value of the variable will be equal to the value assigned to the variable the last time the process was exited.

1.9.4.5 NEXT statement

Causes completion of one of the iterations of an enclosing loop. Format: NEXT; NEXT loop_label; NEXT WHEN boolean_expression; NEXT loop_label WHEN boolean_expression;

Example:

next_xmpl: PROCESS(s) VARIABLE temp,j:INTEGER:=0; BEGIN temp:=0;j:=0; a_loop:FOR j IN 0 TO 7 LOOP j:=j+1; IF j>5 THEN NEXT a_loop; END IF; temp:=temp+1; END LOOP a_loop; END PROCESS next_xmpl;

NEXT without loop label causes the next iteration of the loop it is contained in to be executed. Control still remains within the loop's iteration scheme.

Loop label can refer to the label on any loop enclosing the NEXT statement. The NEXT statement causes completion of the current iteration. Statements which follow the NEXT

are not executed. Control is transferred to the beginning of the loop and the next iteration is started.

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Example: a four-to-sixteen decoder can easily be modeled and synthesize using the FOR loop.

1 PACKAGE my_intgr IS2 SUBTYPE my_int IS INTEGER RANGE 0 TO 1;3 END my_intgr;4 5 LIBRARY IEEE, ARITHMETIC;6 USE IEEE.STD_LOGIC_1164.ALL;7 USE ARITHMETIC.STD_LOGIC_ARITH.ALL;8 USE WORK.my_intgr.ALL;9 10 ENTITY dec4_16 IS11 PORT(in_array: IN ARRAY(0 TO 3) OF my_int; 12 out_array: OUT ARRAY(0 TO 15) OF my_int);13 END dec4_16;14 15 ARCHITECTURE archdec4_16 OF dec4_16 IS16 BEGIN17 PROCESS(in_array)18 VARIABLE index: INTEGER RANGE 0 TO 15;19 BEGIN20 index :=0;21 FOR i IN in_array’RANGE LOOP22 index := index + (2**i)*in_array(i);23 END LOOP;24 25 FOR j IN 0 TO 15 LOOP26 out_array(j) <=0;27 END LOOP;28 out_array(index) <= 1;29 END PROCESS;30 END archdec4_16;

NOTE: the use in_array'RANGE attribute to determine the index range. in_array is an array of type integer with range 0 to 1.

1.10 Signal Assignment Statements

There are three types of signal assignment: simple signal assignment, conditional signal assignment, and selected signal assignment.

1.10.1 Simple Signal Assignment

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The simple signal assignment statement specifies that a target signal is to receive some waveform. Its syntax is:

target_signal <= waveform;

Example:

q <= a AND b

Assumming a, b, and q are signals of type BIT, it is synthesize as an AND gate shown below:

1.10.2 Conditional Signal Assignment

The conditional signal assignment assigns waveforms to a target signal based on the validity of a condition. Its syntax is:

target_signal <= waveform WHEN condition ELSEwaveform;

Example: The following code implements a two-to-one multiplexer (MUX21) 1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 ENTITY mux21 IS4 PORT(a,b,s :IN BIT; o :OUT BIT);5 END mux21;6 ARCHITECTURE archmux21 OF mux21 IS7 BEGIN8 o <= a WHEN (s=’0’) ELSE9 b;10 END archmux21

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1.10.3 Selected Signal Assignment

The selected signal assignment statement assigns waveforms to a target signal based on the value of the included expression. Its syntax is:

WITH expression SELECTtarget_signal <= waveform_1 WHEN expression_value_1,

waveform_2 WHEN expression_value_2,waveform_n WHEN expression_value_n;

You can use any number of WHEN clauses, but no two WHEN clauses can have the same expression value. You must account for all possible values of “expression”. You can use a WHEN OTHERS clause for all unspecified elements and “don’t care” situations.

The following code implements a two-to-one multiplexer (MUX21). Since s is a STD_LOGIC type of signal it has four possible states. WHEN OTHERS is used to accouunt for other values of s.

Example: Multiplexer two-to-one using selected signal assignment.

1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 ENTITY mux21 IS 4 PORT(a, b, s :IN STD_LOGIC; o :OUT STD_LOGIC);5 END mux21;6 ARCHITECTURE archmux21 OF mux21 IS7 BEGIN8 WITH s SELECT9 o <= a WHEN ‘0’,10 b WHEN ‘1’,11 ‘X’ WHEN OTHERS12 END archmux21;

Example: three to eight decoder

1. LIBRARY IEEE;2. USE IEEE.STD_LOGIC_1164.ALL;3.4. ENTITY Decoder IS5. GENERIC(Delay:TIME:=5 ns);6. PORT(Sel:IN BIT_VECTOR(2 DOWNTO 0);7. DOut:OUT BIT_VECTOR(7 DOWNTO 0);8. END Decoder;9.10. ARCHITECTURE behav OF Decoder IS11. BEGIN12. WITH Sel SELECT13. DOut <=14. "00000001" AFTER Delay WHEN "000",15. "00000010" AFTER Delay WHEN "001",16. "00000100" AFTER Delay WHEN "010",17. "00001000" AFTER Delay WHEN "011",18. "00010000" AFTER Delay WHEN "100",19. "00100000" AFTER Delay WHEN "101",

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20. "01000000" AFTER Delay WHEN "110",21. "10000000" AFTER Delay WHEN "111",22. END behav;

REFERENCES

1. “Analog and Mixed-Signal Modeling Using the VHDL-AMS Language”, E.C. Beaverton et.al., 36th Design Automation Conference, New Orleans, June 21-25, 1999.

2. “Simulation System SIMPLORER VHDL-AMS Tutorial,” English Edition, © 2003 Ansoft Corporation.

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