File Number Here ® Spartan-II FPGAs in Set-top Boxes - Sales Tutorial.

File Number Here

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Spartan-II FPGAs in Set-top Boxes - Sales Tutorial

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www.xilinx.comXilinx at Work in Hot New Technologies

Agenda

Introduction

Market & Technology Overview

Spartan-II Solutions in Set-top Boxes

Sales Tools

Summary

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Overview

Xilinx - The Industry Leader in FPGAs/CPLDs— Low cost, high density, high speed

Spartan-II is a Perfect Match for Set-top Boxes— Faster time-to-market with programmable logic— Easily integrates system logic functions

– Interface, control, decode, state machines etc.– Extremely cost effective

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What is a Set-Top Box ?

Set-Top Box— Receives digital broadcast channels and converts signals to

analog or the standard TV format— Pure Internet Gateways and other network PCs are not strictly

set-top boxes, although the term is often used

Different Types of Set-Top Boxes— Cable— xDSL— Satellite— Terrestrial

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Set-Top Box Growth Drivers

More Channels— Increased choices

– More specialist channels– Immediate feedback to broadcasters

— New services– Improved Pay-as-you View– Online shopping– Interactive TV– Hard-drive storage– Instant replay– Near Video-on-demand

— Maximum use of available bandwidth

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Set-Top Box Growth Drivers

Improved Quality— Support for HDTV— No “ghosting” or other interference effects— Allows broadcasters flexibility in terms of bandwidth vs quality

Possible Internet Gateway— Some set-top boxes allow Internet access— Simpler to use than PC based tools

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The Super Glue of System Logic

Front end ASSPsSatelliteCableTerrestrial

Without Xilinx

With Xilinx

External I/F ASSPsNetwork Interfaces

Host - RS-232, USB, IEEE 1394

Security/EncryptionConditional Access

PCMCIAProprietary

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1998 1999 2000 2001

$10$10Sy

stem

Gat

es

30K

Spartan-XL

40K

Spartan-III

250K

Spartan-II

100K

FIFOsFIFOs

PALsPALs

HDLCHDLC

UARTsUARTs

32-bit, 32-bit, 33-MHz 33-MHz

PCIPCI

PCI-MIPS PCI-MIPS BridgeBridge

64 Bit 64 Bit PCIPCI

Reed Solomon Reed Solomon EncoderEncoder

Video Line Video Line BufferBuffer

Ethernet Ethernet MACMAC

ATM IMA ATM IMA

Cable Modem

Graphics Card

Office Networking

Set-Top Box

Embedded μP Apps

Higher Density Enables New Applications

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Set-Top Box Unit Shipments

0

5

10

15

20

25

1998 2000 2002

Year

Uni

ts (m

illio

ns)

Cable DBS Terrestrial

0

5

10

15

20

25

1998 2000 2002

Year

Uni

ts (m

illio

ns)

Cable DBS Terrestrial

Source: Cahners In-Stat Group

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Market Dynamics

Fragmented Market— Cable, Satellite, Terrestrial & xDSL

Evolving Market, Multiple Consumer Requirements— Low end set-top box (decode audio and video)— Mid-range set-top box (limited interactivity e.g. program

schedulers)— High end set-top box (high degree of interactivity; e.g. web-

browsing, hard-disk video storage)

Time to Market Critical— Rapid development cycles, cost sensitive

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Set-Top Box Technology

Cable— Uses cable network to supply the TV channels— Can use same network connection for PCs

xDSL— Adaptive digital modulation technologies to achieve increased data

rates (1.5 Mbps - 8 Mbps)

Satellite— Broadcasts to the home via satellite and dish-aerial

Terrestrial— Broadcast via ground based transmitters in the same way as analog

TV using old analog aerial

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Generic Block Diagram

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0

0.5

1

1.5

2

2.5

3

3.5

1997 1998 1999 2000 2001 2002

$ Billio

ns

0

20

40

60

80

100

120

140

160

Sem

icond

ucto

r Con

tent

ASP

($)

Semiconductor Market Semiconductor Content

Source: Dataquest

STB Semiconductor Content

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DLL

CL IOB

IOB

IOB

IOB

IOB

IOBIOB

IOB

DLL

DLL DLL

CLCL

CL

. . .

. . .. .

.

. . .

CLB CLB

CLB CLB

RAM

RAM

RAM

RAM

I/O Routing Ring

I/O Routing Ring

True Dual-PortTM

4K bit RAM

Clock managementMultiply clockDivide clock

De-skew clock

Chip to BackplanePCI 33MHz 3.3VPCI 33MHz 5.0VPCI 66MHz 3.3VGTL, GTL+, AGP

Chip to MemoryHSTL-I, HSTL-IIIHSTL-IVSSTL3-I, SSTL3-IISSTL2-I, SSTL2-IICTT

Chip to ChipLVTTL, LVCMOS

Power-down modeConfiguration & register

state maintainedPower-down status pin

SelectI/OTM

Technology

Logic and Distributed RAM

Configurable Logic Block (CLB)Delay Locked Loop (DLL)

4Kx12Kx21Kx4512x8

256x16

Block Memory

Power Management

Spartan-II Feature Rich ForSet-Top Box Solutions

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Front End System Interface

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QPSK Decoderand FEC

QAM Decoderand FEC

OFDM Decoderand FEC

xDSLSpartan-II FPGA Allows Interface To MultipleFront Ends

Front End Interface

Not Cost Effective to Support Multiple Receivers— Cable, Terrestrial, Satellite and xDSL— Requires multiple set-top box designs

Interface required to support multiple ASSPs— Choice of ASSP influenced by

broadcaster features

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Clock Distribution

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Clock Generation and Distribution

Spartan-II DLL Circuits Provide Full Clock Management Solution

Clock Generation— Synthesizing many clocks from a single reference crystal or

clock

Clock Buffering and Distribution— Providing multiple copies of a single clock— SDRAM clocks

Spread Spectrum Clocks for EMI Reduction

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DLL1 DLL2

DLL3 DLL4

Deskewclocks

on ChipManage up to 4system clocks

Deskewclocks

on board

CascadeDLLs

Generateclocks• multiply• divide• shift

Convertclocklevelsusing

SelectI/O

Delay Locked Loops lower memory and board costs

Spartan-II Clock Management

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Memory Solutions

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1998 1999 2000

200 MHz Memory Continuum - Transparent Bandwidth

DSP CoefficientsSmall FIFOs

16x1

Distributed RAM

Large FIFOs Video Line BuffersCache Tag Memory

4Kx12Kx21Kx4512x8

256x16

Block RAM

SDRAMSGRAM

PB SRAMDDR SRAMZBT SRAMQDR SRAM

External MemoryInterface

Memory Corner

Memory Corner

Free Reference Designs

Free Reference DesignsMemory Corner

Memory Corner



Spartan-II Memory Solutions

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Spartan-IITrue Dual-Port

Block RAM

Port A

Port BW

R

W

R

W

RR

W Data Flow Spartan-II Two-PortA to B Yes YesB to A Yes NoA to A Yes NoB to B Yes No

Spartan-II Block RAM

True Dual-port Static RAM - 4K Bits— Independently configurable port data width

– 4K x 1; 2K x 2; 1K x 4; 512 x 8; 256 x 16 — Fast synchronous read and write

– 2.5ns clock-to-output with 1.0ns input address/data setup

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Website for Comprehensive Memory Solutions— SRAM, DRAM & embedded FPGA memory solutions

– Data sheets, application notes, tutorials, FAQs, design guidelines

Memory Corner

Memory Corner Offers


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Conditional Access System

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Conditional Access System

Multiple Encryption/decryption Algorithms Exist— Proprietary algorithms driven by broadcasters

Efforts Underway to Standardize Encryption/decryption

Programmable Logic Allows Support for Multiple Algorithms— Encryption algorithm ‘programmed’ after manufacture — Allows single platform for high volume manufacture

– Realize economies of scale— Field upgradable for evolving standards

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Driving New Technology

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FPGA Drives New STB Features

Spartan-II FPGA Drives a New Generation of Set-top Box— Capability to store video on hard disk drives— Provides capability to record and view video simultaneously

(TiVO, Replay)

Provides Data Buffer and Disk Control Logic— On-chip memory for FIFOs— Support for multiple I/O standards

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Spartan-II FPGA Allows Support for Multiple Disk Drives

Provides Ability to Support Evolving Disk Drive Technologies— StreamWeaver command set from Western Digital

– Optimized for simultaneous disk read and write

Enables Dual Sourcing of Multiple Types of Hard Disk Drives

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Spartan-II FPGA Enables New Set-Top Box Technology Spartan-II FPGAs are used to Revolutionize the TV

Experience — Pause live TV— Instant replay— Automatically records favorite programs— Advanced TV program search

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Top End Set-Top Box

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Top End Set-Top Box Solution

Spartan-II FPGAs Provide High Performance MPEG Encoding/decoding— DCT/IDCT AllianceCORE IP from Xentec— Offload processor for high performance system

1 3

180

0

50

100

150

200

266MHz 32-bit uP 266MHz 32-bit uPwith Multimedia

Extensions

Spartan-II

Rel

ativ

e P

erfo

rman

ce

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Spartan-II FPGAs: Programmable ASSP

100,000 System Gates at Under $10— Extensive features: Block RAM, DLL, SelectI/O

IP Portfolio Allows Replacement of Traditional ASSPs— Provide density, features, performance at ASIC prices— IP cores

– DCT/IDCT, DES, QDR SRAM, Reed-Solomon, PCI– See IP Center for additional cores

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A Successful Programmable ASSP

0.5

1

0.1

External PLD7K Gates

External DLLs, memories, Controllers and translators

Standard Chip

Rel

ativ

e C

ompo

nent

Cos

t

PCI ASSPPCI Master

and Slave I/F

XC2S30-5 PQ208

15K Gates Logic

PCI Master I/F

Solution <$6Solution <$6

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Xilinx On-line Field Upgradability Remote Update of Software and Hardware

Results in Increased Lifetime for a Product

Enable Product Features Per End-user Needs— Opening up new opportunities in the ASSP area

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High Volume System Integration

SSTL3

GTL+

5-volt tolerant I/O

SDRAM

QDR SRAMs

MIPS uP

2x CLKPC

I

Clock Mgmt - Board deskew

PLL

$7.50

PCI Master/Target Controller

$15

SSTL-3 Translators

$4

FIFOs

Memory

DualPorts

$7 $2PCI-MIPS System

Controller $40

HSTL Translators

$6

$6

GTL+Backplane

Drivers

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Programmable Logic Solutions in Set-Top Boxes

Glue Logic between Host CPU and I/O Devices

Clock Distribution and Memory Controller and Buffer

Interface between ASSPs and ASSP Replacement

Interface Between Multiple Front-ends and Back-ends

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Enables Advanced Features not Found in ASSPs

Disk Drive Storage of Broadcast Channels

ASSPs will be developed with this interface but will take 12 Months

ASICs could be spun in 6 Months

FPGA could be designed in 1-2 Months

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Advantages of Programmable Logic

Time to Market

Flexibility

Field Upgradable

Cost Competitive

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Additional Resources

Xilinx at Work Website— Market overview— Glossary and FAQs— Application notes— White papers— Free reference designs

FPGA Strategic Applications Group

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Manufacturers• Pace• Echostar• Sony• Amstrad• Thomson• RCA• General Instruments• Matsushita/Panasonic• Philips• Zenith• Mitsubishi• Nokia• Grundig• Scientific Atlanta

Broadcasters• DirecTV• Echostar• Canal Plus• BSkyB• NHK• Kirch • Ondigital• NTL• AT&T/TCI• ComCast• CWC• Turner

ASSP Providers• ST Microelectronics• LSI• Conexant• VLSI• National Semi• Broadcom• C-Cube Microsystems• IBM• Sony• Motorola• Atmel

Set-Top Box - Key Companies

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Hints for Successful Selling - Acronyms

A few of the buzz words & abbreviations — ATSC and DVB

– The two main video standards bodies for digital television— DSB - Digital Satellite Broadcast— DTB - Digital Terrestrial Broadcast— Conditional Access

– Encryption schemes— Smartcard

– Used in conjunction with Conditional Access System to provide encryption and Pay-as-you-view services

— MPEG2 - Motion Picture Experts Group, version 2– The compression scheme used to send video over each broadcast

channel

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Hints for Successful Selling - ASSPs

Total Digital Set-top Box Cost ~ $160— ASSP and Memory devices ~ $80 (50% of total)

ASSPs— Ideal for Implementing the complex system technology

Spartan-II FPGAs Play in the “System Glue” Needed to Connect ASSPs — ASSPs not designed to “speak to each other”— System glue = DMA, FIFO, PCI, ASSP interfacing, Memory

Interface, External Interface Translation, etc.— Look for these opportunities, easy to identify— List of key ASSPs available on Xilinx at Work pages on SPW

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Summary

Sales Strategies— Sell time-to-market, flexibility, least risk solution, ease of

inventory management, field upgrade capability

Spartan-II FPGAs Present— Higher densities at lower costs allow efficient ways of

integrating standard ASSPs — Reprogrammability

– Extends Time-in-Market– Continuous feature integration & future upgrades

– Quick time-to-market in fast growing market– Maximizes revenue of new products

– Non-standard ASSP control interfaces

File Number Here ® Spartan-II FPGAs in Set-top Boxes - Sales Tutorial.

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