figures ch 9 - CRC Press ch 9.pdf · Chapter 9 Structural Modeling 3 Page 499 +a +b +c +d net1 net2...

Chapter 9 Structural Modeling 1

Verilog HDL:Digital Design and Modeling

Chapter 9

Structural Modeling

Additional Figures


Page 494

reg or netnet reg or net

netnet

net

Module

Module Module

Module

outportnet1

net1

inport_a

inport_b

Figure 9.4 Diagram illustrating port connection rules.

Page 495module name (x1, z1);

input [3:0] x1;output [1:0] z1;

.

.

.endmodule

module top;wire [1:0] x2;wire [4:0] z2;

.

.

.name inst1 (

.x1(x2),

.z1(z2));

endmodule

x1

x2

3 2 1 0

1 0

1 0

3 2 1 04z2

z1

z z

z z z

Figure 9.5 Figure to illustrate connecting ports of different widths.


Page 499

+a

+b

+c

+d

net1

net2

net3

net4

net5

net6

net7

net8

net1net3net5net7net1net3net5net8net1net3

–z0

–z1

–z2

–z3

–z4

–z5

–z6

–z7

–z8

–z9

net6net7net1net3net6net8net1net4net5net7net1net4net5net8net1net4net6net7net1net4net6net8net2net3net5net7net2net3net5net8

Figure 9.9 Logic diagram for a BCD-to-decimal decoder.

z0z1z2z3z4z5z6z7z8z9

BCD/DEC

+a

+b

+c

+d

+ f1

+ f2


Page 500

Figure 9.10 Logic diagram to implement the functions for f1 and f2.


Page 500

0 0 0 1 1 1 1 0

0 0 0 0 0 0

0 1 0 1 1 1

1 1 0 0 0 0

1 0 1 1 0 0

a bc d

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

w

0 0 0 1 1 1 1 0

0 0 0 1 1 1

0 1 1 0 0 0

1 1 0 0 0 0

1 0 0 1 0 0

a bc d

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

x

0 0 0 1 1 1 1 0

0 0 1 0 1 0

0 1 1 0 1 0

1 1 0 0 0 0

1 0 1 0 0 0

a bc d

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

y

0 0 0 1 1 1 1 0

0 0 1 0 0 1

0 1 1 0 0 1

1 1 0 0 0 0

1 0 1 0 0 0

a bc d

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

z

Figure 9.11 Karnaugh maps for the BCD-to-excess-3 code.

w = a'bd + a'bc + ab'c '

x = a'b'd + a'b'c + b'c'd + a'bc 'd '

y = a'c 'd ' + a'cd + b'c 'd '

z = a'c 'd ' + a'cd ' + b'c 'd ' (9.3)


01

0123456789

BCD/DEC

+a

+b

+c

+d

–z0–z1–z2–z3–z4–z5–z6–z7–z8–z9

+w

+x

+y

+z

–z0

–z5–z6–z7–z8–z9

–z1–z2–z3–z4–z9

–z3–z4–z7–z8

–z0–z2–z4–z6–z8


Figure 9.12 Logic diagram for BCD-to-excess-3 conversion.


Page 506

0 0 0 1 1 1 1 0

0 0 0 0 0 0

0 1 0 0 1 0

1 1 – – – –

1 0 – – – –

y3y2

y1y0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

Jy3

0 0 0 1 1 1 1 0

0 0 – – – –

0 1 – – – –

1 1 – – – –

1 0 0 1 – –

y3y2

y1y0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

Ky3

0 0 0 1 1 1 1 0

0 0 0 0 1 0

0 1 – – – –

1 1 0 0 0 0

1 0 0 0 0 0

y3y2

y1y0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

Jy2

0 0 0 1 1 1 1 0

0 0 – – – –

0 1 0 0 1 0

1 1 – – – –

1 0 – – – –

y3y2

y1y0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

Ky2

0 0 0 1 1 1 1 0

0 0 0 1 – –

0 1 0 1 – –

1 1 – – – –

1 0 0 0 – –

y3y2

y1y0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

Jy1

0 0 0 1 1 1 1 0

0 0 – – 1 0

0 1 – – 1 0

1 1 – – – –

1 0 – – – –

y3y2

y1y0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

Ky1

Continued on next page

Figure 9.17 Karnaugh maps for modulo-10 counter using JK flip-flops.


Page 507

0 0 0 1 1 1 1 0

0 0 1 – – 1

0 1 1 – – 1

1 1 – – – –

1 0 1 – – –

y3y2

y1y0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

Jy0

0 0 0 1 1 1 1 0

0 0 – 1 1 –

0 1 – 1 1 –

1 1 – – – –

1 0 – 1 – –

y3y2

y1y0

0 1 3 2

4 5 7 6

12 13 15 14

8 9 11 10

Ky0

Figure 9.17 (Continued)

Jy3 = y2 y1 y0 (net1)

Jy2 = y3 ' y1 y0 (net2)

Jy1 = y3 ' y0 (net4)

Jy0 = 1

Ky3 = y0

Ky2 = y1 y0 (net3)

Ky1 = y0

Ky0 = 1 (9.4)


Page 513

a b cinFA3

cout sum

a b cinFA2

cout sum

a b cinFA1

cout sum

a b cinFA0

cout sum

a[0]

b[0]

a[1]

b[1]

a[2]

b[2]

a[3]

b[3]Modecontrolm

cout[3] rslt[3] rslt[2] rslt[1] rslt[0]

cout[2] cout[1] cout[0]

inst0inst1inst2inst3

net0net1net2net3

Figure 9.23 Logic diagram for a 4-bit adder/subtractor.


Page 513

True subtractionA = 0 1 1 1 (+7)

–) B = 0 1 0 0 (+4)(+3)

A = 0 1 1 1+) (B ' + 1) = 1 1 0 0 1 0 0 1 1

No overflow

True additionA = 0 0 1 1 (+3)

–) B = 1 1 0 0 (– 4)(+7)

A = 0 0 1 1+) (B ' + 1) = 0 1 0 0 0 0 1 1 1

No overflow

True additionA = 1 1 0 0 (– 4)

–) B = 0 0 1 1 (+3)(–7)

A = 1 1 0 0+) (B ' + 1) = 1 1 0 1 1 1 0 0 1

No overflow

True subtractionA = 1 0 1 1 (–5)

–) B = 1 1 0 1 (–3)(–2)

A = 1 0 1 1+) (B ' + 1) = 0 0 1 1 0 1 1 1 0

No overflow

True additionA = 0 1 1 0 (+6)

–) B = 1 1 0 0 (– 4)(+10)

A = 0 1 1 0+) (B ' + 1) = 0 1 0 0 0 1 0 1 0

Overflow

True additionA = 1 0 0 0 (–8)

–) B = 0 0 1 0 (+2)(–10)

A = 1 0 0 0+) (B ' + 1) = 1 1 1 0 1 0 1 1 0

Overflow


Page 519

Adder

cin

a[0]b[0]

a[1]b[1]

a[2]b[2]

a[3]b[3]

s[0]

s[1]

s[2]

s[3]

cout

+c[0]–c[1]+a[0]

+b[0]+a[1]+b[1]

+a[2]+b[2]

+a[3]+b[3]

+sum[0]

+sum[1]

+sum[2]

+sum[3]

+cout

+a[0]+b[0]+a[1]+b[1]+a[2]+b[2]+a[3]+b[3]

+a[0]+b[0]+a[1]+b[1]+a[2]+b[2]+a[3]+b[3]

+and[0]

+and[1]

+and[2]

+and[3]

net_and[0]

inst1

inst10inst6

inst2

inst7

inst8

inst9

inst11

inst12

inst13

inst3

inst4

inst5

net_and[1]

net_and[2]

net_and[3]

+or[0]

+or[1]

+or[2]

+or[3]

net_or[0]

net_or[1]

net_or[2]

net_or[3]

net_xor[3]

net_xor[0]

net_xor[1]

net_xor[2]

net_sum[0]

net_sum[1]

net_sum[2]

net_sum[3]

cin_adder

MUX

s0

d0d1

s1

d3

d2

EnblMUX

s0

d0d1

s1

d3

d2

Enbl

MUX

s0

d0d1

s1

d3

d2

EnblMUX

s0

d0d1

s1

d3

d2

Enbl

inst15inst14

inst16 inst17

+enbl+c[0]+c[1]

+sum[0]

+and[0]+or[0]

+enbl+c[0]+c[1]

+sum[1]

+and[1]+or[1]

+fctn[0] +fctn[1]

+enbl+c[0]+c[1]

+sum[2]

+and[2]+or[2]

+fctn[2]

+enbl+c[0]+c[1]

+sum[3]

+and[3]+or[3]

+fctn[3]

Figure 9.29 Logic diagram for a 4-function ALU.


Page 527

Shift LeftAdder output Σ3 Σ2 Σ1 Σ0

No shift Σ3 Σ2 Σ1 Σ0

Shift left 1 Σ2 Σ1 Σ0 0

Shift left 2 Σ1 Σ0 0 0

Shift left 3 Σ0 0 0 0

Shift RightAdder output Σ3 Σ2 Σ1 Σ0

No shift Σ3 Σ2 Σ1 Σ0

Shift right 1 0 Σ3 Σ2 Σ1

Shift right 2 0 0 Σ3 Σ2

Shift right 3 0 0 0 Σ3

Figure 9.34 Pictorial representation of the shift left and shift right operations.

Adder

cin

a[0]b[0]

a[1]b[1]

a[2]b[2]

a[3]b[3]

s[0]

s[1]

s[2]

s[3]

cout

–Logic 0

+a[0]+b[0]

+a[1]+b[1]

+a[2]+b[2]

+a[3]+b[3]

net_sum[0]

net_sum[1]

net_sum[2]

net_sum[3]


inst1

Figure 9.35 Logic diagram for the adder and high-speed shifter.


Page 528

MUX

s0

d0d1

s1

d3

d2

Enbl

inst6

MUX

s0

d0d1

s1

d3

d2

Enbl

inst7

MUX

s0

d0d1

s1

d3

d2

Enbl

inst8

MUX

s0

d0d1

s1

d3

d2

Enbl

inst9

MUX

s0

d0d1

s1

d3

d2

Enbl

inst2

MUX

s0

d0d1

s1

d3

d2

Enbl

inst3

MUX

s0

d0d1

s1

d3

d2

Enbl

inst4

MUX

s0

d0d1

s1

d3

d2

Enbl

inst5

shiftcount[0]

srmux[0]shiftcount[1]

slmux[0]

shiftright

net_sum[0]

shiftcount[0]shiftcount[1]

shiftright

net_sum[1]


shiftright

net_sum[2]


shiftright

net_sum[3]–Logic 0–Logic 0–Logic 0

srmux[1]

net_sum[1]net_sum[2]net_sum[3]

net_sum[2]net_sum[3]–Logic 0

net_sum[3]–Logic 0–Logic 0

srmux[2]

srmux[2]


shiftleft

net_sum[0]


shiftleft

net_sum[1]net_sum[0]


shiftleft

net_sum[2]net_sum[1]net_sum[0]


shiftleft

net_sum[3]net_sum[2]net_sum[1]net_sum[0]

slmux[1]

–Logic 0–Logic 0–Logic 0

–Logic 0–Logic 0

slmux[2]

slmux[3]

–Logic 0



Page 534

a2 a1 a0× ) b2 b1 b0

Partial product 0 a2b0 a1b0 a0b0Partial product 1 a2b1 a1b1 a0b1Partial product 2 a2b2 a1b2 a0b2

25 24 23 22 21 20

Figure 9.40 General array multiply algorithm for two 3-bit operands.

A[2:0]

B[2:0]

Arraymultiplier

P[5:0] FA i

ai

bi

sumi

ci–1

ci

a

b

s

cin

cout

Figure 9.41 Array multiplier block diagram and full adder block diagram.


Page 535

FAa

b

cin

scout

FAa

b

cin

scout

FAa

b

cin

scout

FAa

b

cin

scout

FAa

b

cin

scout

FAa

b

cin

scout

a1b1net5

a0b1net2

a1b0a2b0 0 0 a0b0

a0b2net8

a1b2net11

net1net4

net3net6net7net10

a2b1

a2b2

net15 net13 net12

net140

25 24 23 22 21 20

net9

inst1

inst2inst5

inst3

inst4

inst6

inst10

inst7

inst8inst11 inst8

inst9inst12

inst13inst15

inst14

p5 p4 p3 p2 p1 p0

Figure 9.42 Array multiplier for 3-bit operands.


Page 542

Y λ

Combinationallogic

Multiplexerarray

Selectinputs

Datainputs

δ(X, Y)Yk(t+1)

Yj(t) λ(X, Y)

Xn

p Zm

δ

Figure 9.47 General block diagram of a synchronous sequential machine using mul-tiplexers for the δ next-state logic.

a

y1 y2 0 0

bz1

0 1c

1 0

d1 1

z2

x1x1'

x2

x2'

z1↑t2↓t

z2 ↑t1↓t

Figure 9.48 State diagram for the synchronous sequential machine of Section 9.38 with Moore- and Mealy-type outputs.


Page 543

y1

y2 0 1

0 x1 1

1 x2 0

y1

y1

y2 0 1

0 x1' 1

1 x2 0

y2

Figure 9.49 Input maps for state flip-flops y1 and y2 .

MUXs0

d0d1

s1

d3

d2

MUXs0

d0d1

s1

d3

d2

y1

D

>

S

R

Mux y1

Mux y2

+clock

+y2+y1

+x2

+x1+Logic 1

–Logic 0

–set_n

–rst_n

y2

D

>

S

R

–x1+Logic 1

–Logic 0

+z1

+z2

+y1+y1

+y2

–clock

inst1

inst2

inst3

inst4

inst5

inst6

net1

net2

Figure 9.50 Logic diagram for the synchronous sequential machine of Figure 9.48.


Page 548

–clock

+z1

+z2

t1 t2 t3 t4New state

Figure 9.55 Timing diagram to illustrate the assertion/deassertion of outputs z1 and z2 .

a

y1 y2 y30 0 0

d0 1 1

b0 0 1

c0 1 0

ez1

1 1 1fz2

1 1 0

x1

x2

x3

x1'

x2'

x3'

z1↑t2↓t z2 ↑t2↓t4

Figure 9.56 State diagram for the Moore machine of Section 9.39. Unused states: 100, 101.


Page 549

Present state Next state J K0 0 0 –0 1 1 –1 0 – 11 1 – 0

0 0 0 1 1 1 10y2y3

y1

0 0 x2' 0 1

1 – – – –

0 1 3 2

4 5 7 6

0 0 0 1 1 1 10y2y3

y1

0 – – – –

1 – – 1 1

0 1 3 2

4 5 7 6

Jy1 Ky1

Present statey1 y2 y3 x2

Next statey1 J y1 K y1

0 0 1 0 1 1 –0 0 1 1 0 0 –

J y1 = y2 ' y3 x2' + y2 y3 ' K y1 = 1

0 0 0 1 1 1 10y2y3

y1

0 x1' 1 – –

1 – – – –

0 1 3 2

4 5 7 6

0 0 0 1 1 1 10y2y3

y1

0 – – 1 0

1 – – 1 1

0 1 3 2

4 5 7 6

Jy2 Ky2


Next statey2 J y2 K y2

0 0 0 0 1 1 –0 0 0 1 0 0 –

J y2 = x1' + y3 K y2 = y1 + y3 Continued on next page

Figure 9.57 Karnaugh maps for state variables y1 , y2 , and y3 .


Page 550

0 0 0 1 1 1 10y2y3

y1

0 x1 – – x3

1 – – – 0

0 1 3 2

4 5 7 6

0 0 0 1 1 1 10y2y3

y1

0 – 0 1 –

1 – – 1 –

0 1 3 2

4 5 7 6

Jy3 Ky3


Next statey3 Jy3 Ky3

0 0 0 0 0 0 –0 0 0 1 1 1 –


Next statey3 Jy3 Ky3

0 1 0 0 0 0 –0 1 0 1 1 1 –

Jy3 = y2 ' x1 + y1 ' y2 x3 Ky3 = y2


0 0 0 1 1 1 10y2y3

y1

0 0 0 0 0

1 – – 1 0

0 1 3 2

4 5 7 6

0 0 0 1 1 1 10y2y3

y1

0 0 0 0 0

1 – – 0 1

0 1 3 2

4 5 7 6

z1 z2

z1 = y1 y3 z2 = y1 y3 '

Figure 9.58 Output maps for z1 and z2 .


Page 551

y1

>K

Set

Reset

J

y2

>K

Set

Reset

J

y3

>K

Set

Reset

J

z2

D

>

S

R

+Logic 1

–set_n–clk–y2+y3–x2+y2–y3

–x1

+y1

+x1–y1+x3

–rst_n

+z1

–y3

+y1

+y2

+y3

+z2

inst1

inst2 inst3inst4

inst5

inst6inst7

inst8

inst9 inst10

inst12

inst13inst14

inst11

net1

net2 net3

net5

net6

net8

net9 net10

net13

+clk

Figure 9.59 Logic diagram for the Moore synchronous sequential machine of Sec-tion 9.39.


Page 557

0 0 0 1 1 1 1 0

– – b 0

a – c 0

– – 0 d 0

a – e 0 0

x1x2

z1

a

b

c

d

– – e f 0e

a – g f 0f

– – e b 1g

Figure 9.63 Primitive flow table for the asynchronous sequential machine of Section 9.3.10.

Page 558

b

c

d

e

f

g

a

Figure 9.64 Merger diagram for the asynchronous sequential machine of Section9.3.10.


Page 559

x1x2 00 01 11 10

– c b

– – m d

a – e e d

– – f

– – i b

– – – –

b

c

a

e

a – g b

1

2

3

4

5

6

7

8

a b,

c

d

f

e

f

– – – –

g g

Figure 9.65 Merged flow table for the asynchronous sequential machine of Section 9.3.10.

Page 560

1

2 6

3 8

4

000

111

001

101

010

110

100

011

7

5

Figure 9.66 Transition diagram for the asynchronous sequential machine of Section 9.3.10.


Page 561

x1 x2 0 0 0 1 1 1 1 0 y1f y2f y3f

0 0 0

0 0 1 – – 001 101

0 1 1 – – – –

0 1 0 – – 010 000

1 1 0 100 – 010 110

1 1 1 – – 111 110

1 0 1 100 – 111 101

1 0 0 000 – – –

Y1e Y2e Y3e

1

2

4

5

6

7

8

3

000 – 001 000a b

c

g

f

e

d

Figure 9.67 Combined excitation map.

00 01 11 10000 0 – 0 0

001 – – 0 1

011 – – – –

010 – – 0 0

110 1 – 0 1

111 – – 1 1

101 1 – 1 1

100 0 – – –

x1 x2 y1f y2f y3f

Y1e

00 01 11 10000 0 – 0 0

001 – – 0 0

011 – – – –

010 – – 1 0

110 0 – 1 1

111 – – 1 1

101 0 – 1 0

100 0 – – –

x1 x2 y1f y2f y3f

Y2e


Figure 9.68 Individual excitation maps for Y1e , Y2e , and Y3e.


Page 562

00 01 11 10000 0 – 1 0

001 – – 1 1

011 – – – –

010 – – 0 0

110 0 – 0 0

111 – – 1 0

101 0 – 1 1

100 0 – – –

x1 x2 y1f y2f y3f

Y3e


Y1e = y3f x2' + y1f y3f + y1f y2f x2'

Y2e = y1f x2 + y2f x2 + y1f y2f x1

Y3e = y2f ' x2 + y3f x2 + y2f ' y3f x1 (9.5)


Page 563

+Y1e

+Y2e

inst1

inst2

inst3

inst4

inst5

inst6

inst7

inst8

inst9

inst10

inst11

inst12

inst13

+Y3e

–x2

+x2

+x1

–rst_n

net1

net2

net3

net5

net6

net7

net9

net10

net11

+z1

Figure 9.69 Logic diagram for the asynchronous sequential machine of Section 9.3.10.


Page 567

a

y1 y2 0 0

bz1

1 0

z2

cz1

1 1

dz2

0 1

x1x2

x3

x2

x3x1

x2x1x3

x1

x2 x3

Figure 9.74 State diagram for the Moore pulse-mode asynchronous sequential ma-chine of Section 9.3.11.


Page 568

y1

y2 0

0 S S

1

1 R R

0 1

2 3

y1

y2 0

0 r r

1

1 s s

0 1

2 3

y1

y2 0

0 r s

1

1 S s

0 1

2 3

y1

y2 0

0 r R

1

1 r s

0 1

2 3

x1 x2 x3Inputs

Latches

Ly1

Ly2

y1

y2 0

0 S S

1

1 s s

0 1

2 3

y1

y2 0

0 S R

1

1 S R

0 1

2 3

Figure 9.75 Input maps for latches Ly1 and Ly2 for the Moore pulse-mode machine of Section 9.3.11.

Page 569

SLy1 = y1 ' x1 + x3

RLy1 = y1 x1

SLy2 = y1 x1 + y2 ' x3

RLy2 = y1 ' x2 + y2 x3 (9.6)

z1 = y1

z2 = y2 (9.7)


Page 570

y2

D

>

S

R

y1

D

>

S

R

δ Y λ

+y1 (z1)

+y2 (z2)

+x2+x3

–y1

+y1

–y2

+y2

–set_n

–rst_n

+x1

+y2

inst1

inst2 inst3

inst4

inst5

inst15

inst6

inst7

inst8

inst9inst10

inst11

inst12inst13

inst14inst16

net1

net2net3

net4

net5

net6

net8

net9net10

net11

net12 net13

net14

net15

Ly1

Ly2

Figure 9.76 Logic diagram for the Moore pulse-mode machine of Figure 9.74.

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