FIGURE 2–1 8051 block diagramepsem.upc.edu/~jesusv/uc8051_web/ppt_mackenzie/... · The 8051...

The 8051 Microcontroller, 4e

By I. Scott MacKenzie and Raphael C.-W. Phan

© 2007 Pearson Education, Inc.

Pearson Prentice Hall

Upper Saddle River, NJ 07458

FIGURE 2–1 8051 block diagram






FIGURE 2–2 8051 pinouts






FIGURE 2–3 Driving the 8051 from a TTL oscillator






FIGURE 2–4 Circuitry for I/O ports






FIGURE 2–5 Relationship between oscillator clock cycles, states, and the machine cycle






FIGURE 2–6 Summary of the 8031 memory spaces






FIGURE 2–7 Summary of the 8051 on chip data memory






FIGURE 2–8 Multiplexing the address bus (low-byte) and data bus






FIGURE 2–9 Accessing external code memory






FIGURE 2–10 Read timing for external code memory






FIGURE 2–11 Timing for MOVX instruction






FIGURE 2–12 Interface to 1K RAM






FIGURE 2–13 Address decoding






FIGURE 2–14 Overlapping the external code and data spaces






FIGURE 2–15 8032/52 memory spaces






FIGURE 2–16 Two circuits for system reset. (a) Manual reset (b) Power-on reset.

FIGURE 2–1 8051 block diagramepsem.upc.edu/~jesusv/uc8051_web/ppt_mackenzie/... · The 8051...

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