Figuras y Tablas - UNED · Figuras y Tablas Material de apoyo a ... VHDL sobre el flujo de la...
Transcript of Figuras y Tablas - UNED · Figuras y Tablas Material de apoyo a ... VHDL sobre el flujo de la...
DISENO Y ANALISIS DE CIRCUITOS DIGITALES CON VHDL
ALFONSO URQUIA, CARLA MARTIN-VILLALBA
EDITORIAL UNED - 7101201GR01A01
Figuras y Tablas
Material de apoyo a la tutorıa de la asignatura
Ingenierıa de Computadores III
del Grado en Ingenierıa Informatica de la UNED
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B`DBCDFig. 1.2
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in_0 in_1
out
in_2 in_3
in_4
in_5
in_6
in_7
in_8
in_9
in_10
in_11
in_12in_13in_14in_15
Fig. 1.4
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Fig. 1.5
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Fig. 1.6
(not a(2)) and(not a(1)) and(not a(0))
(not a(2)) anda(1) anda(0)
a(2) and(not a(1)) and
a(0)
a(2) anda(1) and
(not a(0))
a(2)
a(1)
a(0)
(p1 or p2) or(p3 or p4)
p1
p2
p3
p4
par
Fig. 1.7
process (a) variable tmp : std_logic;
begintmp := '0';for i in 2 downto 0 loop
tmp := tmp xor a(i);end loop;impar <= tmp;
end process;
a(2)
a(1)
a(0)
impar parnot impar
Fig. 1.10
process (a) variable suma, r : integer;
beginsuma := 0;for i in 2 downto 0 loop
if a(i) = '1' thensuma := suma + 1;
end if;end loop;r := suma mod 2;if (r = 0) then
par <= '1';else
par <= '0';end if;
end process;
a(2)
a(1)
a(0)
par
Fig. 1.11
vect_test: processbegin
test_in <= "000"; wait for 200 ns;test_in <= "001"; wait for 200 ns;test_in <= "010"; wait for 200 ns;test_in <= "011"; wait for 200 ns;test_in <= "100"; wait for 200 ns;test_in <= "101"; wait for 200 ns;test_in <= "110"; wait for 200 ns;test_in <= "111"; wait for 200 ns;
end process vect_test;
test_inA[2..0] par
ÉÉÊtest_out
verif : processvariable error_status : boolean;
beginwait on test_in;wait for 100 ns; if ( ( test_in = "000" and test_out = '1' ) or
( test_in = "001" and test_out = '0' ) or( test_in = "010" and test_out = '0' ) or( test_in = "011" and test_out = '1' ) or( test_in = "100" and test_out = '0' ) or( test_in = "101" and test_out = '1' ) or( test_in = "110" and test_out = '1' ) or( test_in = "111" and test_out = '0' ) )
thenerror_status := false;
elseerror_status := true;
end if;assert not error_status
report "Test fallado."severity note;
end process verif;
Fig. 1.12
êë
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Fig. 2.8
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Fig. 2.9
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Fig. 2.10
i0i1
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()* +,-i0i1
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()* +,-i0i1
ds0
()* +,-i0i1
ds0
()* +,-a3b3
a2b2
a1b1
a0b0
d3
d2
d1
d0
s0
Fig. 2.12
i0(0) i0(1) i0(2) i0(3) i0(4) i0(5) i0(6) i0(7)i1(0) i1(1) i1(2) i1(3) i1(4) i1(5) i1(6) i1(7)
y(0) y(1) y(2) y(3) y(4) y(5) y(6) y(7)
Fig. 2.13
parity_IN(0)xor_0
parity
parity_IN(7)
parity_IN(6)
parity_IN(5)
parity_IN(4)
parity_IN(3)
parity_IN(2)
parity_IN(1)
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xor_3xor_4
xor_5
xor_6
Fig. 2.14
0d
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2d
3d
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1i
en
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1ien 0
d1d
2d
3d
0 – – 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Fig. 2.18
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Fig. 2.25
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Fig. 2.27
library IEEE;use IEEE.std_logic_1164.all;
entity resF isend entity resF;
architecture resF of resF issignal s : std_logic;
begin
p1 : processbegin
s <= '1';wait;
end process p1;
p2 : processbegin
s <= '0';wait;
end process p2;
end architecture resF;
std_logic’(‘1’)
std_logic’(‘0’)
s : std_logic
Resuelvestd_logic’(‘X’)
Fig. 3.1
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Fig. 4.10
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Fig. 4.13
3I 2I 1I 0I
0Q1Q2Q3Q
rst
_Shl In_Shr In
ShrShl
Ld
rst Shr ShlLd Operación
0 0 0 0 Mantiene valor
0 0 0 1 Desplaz. Izq.
0 0 1 – Desplaz. Drcha.
0 1 – – Carga paralelo
1 – – – Reset (carga “0000”)
Fig. 5.3
0Q1Q
rst
_Shr In
Shr
…
31Q
rst Shr Operación
0 0 Mantiene valor
0 1 Desplaz. Drcha.
1 – Reset (carga X“00000000”)
Fig. 5.5
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Fig. 5.7
reset
puertaAbierta
coccion
stop_Reset
puertaCerrada
alarmaActivada
puerta’puerta
marcha and t_coccion>0
stop_Reset
puerta
puerta
t_coccion=0
stop_Reset
stop_Reset
t_alarma=0
Fig. 6.19
cno
t_4
and_1
and_2
and_3
and_4
and_5
or_1
or_2
not_3
clock
reset reset_n
D
D
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CLRN
Q
Q
state(1)
state(0)
Q1
Q0
not_1
not_2
Q1
Q0
Q1_n
Q0_n
yor_1
yor_2
c_n
yand_1
yand_2
yand_3
yand_4
yand_5
Fig. 6.23
reset
puertaAbierta
coccion
stop_Reset
puertaCerrada
alarmaActivada
puerta’ puerta
marcha and t_coccion>0
stop_Reset
puerta
puerta
t_coccion=0
stop_Reset
stop_Reset
t_alarma=0
170
58
10
9
1 6 11
7
3
2
14
16
4
1312
15
Fig. 6.27
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