Fifo+ +lifo

Mahin Ani l KumarS1 VLSI De s ign

P2VLD16014

FIFO & LIFO

Contents

Amrita Vishwa Vidyapeetam

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ü FIFOØ What it isØ A pictorial

representationØ TypesØ Verilog CodeØ Applications

üLIFOØWhat it isØA pictorial representation

ØVerilog CodeØApplications

o Fi r s t I n F i r s t Ou t

o A me thod o f Que u ing .

o An In t e r f a c e b /w De s igns .


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FIFO

What it is

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A Pictorial Representation


The re a r e 4 k inds o f F IFO’s

v Sh i f t Re g i s t e r F IFOs

v Exc lus ive Re a d /Wr i t e F IFOs

v Conc ur r e n t Re a d /Wr i t e F IFOs

§ Asynchronous FIFOs

§ Synchronous FIFOs

Types 5


Asynchronous FIFO6


Synchronous FIFO7


A simple FIFO in Verilog

module beh_fifo (rdata, wfull, rempty, wdata,winc, wclk, wrst_n, rinc, rclk, rrst_n);parameter DSIZE = 8;parameter ASIZE = 4;output [DSIZE-1:0] rdata;output wfull;output rempty;input [DSIZE-1:0] wdata;input winc, wclk, wrst_n;input rinc, rclk, rrst_n;reg [ASIZE:0] wptr, wrptr1, wrptr2, wrptr3;reg [ASIZE:0] rptr, rwptr1, rwptr2, rwptr3;parameter MEMDEPTH = 1<<ASIZE;reg [DSIZE-1:0] ex_mem [0:MEMDEPTH-1];always @(posedge wclk or negedge wrst_n)if (!wrst_n) wptr <= 0;else if (winc && !wfull) begin

ex_mem[wptr[ASIZE-1:0]] <= wdata;wptr <= wptr+1;endalways @(posedge wclk or negedge wrst_n)if (!wrst_n) {wrptr3,wrptr2,wrptr1} <= 0;else {wrptr3,wrptr2,wrptr1} <= {wrptr2,wrptr1,rptr};always @(posedge rclk or negedge rrst_n)if (!rrst_n) rptr <= 0;else if (rinc && !rempty) rptr <= rptr+1;always @(posedge rclk or negedge rrst_n)if (!rrst_n) {rwptr3,rwptr2,rwptr1} <= 0;else {rwptr3,rwptr2,rwptr1} <= {rwptr2,rwptr1,wptr};assign rdata = ex_mem[rptr[ASIZE-1:0]];assign rempty = (rptr == rwptr3);assign wfull = ((wptr[ASIZE-1:0] == wrptr3[ASIZE-1:0]) &&(wptr[ASIZE] != wrptr3[ASIZE] ));endmodule

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Ø T h e p r o c e s s i n g s p e e d o f a p r o c e s s o r n e e d n o t b e r e d u c e d

w h e n i t e x c h a n g e s d a t a w i t h a p e r i p h e r a l .

Ø P e r m i t s b l o c k t r a n s f e r o f t h e d a t a .

Ø I t i s p o s s i b l e t o i m p l e m e n t a p r o g r a m m a b l e , d i g i t a l d e l a y

l i n e w i t h m i n i m u m e f f o r t .

Ø C o l l e c t i n g d a t a b e f o r e a n d a f t e r a n e v e n t .

Applications


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o La s t i n f i r s t ou t

o A me thod o f s t a c k ing .

o Use d whe ne ve r you ne e d t o r e me mbe r some th ing you a r e c u r r e n t l y work ing on a nd s t a r t on some th ing ne w.

LIFO

What it is10


LIFO


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Verilog Code

module lifo #( parameter depth = 32, parameter width = 32, parameter log2_depth = log2(depth), parameter log2_depthp1 = log2(depth+1) ) ( input clk, input reset, output reg empty, output reg full, output reg [log2_depthp1-1:0] count, input push, input [width-1:0] push_data, input pop, output [width-1:0] tos );

function integer log2; input [31:0] value; begin

value = value-1; for (log2=0; value>0; log2=log2+1) value = value>>1;

end endfunctionwire writing = push && (count < depth || pop); wire reading = pop && count > 0;reg [log2_depthp1-1:0] next_count; always @(*) if (reset) next_count = 0; else if (writing && !reading) next_count = count+1; else if (reading && !writing) next_count = count-1;

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Code cont . .

else next_count = count;always @(posedge clk) count <= next_count;always @(posedge clk) full <= next_count == depth;

always @(posedge clk) empty <= next_count == 0;wire [log2_depth-1:0] ptr = writing ? count

[log2_depth-1:0] : (count [log2_depth-1:0])-1;reg [width-1:0] mem [depth-1:0];

always @(posedge clk) if (writing && !reading) mem[ptr] <= tos;reg [width-1:0] mem_rd;

always @(posedge clk) if (reading) mem_rd <= mem[ptr];reg [width-1:0] tos_shadow; always @(posedge clk) if (writing) tos_shadow <= push_data;reg use_mem_rd; always @(posedge clk) if (reset) use_mem_rd <= 0; else if (writing) use_mem_rd <= 0; else if (reading) use_mem_rd <= 1; assign tos = use_mem_rd ? mem_rd : tos_shadow;endmodule

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Ø Mos t l y u se d t o p l a c e a n Ac c oun t ing va lue on Inve n to ry.

Applications


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Any Questions

??

Amrita Vishwa Vidyapeetam 15

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Fifo+ +lifo

Engineering

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