Field-Effect Transistors(FETs) are unipolardevices, and have twobig advantages over

bipolar transistors: one is thatthey have a near-infinite inputresistance and thus offer near-infinite current and powergain; the other is that theirswitching action is not marredby charge-storage problems,and they thus outperformmost bipolars in terms of digi-tal switching speeds.

Several different basictypes of FETs are available,and this opening episodelooks at their basic operatingprinciples. Parts 2 to 4 of theseries will show practical waysof using FETs.

FET BASICS

An FET is a three-terminal ampli-fying device. Its terminals are knownas the source, gate, and drain, andcorrespond respectively to the emit-ter, base, and collector of a normaltransistor. Two distinct families ofFETs are in general use. The first ofthese is known as ‘junction-gate’types of FETs; this term generallybeing abbreviated to either JUGFETor (more usually) JFET.

The second family is known aseither ‘insulated-gate’ FETs or MetalOxide Semiconductor FETs, andthese terms are generally abbreviat-ed to IGFET or MOSFET, respectively.‘N-channel’ and ‘p-channel’ versionsof both types of FET are available,just as normal transistors are avail-able in npn and pnp versions. Figure1 shows the symbols and supplypolarities of both types of bipolartransistor, and compares them withboth JFET versions.

Figure 2 illustrates the basic con-struction and operating principles ofa simple n-channel JFET. It consists ofa bar of n-type semiconductor mate-

rial with a drain terminal at one endand a source terminal at the other. Ap-type control electrode or gate sur-rounds (and is joined to the surfaceof) the middle section of the n-typebar, thus forming a p-n junction.

In normal use, the drain terminalis connected to a positive supply andthe gate is biased at a value that isnegative (or equal) to the source volt-age, thus reverse-biasing the JFET’sinternal p-n junction, and account-ing for its very high input imped-ance.

With zero gate bias applied, a current flow from drain to source viaa conductive ‘channel’ in the n-typebar is formed. When negative gatebias is applied, a high resistanceregion is formed within the junction,and reduces the width of the n-typeconduction channel and thusreduces the magnitude of the drain-to-source current. As the gate bias isincreased, the ‘depletion’ regionspreads deeper into the n-type chan-nel, until eventually, at some ‘pinch-off’ voltage value, the depletion layer

becomes so deep that conductionceases.

Thus, the basic JFET of Figure 2passes maximum current when itsgate bias is zero, and its current isreduced or ‘depleted’ when the gatebias is increased. It is thus known asa ‘depletion-type’ n-channel JFET. Ap-channel version of the device can(in principle) be made by simplytransposing the p and n materials.

JFET DETAILS

Figure 3 shows the basic form ofconstruction of a practical n-channelJFET; a p-channel JFET can be madeby transposing the p and n materials.All JFETs operate in the depletionmode, as already described. Figure 4shows the typical transfer character-istics of a low-power n-channel JFET,and illustrates some important fea-tures of this type of device. The mostimportant characteristics of the JFETare as follows:

(1). When a JFET is connected toa supply withthe polarityshown inFigure 1(drain +ve for

an n-channel FET, -ve for a p-channelFET), a drain current (ID) flows andcan be controlled via a gate-to-sourcebias voltage VGS.

(2). ID is greatest when VGS = 0,and is reduced by applying a reversebias to the gate (negative bias in ann-channel device, positive bias in ap-type). The magnitude of VGS need-ed to reduce ID to zero is called the‘pinch-off’ voltage, VP, and typicallyhas a value between 2 and 10 volts.The magnitude of ID when VGS = 0 isdenoted IDSS, and typically has avalue in the range 2 to 20mA.

(3). The JFET’s gate-to-sourcejunction has the characteristics of asilicon diode. When reverse-biased,gate leakage currents (IGSS) are onlya couple of nA (1nA = .001µA) atroom temperature. Actual gate sig-nal currents are only a fraction of annA, and the input impedance of thegate is typically thousands ofmegohms at low frequencies. Thegate junction is shunted by a few pF,so the input impedance falls as fre-quency rises.

If the JFET’s gate-to-source junc-tion is forward-biased, it conductslike a normal silicon diode. If it isexcessively reverse-biased, it

PRINCIPLES AND CIRCUITSPart 1

by Ray Marston Ray Marston explains FET(Field-Effect Transistor)basics in this openingepisode of this new four-part series.

FET

Figure 1.Comparison oftransistor andJFET symbols,notations, and

supply polarities.

Figure 2. Basic structure of a simple n-channel JFET,

showing how channel width iscontrolled via the gate bias.

Field-Effect Transistors

1 MAY 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

Figure 3.Constructionof n-channel

JFET.

Figure 4.Idealized transfer characteristicsof ann-channel JFET.

Figure 5. An n-channelJFET can beused as avoltage-

controlledresistor.

avalanches like a zener diode. Ineither case, the JFET suffers no dam-age if gate currents are limited to afew mA.

(4). Note in Figure 4 that, foreach VGS value, drain current ID riseslinearly from zero as the drain-to-source voltage (VDS) is increasedfrom zero up to some value at whicha ‘knee’ occurs on each curve, andthat ID then remains virtually con-

stant as VDS is increased beyond theknee value. Thus, when VDS is belowthe JFET’s knee value, the drain-to-source terminals act as a resistor, RDS,with a value dictated by VGS, and canthus be used as a voltage-variableresistor, as in Figure 5.

Typically, RDS can be varied froma few hundred ohms (at VGS = 0) tothousands of megohms (at VGS = VP),enabling the JFET to be used as avoltage-controlled switch (Figure 6)or as an efficient ‘chopper’ (Figure 7)that does not suffer from offset-volt-age or saturation-voltage problems.

Also note in Figure 4 that whenVDS is above the knee value, the IDvalue is controlled by the VGS valueand is almost independent of VDS,i.e., the JFET acts as a voltage-con-trolled current generator. The JFETcan be used as a fixed-value currentgenerator by either tying the gate tothe source as in Figure 8(a), or byapplying a fixed negative bias to thegate as in Figure 8(b). Alternatively, itcan (when suitably biased) be used asa voltage-to-current signal amplifier.

(5). FET ‘gain’ is specified astransconductance, gm, and denotesthe magnitude of change of draincurrent with gate voltage, i.e., a gmof 5mA/V signifies that a VGS varia-tion of one volt produces a 5mAchange in ID. Note that the form I/Vis the inverse of the ohms formula,so gm measurements are oftenexpressed in ‘mho’ units. Usually, gmis specified in FET data sheets interms of mmhos (milli-mhos) orµmhos (micro-mhos). Thus, a gm of5mA/V = 5-mmho or 5000-µmho.

In most practical applications,the JFET is biased into the linearregion and used as a voltage amplifi-er. Looking at the n-channel JFET, itcan be used as a common sourceamplifier (corresponding to the bipo-lar npn common emitter amplifier)by using the basic connections inFigure 9.

Alternatively, the common drainor source follower (similar to thebipolar emitter follower) configura-tion can be obtained by using theconnections in Figure 10, or the com-mon gate (similar to common base)

configuration can beobtained by usingthe basic Figure 11circuit. In practice,fairly accurate bias-ing techniques (dis-cussed in Part 2 ofthis series) must beused in these cir-cuits.

THE IGFET/MOSFET

The second (and most impor-tant) family of FETs are those knownunder the general title of IGFET orMOSFET. In these FETs, the gate ter-minal is insulated from the semicon-ductor body by a very thin layer of sil-icon dioxide, hence the title‘Insulated Gate Field EffectTransistor,’ or IGFET. Also, the devicesgenerally use a ‘Metal-Oxide Silicon’semiconductor material in their con-struction, hence the alternative titleof MOSFET.

Figure 12 shows the basic con-struction and the standard symbol ofthe n-channel depletion-mode FET. Itresembles the JFET, except that itsgate is fully insulated from the bodyof the FET (as indicated by the Figure12(b) symbol) but, in fact, operateson a slightly different principle to theJFET.

It has a normally-open n-typechannel between drain and source,but the channel width is controlled bythe electrostatic field of the gate bias.The channel can be closed by applyingsuitable negative bias, or can beincreased by applying positive bias.

In practice, the FET substrate maybe externally available, making a four-

terminal device, or may be internallyconnected to the source, making athree-terminal device.

An important point about theIGFET/MOSFET is that it is also avail-able as an enhancement-mode device,in which its conduction channel is nor-mally closed but can be opened byapplying forward bias to its gate.

Figure 13 shows the basic con-struction and the symbol of the n-channel version of such a device.Here, no n-channel drain-to-sourceconduction path exists through the p-type substrate, so with zero gate biasthere is no conduction between drainand source; this feature is indicated inthe symbol of Figure 13(b) by thegaps between source and drain.

To turn the device on, significantpositive gate bias is needed, andwhen this is of sufficient magnitude, itstarts to convert the p-type substratematerial under the gate into an n-channel, enabling conduction to takeplace.

Figure 14 shows the typical trans-fer characteristics of an n-channelenhancement-mode IGFET/MOSFET,and Figure 15 shows the VGS/IDcurves of the same device whenpowered from a 15V supply. Notethat no ID current flows until the gatevoltage reaches a ‘threshold’ (VTH)value of a few volts, but that beyondthis value, the drain current rises in anon-linear fashion.

Also note that the transfer graphis divided into two characteristicregions, as indicated (in Figure 14) bythe dotted line, these being the ‘tri-ode’ region and the ‘saturated’region. In the triode region, thedevice acts like a voltage-controlled

Figure 7. An n-channel JFET can be used asan electronic chopper.

Figure 6. An n-channel JFET can be used as a

voltage-controlled switch.

Figure 8. An n-channel JFET

can be used as a constant-current

generator.

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/MAY 2000 2

Figure 9. Basic n-channel common-source amplifier

JFET circuit.

Figure 10. Basic n-channel common-drain

(source-follower) JFET circuit.

Figure 11. Basic n-channel common-gate JFET circuit.

Figure 12. Construction (a) and symbol (b)

of n-channel depletion-modeIGFET/MOSFET.

Figure 13. Construction (a) and symbol (b)

of n-channel enhancement-mode

IGFET/MOSFET.

Figure 14. Typical transfer

characteristics of n-channel

enhancement-modeIGFET/MOSFET.

resistor; in the saturated region, itacts like a voltage-controlled con-stant-current generator.

The basic n-channel MOSFETs ofFigures 12 and 13 can — in principle— be converted to p-channel devicesby simply transposing their p and nmaterials, in which case their sym-bols must be changed by reversingthe directions of their substratearrows.

A number of sub-variants of theMOSFET are in common use. Thetype known as ‘DMOS’ uses a dou-ble-diffused manufacturing tech-nique to provide it with a very shortconduction channel and a conse-quent ability to operate at very highswitching speeds. Several otherMOSFET variants are described in theremainder of this opening episode.

Note that the very high gateimpedance of MOSFET devicesmakes them liable to damage fromelectrostatic discharges and, for thisreason, they are often provided withinternal protection via integral diodesor zeners, as shown in the examplein Figure 16.

VFET DEVICES

In a normal small-signal JFET or

MOSFET, the main signal currentflows ‘laterally’ (see Figures 3, 12,and 13) through the device’s con-ductive channel. This channel is verythin, and maximum operating cur-rents are consequently very limited(typically to maximum values in therange 2 to 40mA).

In post-1970 times, many manu-facturers have tried to produce viablehigh-power/high-current versions ofthe FET, and the most successful ofthese have relied on the use of a ‘ver-tical’ (rather than lateral) flow of cur-rent through the conductive channelof the device. One of the best knownof these devices is the ‘VFET,’ anenhancement-mode power MOSFETwhich was first introduced bySiliconix way back in 1976.

Figure 17 shows the basic struc-ture of the original Siliconix VFET. Ithas an essentially four-layer struc-ture, with an n-type source layer atthe top, followed by a p-type ‘body’layer, an epitaxial n-type layer, and(at the bottom) an n-type drain layer.Note that a ‘V’ groove (hence the‘VFET’ title) passes through the firsttwo layers and into the third layer ofthe device, and is electrostatically

connected (via aninsulating silicondioxide film) tothe gate terminal.

If the gate isshorted to thesource, and thedrain is made pos-itive, no drain-to-source currentflows, becausethe diode formedby the p and nmaterials isreverse -b iased.But if the gate is

made positive to the source, theresulting electrostatic field convertsthe area of p-type material adjacentto the gate into n-type material, thuscreating a conduction channel in theposition shown in Figure 17 andenabling current to flow verticallyfrom the drain to the source.

As the gate becomes more posi-tive, the channel width increases,enabling thedrain-to-sourcecurrent toincrease as thedrain-to-sourcer e s i s t a n c edecreases. Thisbasic VFET canthus pass reason-ably high cur-rents (typicallyup to 2A) with-out creatingexcessive currentdensity withinthe channelregions.

The originalSiliconix VFETdesign of Figure17 was success-ful, but imper-fect. The sharp

bottom of its V-groove caused anexcessive electric field at this pointand restricted the device’s operatingvoltage. Subsequent to the originalVFET introduction, Intersil introducedtheir own version of the ‘VMOS’ tech-nique, with a U-shaped groove (plusother modifications) that improveddevice reliability and gave higher max-imum operating currents and volt-ages. In 1980, Siliconix added theseand other modifications to their ownVFET devices, resulting in furtherimprovements in performance.

OTHER POWER FETs

Several manufacturers have pro-duced viable power FETs withoutusing ‘V’- or ‘U’-groove techniques,but still relying on the vertical flow ofcurrent between drain and source. Inthe 1980s, Hitachi produced both p-channel and n-channel power MOS-FET devices with ratings up to 8A and200V; these devices were intendedfor use mainly in audio and low-RFapplications.

Supertex of California andFarranti of England pioneered thedevelopment of a range of powerMOSFETS with the general title of‘vertical DMOS.’ These featured highoperating voltages (up to 650V), highcurrent rating (up to 16A), low onresistance (down to 50 milliohms),and very fast operating speeds (up to2GHz at 1A, 500MHz at 10A).

Siemens of West Germany used amodified version of DMOS, known asSIPMOS, to produce a range of n-channel devices with voltage ratingsas high as 1kV and with current rat-ings as high as 30A.

One International Rectifier solu-tion to the power MOSFET problem isa device which, in effect, houses avast array of parallel-connected low-power vertical MOSFETs or ‘cells’which share the total current equallybetween them, and thus act like a sin-gle high-power MOSFET, as indicatedin Figure 18. These devices are namedHEXFET, after the hexagonal structureof these cells, which have a density of about 100,000 persquare centimeter of semiconductor

material.Several manufacturers produce

power MOSFETs that each comprise alarge array of parallel-connected low-power lateral (rather than horizontal)MOSFET cells that share the totaloperating current equally betweenthem; the device thus acts like a sin-gle high-power MOSFET. These high-power devices are known as lateralMOSFETs or L-MOSFETs, and give aperformance that is particularly usefulin super-fi audio power amplifierapplications.

Note that, in parallel-connectedMOSFETs (as used in the internalstructure of the HEXFET and L-MOS-FET devices described above), equalcurrent sharing is ensured by the con-duction channel’s positive tempera-ture coefficient; if the current in oneMOSFET becomes excessive, theresultant heating of its channel raisesits resistance, thus reducing its cur-rent flow and tending to equalize itwith that of other parallel-connectedMOSFETs. This feature makes suchpower MOSFETs almost immune tothermal runaway problems.

Today, a vast range of powerMOSFET types are manufactured.‘Low voltage’ n-channel types arereadily available with voltage/currentratings as high as 100V/75A, and‘high voltage’ ones with ratings ashigh as 500V/25A.

One of the most importantrecent developments in the power-MOSFET field has been the introduc-tion of a variety of so-called ‘intelli-gent’ or ‘smart’ MOSFETs with built-in overload protection circuitry; theseMOSFETs usually carry a distinctiveregistered trade name. Philipsdevices of this type are known asTOPFETs (Temperature and OverloadProtected MOSFETs); Figure 19shows (in simplified form) the basicinternal circuitry and the circuit sym-bol of the TOPFET.

The Siemens version of thesmart MOSFET is known as the PRO-FET. PROFET devices incorporate pro-tection against damage from shortcircuits, over temperature, overload,and electrostatic discharge (ESD).International Rectifier produce a

3 MAY 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

Figure 15. Typical VGS/ID

characteristics of n-channel

enhancement-modeIGFET/MOSFET

Figure 16.Internally-protected n-channel

depletion-modeIGFET/MOSFET.

Figure 17. Basic structure of the VFET power device.

Figure 18. The IR HEXFET comprisesa balanced matrix of parallel-

connected low-power MOSFETs,which are equivalent to a single

high-power MOSFET.

Figure 19. The basicinternal circuitry (a)

and the circuit symbol(b) of the TOPFET(Temperature and

Overload ProtectedMOSFET).

range of smart n-channel MOSFETknown as SMARTFETs; these incor-porate protection against damagefrom short circuits, over tempera-ture, overvoltage, and ESD.

Finally, yet another recent andimportant development in the n-channel power MOSFET field, hasbeen the production — by variousmanufacturers — of a range of highpower devices known as IGBTs(Insulated Gate Bipolar Transistors),which have a MOSFET-type input and

an internally pro-tected high-voltagehigh-current bipo-lar transistor out-put. Figure 20shows the normalcircuit symbol of

the IGBT. Devices of this type usuallyhave voltage/current/power ratingsranging from as low as600V/6A/33W (in the device knownas the HGTD3N603), to as high as1200V/520A/3000W (in the deviceknown as the MG400Q1US51).

CMOS BASICS

One major FET application is indigital ICs. The best known range ofsuch devices use the technology

known as CMOS, and rely on the useof complementary pairs of MOSFETs.Figure 21 illustrates basic CMOS prin-ciples. The basic CMOS device com-prises a p-type and n-type pair ofenhancement-mode MOSFETs, wiredin series, with their gates shortedtogether at the input and their drainstied together at the output, asshown in Figure 21(a). The pair aremeant to use logic-0 or logic-1 digitalinput signals, and Figures 21(b) and21(c), respectively, show the device’sequivalent circuit under these condi-tions.

When the input is at logic-0, theupper (p-type) MOSFET is biased fullyon and acts like a closed switch, andthe lower (n-type) MOSFET is biasedoff and acts like an open switch; theoutput is thus effectively connectedto the positive supply line (logic-1) viaa series resistance of about 100R.

When the input is at logic-1, theMOSFET states are reversed, with Q1acting like an open switch and Q2acting like a closed switch, so theoutput is effectively connected toground (logic-0) via 100R. Note inboth cases that the entire signal cur-rent is fed to the load, and none isshunted off by the CMOS circuitry;this is a major feature of CMOS tech-nology. NV

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/MAY 2000 4

Figure 20. Normal circuitsymbol of the IGBT

(Insulated Gate BipolarTransistor).

Figure 21. Basic CMOS circuit (a), and its equivalent with (b) a logic-0 input and (c) a logic-1 input.

Last month’s openingepisode explained (amongother things) the basic oper-ating principles of JFETs.JFETs are low-power devices

with a very high input resistanceand invariably operate in the deple-tion mode, i.e., they pass maximumcurrent when the gate bias is zero,and the current is reduced (‘deplet-ed’) by reverse-biasing the gate terminal.

Most JFETs are n-channel(rather than p-channel) devices.Two of the oldest and best knownn-channel JFETs are the 2N3819and the MPF102, which are usuallyhoused in TO92 plastic packageswith the connections shown inFigure 1; Figure 2 lists the basiccharacteristics of these two devices.

This month’s article looks atbasic usage information and appli-cations of JFETs. All practical cir-cuits shown here are specificallydesigned around the 2N3819, butwill operate equally well whenusing the MPF102.

JFET BIASING

The JFET can be used as a lin-ear amplifier by reverse-biasing itsgate relative to its source terminal,thus driving it into the linear region.Three basic JFET biasing techniquesare in common use. The simplest ofthese is the ‘self-biasing’ systemshown in Figure 3, in which thegate is grounded via Rg, and anycurrent flowing in Rs drives thesource positive relative to the gate,thus generating reverse bias.

Suppose that an ID of 1mA iswanted, and that a VGS bias of -2V2is needed to set this condition; thecorrect bias can obviously beobtained by giving Rs a value of2k2; if ID tends to fall for some rea-son, VGS naturally falls as well, andthus makes ID increase and counterthe original change; the bias is thusself-regulating via negative feed-back.

In practice, the VGS value need-ed to set a given ID varies widelybetween individual JFETS, and theonly sure way of getting a precise IDvalue in this system is to make Rs avariable resistor; the system is, how-ever, accurate enough for many

applications, and is the most widelyused of the three biasing methods.

A more accurate way of biasingthe JFET is via the ‘offset’ system ofFigure 4(a), in which divider R1-R2applies a fixed positive bias to thegate via Rg, and the source voltageequals this voltage minusVGS. If the gate voltage islarge relative to VGS, ID isset mainly by Rs and is notgreatly influenced by VGS

variations. This system thusenables ID values to be setwith good accuracy andwithout need for individualcomponent selection.Similar results can beobtained by grounding thegate and taking the bot-tom of Rs to a large negative volt-age, as in Figure 4(b).

The third type of biasing systemis shown in Figure 5, in which con-stant-current generator Q2 sets theID, irrespective of the JFET character-istics. This system gives excellentbiasing stability, but at the expenseof increased circuit complexity and cost.

In the three biasing systemsdescribed, Rg can have any value upto 10M, the top limit being imposedby the volt drop across Rg causedby gate leakage currents, which mayupset the gate bias.

SOURCE FOLLOWER CIRCUITS

When used as linear amplifiers,JFETs are usually used in either thesource follower (common drain) orcommon-source modes. The sourcefollower gives a very high inputimpedance and near-unity voltagegain (hence the alternative title of‘voltage follower’).

Figure 6 shows a simple self-biasing (via RV1) source follower;RV1 is used to set a quiescent R2volt-drop of 5V6. The circuit’s actualinput-to-output voltage gain is 0.95.A degree of bootstrapping isapplied to R3 and increases its effec-tive impedance; the circuit’s actualinput impedance is 10M shunted by10pF, i.e., it is 10M at very low fre-quencies, falling to 1M0 at about16kHz and 100k at 160kHz, etc.

Figure 7 shows a source follow-

er with offset gate biasing. Overallvoltage gain is about 0.95. C2 is abootstrapping capacitor and raisesthe input impedance to 44M, shunt-ed by 10pF.

Figure 8 shows a hybrid (JFETplus bipolar) source follower. Offsetbiasing is applied via R1-R2, andconstant-current generator Q2 actsas a very high-impedance sourceload, giving the circuit an overallvoltage gain of 0.99. C2 bootstrapsR3’s effective impedance up to

PRINCIPLES AND CIRCUITSPart 2

by Ray Marston Ray Marston looks atpractical JFET circuits inthis second episode ofthis four-part series.

FET

Field-Effect Transistors

Figure 1.Outline and

connections ofthe 2N3819 andMPF102 JFETs.

Parameter 2N3918 MPF102

VDS max (= max. drain-to-source voltage) 25V 25VVDG max (= max. drain-to-gate voltage) 25V 25VVGS max (= max. gate-to-source voltage) -25V -25VIDSS (= drain-to-source current with VGS = 0V) 2-20mA 2-20mAIGSS max (= gate leakage current at 25° C) 2nA 2nAPT max (= max. power dissipation, in free air) 200mW 310mW

Figure 2. Basic characteristics of the 2N3819 and MPF102 n-channel JFETs.

Figure 3. Basic JFET ‘self-biasing’ system.

1 JUNE 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

Figure 4. Basic JFET

‘offset-biasing’system.

Figure 5. Basic JFET ‘constant-current’ biasing

system.Figure 6. Self-biasing

source-follower. Zin = 10M.

1000M, which is shunted by theJFET’s gate impedance; the inputimpedance of the complete circuitis 500M, shunted by 10pF.

Note then if the high effectivevalue of input impedance of thiscircuit is to be maintained, theoutput must either be taken toexternal loads via an additionalemitter follower stage (as showndotted in the diagram) or must betaken only to fairly high imped-ance loads.

COMMON SOURCE AMPLIFIERS

Figure 9 shows a simple self-biasing common source amplifier;RV1 is used to set a quiescent5V6 across R3. The RV1-R2 bias-ing network is AC-decoupled viaC2, and the circuit gives a voltagegain of 21dB (= x12), and has a±3dB frequency response thatspans 15Hz to 250kHz and aninput impedance of 2M2 shuntedby 50pF. (This high shunt value isdue to Miller feedback, whichmultiplies the JFET’s effectivegate-to-drain capacitance by thecircuit’s x12 Av value.)

Figure 10 shows a simple self-biasing headphone amplifier thatcan be used with headphoneimpedances of 1k0 or greater. Ithas a built-in volume control(RV1), has an input impedance of2M2, and can use any supply inthe 9V to 18V range.

Figure 11 shows a self-biasingadd-on pre-amplifier that gives avoltage gain in excess of 20dB,has a bandwidth that extendsbeyond 100kHz, and has an inputimpedance of 2M2. It can beused with any amplifier that canprovide a 9V to 18V powersource.

JFET common source ampli-fiers can — when very high biasingaccuracy is needed — be designedusing either the ‘offset’ or ‘con-stant-current’ biasing technique.Figures 12 and 13 show circuits ofthese types. Note that the ‘offset’circuit of Figure 12 can be usedwith supplies in the range 16V to20V only, while the hybrid circuitof Figure 13 can be used with anysupply in the 12V to 20V range.Both circuits give a voltage gain of21dB, a ±3dB bandwidth of 15Hzto 250kHz, and an input imped-

ance of 2M2.

DC VOLTMETERS

Figure 14 shows a JFET used tomake a very simple and basic three-range DC voltmeter with a maxi-mum FSD sensitivity of 0.5V and aninput impedance of 11M1. Here,R6-RV2 and R7 form a potentialdivider across the 12V supply and —if the R7-RV2 junction is used as thecircuit’s zero-voltage point — setsthe top of R6 at +8V and the bot-tom of R7 at -4V. Q1 is used as asource follower, with its gategrounded via the R1 to R4 networkand is offset biased by taking itssource to -4V via R5; it consumesabout 1mA of drain current.

In Figure 14, R6-RV2 and Q1-R5act as a Wheatstone bridge net-work, and RV2 is adjusted so thatthe bridge is balanced and zero cur-rent flows in the meter in theabsence of an input voltage at Q1gate. Any voltage applied to Q1gate then drives the bridge out ofbalance by a proportional amount,which can be read directly on themeter.

R1 to R3 form a range multipli-er network that — when RV1 is cor-rectly adjusted — gives FSD ranges

of 0.5V, 5V, and 50V. R4 protectsQ1’s gate against damage if exces-sive input voltage is applied to thecircuit.

To use the Figure 14 circuit,first trim RV2 to give zero meterreading in the absence of an inputvoltage, and then connect an accu-rate 0.5V DC to the input and trimRV1 to give a precise full-scalemeter reading. Repeat these adjust-ments until consistent zero and full-scale readings are obtained; theunit is then ready for use.

In practice, this very simple cir-cuit tends to drift with variations insupply voltage and temperature,and fairly frequent trimming of thezero control is needed. Drift can begreatly reduced by using a zener-stabilized 12V supply.

Figure 15 shows an improvedlow-drift version of the JFET volt-meter. Q1 and Q2 are wired as adifferential amplifier, so any driftoccurring on one side of the circuitis automatically countered by a simi-lar drift on the other side, andgood stability is obtained. The cir-cuit uses the ‘bridge’ principle, withQ1-R5 forming one side of thebridge and Q2-R6 forming theother. Q1 and Q2 should ideally bea matched pair of JFETs, with IDSS

Figure 7. Source follower withoffset biasing. Zin = 44M.

Figure 8. Hybrid source follower. Zin = 500M.

Figure 9. Simple self-biasing common-source amplifier.

Figure 12. Common-source amplifier with offset gate biasing.

Figure 10. Simple headphoneamplifier.

Figure 14. Simple three-range DC voltmeter.

Figure 13. ‘Hybrid’ common-sourceamplifier.

Figure 11. General-purpose add-on pre-amplifier.

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/JUNE 2000 2

Figure 15.Low-drift

three-rangeDC volt-meter.

values matched within 10%. The cir-cuit is set up in the same way asthat of Figure 14.

MISCELLANEOUS JFET CIRCUITS

To conclude this month’s arti-cle, Figures 16 to 19 show a miscel-laneous collection of useful JFET cir-cuits. The Figure 16 design is thatof a very-low-frequency (VLF)astable or free-running multivibrator;its on and off periods are controlledby C1-R4 and C2-R3, and R3 and R4can have values up to 10M.

With the values shown, the cir-cuit cycles at a rate of once per 20seconds, i.e., at a frequency of0.05Hz; start button S1must be held closed forat least one second toinitiate the astableaction.

Figure 17 shows —in basic form — how aJFET and a 741 op-ampcan be used to make avoltage-controlled ampli-fier/attenuator. The op-amp is used in theinverting mode, with itsvoltage gain set by theR2/R3 ratio, and R1 andthe JFET are used as avoltage-controlled inputattenuator.

When a large nega-

tive control voltage is fed toQ1 gate, the JFET acts like a near-infinite resistance and causes zerosignal attenuation, so the circuitgives high overall gain but, whenthe gate bias is zero, the FET actslike a low resistance and causesheavy signal attenuation, so the cir-cuit gives an overall signal loss.

Intermediate values of signalattenuation and overall gain or losscan be obtained by varying the con-trol voltage value.

Figure 18 shows how this volt-age-controlled attenuator techniquecan be used to make a ‘constantvolume’ amplifier that produces anoutput signal level change of only7.5dB when the input signal level isvaried over a 40dB range (from

3mV to 300mVRMS).

The circuit canaccept input signallevels up to a maxi-mum of 500mVRMS Q1 and R4are wired in seriesto form a voltage-controlled attenua-tor that controlsthe input signallevel to commonemitter amplifier

Q2, which has its output bufferedvia emitter follower Q3.

Q3’s output is used to generate(via C5-R9-D1-D2-C4-R5) a DC con-trol voltage that is fed back to Q1’sgate, thus forming a DC negative-feedback loop that automaticallyadjusts the overall voltage gain sothat the output signal level tends toremain constant as the input signallevel is varied, as follows.

When a very small input signalis applied to the circuit, Q3’s outputsignal is also small, so negligible DCcontrol voltage is fed to Q1’s gate;Q1 thus acts as a low resistanceunder this condition, so almost thefull input signal is applied to Q2base, and the circuit gives high over-all gain.

When a large inputsignal is applied to the cir-cuit, Q3’s output signaltends to be large, so a

large DC negative control voltage isfed to Q1’s gate; Q1 thus acts as ahigh resistance under this condition,so only a small part of the input sig-nal is fed to Q2’s base, and the cir-cuit gives low overall gain.

Thus, the output level staysfairly constant over a wide range ofinput signal levels; this characteris-tic is useful in cassette recorders,intercoms, and telephone ampli-fiers, etc.

Finally, Figure 19 shows a JFETused to make a DC-to-AC converteror ‘chopper’ that produces a square-wave output with a peak amplitudeequal to that of the DC input volt-age.

In this case, Q1 acts like anelectronic switch that is wired inseries with R1 and is gated on andoff at a 1kHz rate via the Q2-Q3astable circuit, thus giving the DC-to-AC conversion. Note that Q1’s gate-drive signal amplitude can be variedvia RV1; if too large a drive is used,Q1’s gate-to-source junction startsto avalanche, causing a small spikevoltage to break through the drainand give an output even when noDC input is present.

To prevent this, connect a DCinput and then trim RV1 until theoutput is just on the verge ofdecreasing; once set up in this way,the circuit can be reliably used tochop voltages as small as a fractionof a millivolt. NV

3 JUNE 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

Figure 16. VLF astable multivibrator.

Figure 17. Voltage-controlled amplifier/attenuator.

Figure 18. Constant-volume amplifier.

Figure 19. DC-to-AC converter or ‘chopper’ circuit.

Part 1 of this seriesexplained (among otherthings) the basic operatingprinciples of the MOSFET(or IGFET), and pointed

out that complementary enhance-ment-mode pairs of these devicesform the basis of the digital tech-nology known as CMOS.

The present episode of theseries looks at practical applicationsof MOSFETs and CMOS-basedMOSFET devices.

A MOSFET INTRODUCTION

MOSFETs are available in bothdepletion-mode and enhancement-mode versions. Depletion-modetypes give a performance similar toa JFET, but with a far higher inputresistance (i.e., with a far higherlow-frequency input impedance).

Some depletion-modeMOSFETs are equipped with twoindependent gates, enabling thedrain-to-source currents to be con-trolled via either one or both ofthe gates; these devices (which areoften used as signal mixers in VHFtuners) are known as dual-gate ortetrode MOSFETs, and use the sym-bol shown in Figure 1.

Most modern MOSFETs areenhancement-mode devices, inwhich the drain-to-source conduc-tion channel is closed when thegate bias is zero, but can beopened by applying a forward gate

bias. This ‘normally open-circuit’action is implied by the gapsbetween source and drain in thedevice’s standard symbol, shown inFigure 2(a), which depicts an n-channel MOSFET (the arrow headis reversed in a p-channel device).In some devices, the semiconduc-tor substrate is made externallyavailable, creating a ‘four-terminal’MOSFET, as shown in Figure 2(b).

Figure 3 shows typical transfercharacteristics of an n-channelenhancement-mode MOSFET, andFigure 4 shows the VGS/ID curvesof the same device when poweredfrom a 15V supply. Note that nosignificant ID current flows until thegate voltage rises to a threshold(VTH) value of a few volts but that,beyond this value, the drain currentrises in a non-linear fashion.

Also note that the Figure 3graph is divided into two character-istic regions, as indicated by thedotted line; these being the ‘tri-ode’ region, in which the MOSFETacts like a voltage-controlled resis-tor, and the ‘saturated’ region,’ in

which it acts like a voltage-controlled constant-currentgenerator.

Because of their veryhigh input resistances,MOSFETs are vulnerable todamage via electrostatic dis-charges; for this reason,

MOSFETs are some-times provided withintegral protectionvia diodes or zen-ers.

THE 4007UB

The easiest andcheapest practicalway of learning about enhance-ment-mode MOSFETs is via a4007UB IC, which is the simplestmember of the popular CMOS‘4000-series’ digital IC range, andactually houses six useful MOSFETsin a single 14-pin DIL package.

Figure 5 shows the functionaldiagram and pin numbers of the4007UB, which houses two com-plementary pairs of independently-accessible MOSFETs and a thirdcomplementary MOSFET pair thatis connected as a standard CMOSinverter stage.

Each of the IC’s three indepen-dent input terminals is internallyconnected to the standard CMOSprotection network shown inFigure 6.

Within the IC, Q1, Q3, and Q5are p-channel MOSFETs, and Q2,Q4, and Q6 are n-channel types.Note that the performance graphsof Figures 3 and 4 actually apply tothe individual n-channel deviceswithin this CMOS IC.

The 4007UB usage rules aresimple. In any given application, allunused IC elements must be dis-abled. Complementary pairs ofMOSFETs can be disabled by con-necting them as standard CMOSinverters (i.e., gate-to-gate andsource-to-source) and tying theirinputs to ground, as shown inFigure 7.

Individual MOSFETs can be dis-abled by tying their source to theirsubstrate and leaving the drainopen circuit. In use, the IC’s inputterminal must not be allowed torise above VDD (the supply voltage)or fall below VSS (zero volts).

To use an n-channel MOSFET,the source must be tied to VSS,either directly or via a current-limit-ing resistor. To use a p-channelMOSFET, the source must be tiedto VDD, either directly or via a cur-rent-limiting resistor.

Figure 1.Symbol of thedual-gate or

tetrode MOSFET.

Figure 2. Standard symbols of(a) three-pin and (b) four-pin n-channel enhancement-mode

MOSFETs.

Figure 3. Typical transfer characteristics of4007UB n-channel enhancement-mode MOSFETs.

1 JULY 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

PRINCIPLES AND CIRCUITSPart 3

by Ray MarstonRay Marston looks at practicalMOSFET and CMOS circuits inthis penultimate episode ofthis four-part series.

FET

Field-Effect Transistors

Figure 4. Typical VGS/IDcharacteristics of 4007UB n-channel

enhancement-mode MOSFET.

Figure 5.Functionaldiagram ofthe 4007UBdual CMOS

pair plusinverter. Figure 6. Internal-

protection network (within dotted lines) on

each input of the 4007UB.

LINEAR OPERATION

To fully understand the opera-tion and vagaries of CMOS circuit-ry, it is necessary to understandthe linear characteristics of basicMOSFETs, as shown in the graphof Figure 4.

Note that negligible drain cur-rent flows until the gate rises to a‘threshold’ value of about 1.5 to2.5 volts, but that the drain currentthen increases almost linearly withfurther increases in gate voltage.

Figure 8 shows how to use ann-channel 4007UB MOSFET as alinear inverting amplifier. R1 acts asQ2’s drain load, and R2-Rx bias thegate so that Q2 operates in the lin-ear mode.

The Rx value is selected to givethe desired quiescent drain voltage,and is normally in the 18k to 100krange.

The amplifier can be made togive a very high input impedanceby wiring a 10M isolating resistorbetween the R2-Rx junction andQ2 gate, as shown in Figure 9.

Figure 10 shows how to use

an n-channel MOSFET as a unity-gain non-inverting common-drainamplifier or source follower.

The MOSFET gate is biased athalf-supply volts by the R2-R3divider, and the source terminalautomatically takes up a quiescentvalue that is slightly more than VTHbelow the gate value.

The basic circuit has an inputimpedance equal to the paralleledvalues of R2 and R3 (=50k), butcan be increased to greater than10M by wiring R4 as shown.

Alternatively, the input imped-ance can be raised to several hun-dred megohms by bootstrappingR4 via C1 as shown in Figure 11.

Note from the above descrip-tion that the enhancement-modeMOSFET performs like a conven-tional bipolar transistor, except thatit has an ultra-high input imped-ance and has a substantially largerinput-offset voltage (the base-to-emitter offset of a bipolar is typi-cally 600mV, while the gate-to-source offset voltage of a MOSFETis typically two volts).

Allowing for these differences,the enhancement-mode MOSFET

can thus be used as a directreplacement in many small-signalbipolar transistor circuits.

THE CMOS INVERTER

A major application ofenhancement-mode MOSFETs is inthe basic CMOS inverting stage ofFigure 12(a), in which an n-channeland a p-channel pair of MOSFETsare wired in series but share com-mon input and output terminals.

This basic CMOS circuit is pri-marily meant for use in digitalapplications (as described towardsthe end of Part 1 of this series), inwhich it consumes negligible quies-cent current but can source or sinksubstantial output currents.

Figures 12(b) and 12(c) showthe inverter’s digital truth table andits circuit symbol. Note that Q5and Q6 of the 4007UB IC arefixed-wired in the CMOS inverterconfiguration.

Although intended primarilyfor digital use, the basic CMOSinverter can be used as a linearamplifier by biasing its input to avalue between the logic-0 andlogic-1 levels; under this conditionQ1 and Q2 are both biased partlyon, and the inverter thus passes

significant quiescent current. Figure 13 shows the typical

drain-current (ID) transfer character-istics of the circuit under this condi-tion; ID is zero when the input is atzero or full supply volts, but risesto a maximum value (typically0.5mA at 5V, or 10.5mA at 15V)when the input is at roughly half-supply volts, under which conditionboth MOSFETs of the inverter arebiased equally.

Figure 14 shows the typicalinput-to-output voltage-transfercharacteristics of the simple CMOSinverter at different supply voltagevalues. Note that the output volt-age changes by only a smallamount when the input voltage isshifted around the VDD and 0V lev-els, but that when Vin is biased atroughly half-supply volts, a smallchange of input voltage causes alarge change of output voltage.

Typically, the inverter gives avoltage gain of about 30dB whenused with a 15V supply, or 40dB at 5V.

Figure 15 shows a practical lin-ear CMOS inverting amplifierstage. It is biased by wiring 10Mresistor R1 between the input andoutput terminals, so that the out-put self-biases at approximately

Figure 7. Individual 4007UB complementary pairs can be disabled by connecting them as CMOS

inverters and grounding their inputs.

Figure 8.Method of

biasing n-channel4007UB

MOSFETs foruse as a linear

invertingamplifier (withmedium inputimpedance).

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/JULY 2000 2

Figure 9. High impedance version of the inverting

amplifier.

Figure 10. Methods of biasingn-channel 4007UB MOSFET as

a unity-gain non-invertingamplifier or source follower.

Figure 11. Bootstrapped sourcefollower has ultra-high input

impedance.

Figure 12. Circuit (a), truth table (b),and symbol (c) of the basic CMOS

digital inverter.

Figure 14. Typicalinput-to-output voltage transfer characteristics of

the 4007UB simpleCMOS inverter.

Figure 13. Drain-currenttransfer characteristics

of the simple CMOSinverter.

half-supply volts. Figure 16 shows the typical

voltage gain and frequency charac-teristics of this circuit when operat-ed at three alternative supply railvalues; this graph assumes that theamplifier output is feeding into thehigh impedance of a 10M/15pFoscilloscope probe and, under thiscondition, the circuit has a band-width of 2.5MHz when operatingfrom a 15V supply.

As would be expected fromthe voltage transfer graph ofFigure 14, the distortion character-istics of the CMOS linear amplifierare quite good with small-ampli-tude signals (output amplitudes upto 3V peak-to-peak with a 15V sup-ply), but the distortion thenincreases as the output approachesthe upper and lower supply limits.Unlike a bipolar transistor circuit,the CMOS amplifier does not ‘clip’excessive sinewave signals, but pro-gressively rounds off their peaks.

Figure 17 shows the typicaldrain-current versus supply-voltagecharacteristics of the CMOS linearamplifier. The current typicallyvaries from 0.5mA at 5V, to12.5mA at 15V.

In many applications, the qui-escent supply current of the4007UB CMOS amplifier can beusefully reduced — at the cost ofreduced amplifier bandwidth — bywiring external resistors in serieswith the source terminals of the

two MOSFETs of the CMOS stage,as shown in the ‘micropower’ cir-cuit of Figure 18.

This diagram also lists theeffects that different resistor valueshave on the drain current, voltagegain, and bandwidth of the amplifi-er when operated from a 15V sup-ply and with its output loaded by a10M/15pF oscilloscope probe.

Note that the additional resis-tors of the Figure 18 circuitincrease the output impedance ofthe amplifier (the output imped-ance is roughly equal to the R1-AVproduct), and this impedance andthe external load resistance/capaci-tance has a great effect on theoverall gain and bandwidth of thecircuit.

When using a 10k value forR1, for example, if the load capaci-tance is increased (from 15pF) to50pF, the bandwidth falls to about4kHz, but if the capacitance isreduced to 5pF, the bandwidthincreases to 45kHz. Similarly, if theresistive load is reduced from 10Mto 10k, the voltage gain falls tounity; for significant gain, the loadresistance must be large relative tothe output impedance of theamplifier.

The basic (unbiased) CMOSinverter stage has an input capaci-tance of about 5pF and an inputresistance of near-infinity. Thus, ifthe output of the Figure 18 circuitis fed directly to such a load, itshows a voltage gain of x30 and abandwidth of 3kHz when R1 has avalue of 1M0; it even gives a usefulgain and bandwidth when R1 hasa value of 10M, but consumes aquiescent current of only 0.4µA.

PRACTICAL CMOS

The CMOS linear amplifier caneasily be used in either its standardor micropower forms to make a vari-ety of fixed-gain amplifiers, mixers,integrators, active filters, and oscilla-tors, etc. A selection of such circuitsis shown in Figures 19 to 23.

Figure 19 shows the practicalcircuit of an x10 inverting amplifier.The CMOS stage is biased by feed-back resistor R2, and the voltagegain is set at x10 by the R1/R2ratio. The input impedance of thecircuit is 1M0, and equals the R1value.

Figure 20 shows the above cir-cuit modified for use as an audio‘mixer’ or analog voltage adder.

The circuit has four input terminals,and the voltage gain between eachinput and the output is fixed atunity by the relative values of the1M0 input resistor and the 1M0feedback resistor.

Figure 21 showsthe basic CMOSamplifier used as asimple integrator.

Figure 22 showsthe linear CMOSamplifier used as acrystal oscillator. Theamplifier is linearlybiased via R1 andprovides 180° ofphase shift at thecrystal resonant fre-quency, thus

enabling the circuit to oscillate. Ifthe user wants the crystal to pro-vide a frequency accuracy within0.1% or so, Rx can be replaced bya short and C1-C2 can be omitted.For ultra-high accuracy, the correctvalues of Rx-C1-C2 must be individ-ually determined (the diagramshows the typical range of values).

Finally, Figure 23 shows a‘micropower’ version of the CMOScrystal oscillator. In this case, Rx isactually incorporated in the amplifi-er. If desired, the output of thisoscillator can be fed directly to theinput of an additional CMOSinverter stage, for improved wave-form shape/amplitude. NV

3 JULY 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

Figure 16.Typical AV

and frequency

characteristics of the

linear-modebasic CMOSamplifier.

Figure 15. Method of biasingthe simple CMOS inverter for

linear operation.

Figure 17.Typical ID/VDDcharacteristics

of the linear-mode

CMOS amplifier.

Figure 19. Linear CMOSamplifier wired as x10

inverting amplifier.

Figure 18. Micropower 4007UBCMOS linear amplifier, showing

method of reducing ID, with performance details. Figure 20. Linear CMOS

amplifier wired as unity-gain four-input

audio mixer.

Figure 21.LinearCMOS

amplifierwired as

an integrator.

Figure 22. Linear CMOS amplifier wired as a

crystal oscillator.

Figure 23.Micropower

version of thecrystal

oscillator.

Part 1 of this series explained(among other things) thebasic operating principles ofthose enhancement-modepower-FET devices known

as VFETs or VMOS. This finalepisode of the series takes a deeperlook at these devices and showspractical ways of using them.

A VMOS INTRODUCTION

A VFET can, for most practicalpurposes, be simply regarded as ahigh-power version of a conventionalenhancement-mode MOSFET. Thespecific form of VFET constructionshown in Figure 17 in Part 1 of thisseries was pioneered by Siliconix inthe mid-1970s, and the devicesusing this construction are marketedunder the trade name ‘VMOS powerFETs’ (Vertically-structured Metal-Oxide Silicon power Field-EffectTransistors). This ‘VMOS’ name istraditionally associated with the V-shaped groove formed in the struc-ture of the original (1976) versionsof the device.

Siliconix VMOS power FETs areprobably the best known type of

VFETs. They are available as n-chan-nel devices only, and usually incorpo-rate an integral zener diode whichgives the gate a high degree of pro-tection against accidental damage;Figure 1 shows the standard symbolused to represent such a device, andFigure 2 lists the main characteristicsof five of the most popular membersof the VMOS family; note in particu-lar the very high maximum operat-ing frequencies of these devices.

Other well-known families of‘Vertically-structured’ power MOS-FETS are those produced by Hitachi,Supertex, and Farranti, etc. Some ofthese V-type power MOSFETs areavailable in both n-channel and p-channel versions and are useful invarious high-performance comple-

mentaryaudiopoweramplifier

applications.

THE VN66AF

The best way to get to knowVMOS is to actually ‘play’ with it,and the readily available SiliconixVN66AF is ideal for this purpose. Itis normally housed in a TO202-styleplastic-with-metal-tab package withthe outline and pin connectionsshown in Figure 3.

Figure 4 lists the major staticand dynamic characteristics of theVN66AF. Points to note here arethat the input (gate-to-source) signalmust not exceed the unit’s 15Vzener rating, and that the device hasa typical dynamic input capacitanceof 50pF. This capacitance dictatesthe dynamic input impedance of theVN66AF; the static input impedanceis of the order of a millionmegohms. Figures 5 and 6 show the

VN66AF’s typical output and satura-tion characteristics. Note the follow-ing specific points from thesegraphs.

(1) The device passes negligibledrain current until the gate voltagereaches a threshold value of about1V; the drain current then increasesnon-linearity as the gate is varied upto about 4V, at which point thedrain current value is about 400mA;the device has a square-law transfer

characteristic below 400mA.(2) The device has a

highly linear transfer charac-teristic above 400mA (4V onthe gate) and thus offersgood results as a low-distor-tion class-A power amplifier.

(3) The drain current iscontrolled almost entirely bythe gate voltage and isalmost independent of thedrain voltage so long as thedevice is not saturated. Apoint not shown in the dia-gram is that, for a givenvalue of gate voltage, thedrain current has a negativetemperature coefficient ofabout 0.7% per °C, so thatthe drain current decreasesas temperature rises. Thischaracteristic gives a fairdegree of protection against

1 AUGUST 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

PRINCIPLES AND CIRCUITSPart 4

by Ray Marston

Ray Marston looks at practical VMOS power FET circuits in this final episode ofthis four-part series.

FET

Field-Effect Transistors

Figure 1. Symbol ofSiliconix VMOS power

FET with integral zener diode

gate protection.

Figure 2.Major

parameters offive popular

n-channelSiliconix VMOS

power FETs.

Figure 3.Outline and pin

connections of the

TO202-casedVN66AF

power FET.

Figure 5. Typical output characteristics of the VN66AF.

Figure 4. Major static and dynamic characteristics of the VN66AF.

thermal runaway.(4) When the device is saturat-

ed (switched fully on) the drain-to-source path acts as an almost pureresistance with a value controlled bythe gate voltage. The resistance istypically 2R0 when 10V is on thegate, and 10R when 2V is on thegate. The device’s ‘off’ resistance isin the order of megohms. These fea-tures make the device highly suitablefor use as a low-distortion high-

speed analog power switch.

DIGITAL CIRCUITS

VMOS can be used in a widevariety of digital and analog applica-tions. It is delightfully easy to use indigital switching and amplifyingapplications; Figure 7 shows thebasic connections. The load is wiredbetween the drain and the positivesupply rail, and the digital input sig-nal is fed directly to the gate termi-nal. Switch-off occurs when theinput goes below the gate thresholdvalue (typically about 1.2V). Thedrain ON current is determined bythe peak amplitude of the gate sig-nal, as shown in Figure 5, unless sat-uration occurs. In most digital appli-cations, the ON current should bechosen to ensure saturation.

The static input impedance ofVMOS is virtually infinite, so zerodrive power is needed to maintainthe VN66AF in the ON or OFF state.Drive power is, however, needed toswitch the device from one state tothe other; this power is absorbed incharging or discharging the 50pF

input capacitance of the VN66AF.The rise and fall times of the

output of the Figure 7 circuit are(assuming zero input rise and falltimes) determined by the sourceimpedance of the input signal, bythe input capacitance and forwardtransconductance of the VMOSdevice, and by the value of RL. IfRL is large compared to RS, theVN66AF gives rise and fall times ofroughly 0.11nS per ohm of RSvalue. Thus, a 100R source imped-ance gives a 11nS rise or fall time.

If RL is not large compared to RS,these times may be considerablychanged.

A point to note when drivingthe VN66AF in digital applications isthat its zener forward and reverseratings must never be exceeded.Also, because of the very high fre-quency response of VMOS, thedevice is prone to unwanted oscilla-tions if its circuitry is poorlydesigned. Gate leads should be kept

short, or be pro-tected with a fer-rite bead or asmall resistor inseries with thegate.

VMOS can beinterfaced directlyto the output of aCMOS IC, asshown in Figure8. Output riseand fall times ofabout 60nS can be expected, due tothe limited output currents availablefrom a single CMOS gate, etc. Riseand fall times can be reduced by dri-ving the VMOS from a number ofCMOS gates wired in parallel, or byusing a special high-current driver.

VMOS can be interfaced to theoutput of TTL by using a pull-upresistor on the TTL output, as shownin Figure 9. The 5V TTL output ofthis circuit is sufficient to drive600mA through a single VN66AF.Higher output cur-rents can beobtained either bywiring a level-shifter stagebetween the TTLoutput and theVMOS input, or bywiring a numberof VMOS devicesin parallel, asshown in Figure10.

When using

VMOS in digital switching applica-tions, note that if inductive drainloads such as relays, self-interruptingbells or buzzers, or moving-coilspeakers are used, clamping diodesmust be connected as shown inFigure 11, to damp inductive back-EMFs and thus protect the VMOSdevice against damage.

SOME DIGITAL DESIGNS

Figures 12 to 15 show a few

©T & L Publications, Inc. All rights reserved. Nuts & Volts Magazine/AUGUST 2000 2

Figure 6.Typical

saturationcharacteristics

of theVN66AF.

Figure 7. Basic VMOS digitalswitch or amplifier.

Figure 8. Methods of drivingVMOS from CMOS.

Figure 9. Method of drivingVMOS from TTL.

Figure 10.Method of

boosting theoutput of

Figure 9 by driving threeVN66AFs in

parallel.

Figure 11. Ifinductive loadssuch as relays(a) or bells,buzzers, or

speakers (b) areused in digital

switching circuits,

protectiondiodes must be wired as

shown.

Figure 12.Water-

or touch-activated

powerswitch.

Figure 13.Delayed-turn-offpowerswitch.

Figure 14.Simple

relay-outputtimer circuit.

simple but useful digital applicationsof the VN66AF. The water- or touch-activated power switch of Figure 12could not be simpler: when thetouch contacts and water probes areopen, zero volts are on the gate ofthe VN66AF, so the device passeszero current. When a resistance(zero to 10s of megohms) is placedacross the contacts (by contact withskin resistance) or probes (by watercontact), a substantial gate voltageis developed by potential divideraction and the VN66AF passes ahigh drain current, thus activatingthe bell, buzzer, or relay.

In the manually activateddelayed-turn-off circuit of Figure 13,C1 charges rapidly via R1 whenpush-button switch PB1 is closed,and discharges slowly via R2 whenPB1 is open. The load thus activatesas soon as PB1 is closed, but doesnot deactivate until some 10s of sec-onds after PB1 is released.

In the simple relay-output timercircuit of Figure 14, the VMOSdevice is driven by the output of amanually triggered monostable orone-shot multivibrator designedaround two gates of a 4001B CMOSIC; the relay turns on as soon as PB1is closed, and then turns off auto-matically again some pre-set ‘delaytime’ later. The delay is variable froma few seconds to a few minutes viaRV1.

Finally, Figure 15 shows thepractical circuit of an inexpensivebut very impressive alarm-call gener-ator that produces a ‘dee-dah’sound like that of a British police carsiren. The alarm can be turned onby closing PB1 or be feeding a ‘high’voltage to the R1-R2 junction. Thecircuit uses an 8R0 speaker and gen-erates roughly six watts of outputpower.

DC LAMP CONTROLLERS

Figures 16 to 18 show threesimple but useful DC lamp controllercircuits that can be used to controlthe brilliance of any 12V lamp witha power rating of up to six watts. AVMOS power FET can, for many pur-poses, be regarded as a voltage con-trolled constant-current generator;thus, in Figure 16, the VMOS draincurrent (and thus the lamp bright-ness) is directly controlled by thevariable voltage of RV1’s slider. Thecircuit thus functions as a manuallamp dimmer.

The Figure 17 circuit is a simplemodification of the above design,the action being such that the lampturns on slowly when the switch isclosed as C1 charges up via R3, andturns off slowly when the switch isopened as C1 discharges via R3.

The Figure 18 circuit is an effi-cient ‘digital’ lamp dimmer whichcontrols the lamp brilliance withoutcausing significant power loss acrossthe VMOS device. The two 4011BCMOS gates form an astable multivi-brator with a mark/space ratio thatis fully variable from 10:1 to 1:10 viaRV1; its output is fed to the VN66AFgate, and enables the mean lampbrightness to be varied from virtuallyfully-off to fully-on. In this circuit, theVMOS device is alternately switchedfully on and fully off, so power loss-es are negligible.

LINEAR CIRCUITS

VMOS power FETs can, whensuitably biased, easily be used ineither the common source or com-mon drain (voltage follower) linearmodes. The voltage gain in the com-mon source mode is equal to theproduct of RL and the device’s gM orforward transconductance. In thecase of the VN66AF, this gives avoltage gainof 0.25 perohm of RLvalue, i.e., again of x4with a 16Rload, or x25with a 100Rload. The volt-age gain inthe commondrain mode isslightly lessthan unity.

A VMOS powerFET can be biasedinto the linear com-mon source modeby using the stan-dard enhancement-mode MOSFET bias-ing techniqueshown in Figure 19,in which the R1-R2potential divider is

wired in the drain-to-gate negativefeedback loop and sets the quiescentdrain voltage at roughly half-supplyvalue, so that maximal signal levelswings can be accommodated beforeclipping occurs.

When — in the Figure 19 circuit— R3 has a value of zero ohms, thecircuit exhibits an input impedancethat, because of the AC negativefeedback effects, is roughly equal tothe parallel values of R1 and R2 divid-ed by the circuit’s voltage gain (RL xgM. If R3 has a finite value, the inputimpedance is slightly less than the R3value, unless AC feedback-decouplingcapacitor C2 is fitted in place, inwhich case, the input impedance isslightly greater than the R3 value.

Figure 20 shows how to bias theVN66AF for common drain (voltagefollower) operation. Potential dividerR1-R2 sets the VMOS gate at a quies-cent value slightly greater than half-supply voltage. When the R3 value iszero, the circuit input impedance isequal to the parallel values of R1 andR2. When the R3 value is finite, theinput impedance equals the R3 valueplus the parallel R1-R2 values. Theinput impedance can be raised to avalue many times greater than R3 byadding the C2 ‘bootstrap’ capacitorto the circuit.

Finally, Figure 21 shows a practi-cal example of a VMOS linear appli-cation. The circuit is wired as a class-A power amplifier which, because ofthe excellent linearity of the VN66AF,gives remarkably little distortion forso simple a design. The VN66AFmust be mounted on a goodheatsink in this application. Whenthe design is used with a purelyresistive 8R0 load, the amplifierbandwidth extends up to 10MHz. NV

3 AUGUST 2000/Nuts & Volts Magazine ©T & L Publications, Inc. All rights reserved.

Figure15.

Warble-tone six

wattalarm.

Figure 16. Simple DC lamp dimmer.

Figure 17. Soft-start lamp switch.

Figure 18.High-

efficiency DC lampdimmer.

Figure 19. Biasingtechnique for

linear commonsource operation.

Figure 21.Simple class-Aaudio power

amplifier gives1% THD at 1W.

Figure 20.Biasing

techniques forlinear commondrain (voltage

follower) operation.

FFEETT