Field-Effect Transistors (FETs) 3.4 The p-channel MOSFET ...

Electronic Circuits, Dept. of Elec. Eng., The Chinese University of Hong Kong, Prof. K.-L. Wu Lesson 25&26

Field-Effect Transistors (FETs) 3.4 The p-channel MOSFET & COMS

A p-channel enhancement-type MOSFET is fabricated on an n-type

substrate with p+ regions for the drain and source, and has holes as charge

carriers. The device operates in the same manner as the n-channel MOSFET

except that vGS and vDS are negative and the Vt is negative. iD enters the

source terminal and leaves through the drain terminal.

Complementary MOS or CMOS employs

MOS transistors of both polarities (n-channel

MOS and p-channel MOS). The availability of

COMS makes possible many powerful circuit-

design possibilities.

At the present time CMOS is the most useful

of all the integrated-circuit MOS technologies

for both analog and digital circuits.

While the NMOS transistor is implemented directly in the p-type substrate, the

PMOS transistor is fabricated in a specially created n region , known as an n

well. The two devices are isolated from each other by a thick region of oxide

that functions as an insulator.


Field-Effect Transistors (FETs) 3.5 Current-Voltage Characteristics

Circuit Symbol

The arrowhead on the source terminal points in

the normal direction of current flow. Therefore,

it indicates three things: (1) distinguishing the

source from the drain, (2) indicates the polarity

of the device and (3) designating the terminals.

tGS Vv <

−−′=

>−=+=>

2

2

1)(

,

DSDStGSnD

tDSGSSDGSGD

tGS

vvVvL

Wki

Vvvvvv

Vv

2)(2

1

,

tGSnD

tDSGSSDGSGDtGS

VvL

Wki

VvvvvvVv

−′=

<−=+=>

2

2

1DSnD v

L

Wki ′=Three Regions:

Cutoff region

Triode region

Saturation region


Field-Effect Transistors (FETs) 3.6 Large Signal Equivalent Circuits

tGS Vv <

tDSGSSDGSGD

tGS

Vvvvvv

Vv

>−=+=> ,

tDSGSSDGSGD

tGS

Vvvvvv

Vv

<−=+=> ,

Three Regions:

Cutoff region

Triode region

Saturation region

DSGSGD vvv −=

GSv

DSv

DSGSt vvV −< tGSDS Vvv −<or

vD

vS

vG

vt

Triode

DSGSGD vvv −=

GSvDSv

vD

vS

vGvt

DSGSt vvV −≥ tGSDS Vvv −≥or

Saturation

Vt is a ruler


Field-Effect Transistors (FETs) 3.7 Channel-Length Modulation

Once the MOSFET enter saturation mode the

additional voltage applied to the drain appears as a

voltage drop across the narrow depletion region

between the end of the channel and the drain

region. This voltage accelerates the electrons that

reach the end of the channel and sweeps them

across the depletion region into the drain. Its

effective channel length is reduced because

electrons travel in a less time. The phenomenon is

known as channel-length modulation.

The channel-length modulation can be

analytically accounted for by incorporating a

factor in the i-v equation

Similar to the Early voltage in a BJT, and we

will refer to it here as the Early voltage.

Typically, l=0.005 to 0.03 1/V, and

correspondingly,VA is in the range of 200 to

20 volts.


It should be obvious that channel-length modulation

makes the output resistance in saturation finite.

Defining the output resistance as

results in

where

which can be approximated by

or alternatively

BJTfor tocompared AsC

Ao

I

Vr ≈

DI


Field-Effect Transistors (FETs) 3.8 Practical Considerations

The Body Effect

In IC circuits, the substrate is usually

connected to the most negative power

supply in an NMOS. The resulting

reverse-bias voltage between source and

body (VSB in an n-channel device) will

have an effect on device operation. The

reverse bias voltage will widen the de-

pletion region. As a result, Vt increases.

Temperature Effects

Both Vt and k’ are temperature sensitive.

The magnitude of Vt decrease by about

2mV for every 1oC rise in temperature. This

decrease in | Vt | gives rise to a

corresponding increase in drain current as

temperature is increase. However, because

k’ decreases with temperature and its effect

is a dominant one, the overall observed

effect of a temperature increase is a

decrease in drain current.

Breakdown and Input Protection

As the voltage on the drain is increased,

the pn Junction between drain and sub-

strate suffers avalanche breakdown at

voltages of 50 to 100V

punch-through (about 20 V)

When vGS exceeds about 50 V, gate

oxide is broken down resulting in

permanent damage to the device.


Field-Effect Transistors (FETs) Examples of DC Analysis



We assume saturation-region operation, solve the

problem, and then check the validity.


Field-Effect Transistors (FETs) 3.9 MOSFET as an Amplifier

The DC drain current can be found from

2)(2

1tGSnD VV

L

WkI −′=

where we have neglected channel-length

modulation. The load line will be

DDDDD IRVV −=

To ensure saturation-region operation,

we mush have

tGSD VVV −>

Furthermore, VD has to be sufficiently

greater than to allow for the

required signal swing.tGS VV −

The Signal Current in The Drain Terminal

Next, we apply vgs to gate-to-source voltage

gsGSGS vVv +=

2

2

2

2

1

)()(2

1

)(2

1

gsn

gstGSntGSn

tgsGSnD

vL

Wk

vVVL

WkVV

L

Wk

VvVL

Wki

′+

−′+−′=

−+′=

Calculation of the DC Bias Point

To operate the MOSFET as an amplifier, it must

be biased at a point in the saturation region.


To reduce the nonlinear distortion introduced by

the MOSFET, the input signal should be kept

small so that

gstGSngsn vVVL

Wkv

L

Wk )(2

1 2 −′<<′

resulting in

Small-signal condition

for MOSFET

The MOSFET transconductance

)(2 tGSgs VVv −<<

Therefore,

444 3444 21444 3444 21dD i

gstGSn

I

tGSnD vVVL

WkVV

L

Wki )()(2

1 2 −′+−′=

)( tGSn

gs

d

VvGS

Dm VV

L

Wk

v

i

v

ig

GSGS

−′==∂

∂≡

=gsd vgi m =


Voltage Gain

Since

gsDmDdd vRgRiv −=−=

which gives the voltage gain as

Dm

gs

d Rgv

v−=

The minus sign indicates that

the output signal is 180 degs

out of phase with respect to the

input signal

Field-Effect Transistors (FETs) 3.4 The p-channel MOSFET ...

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