FIELD

EFFECT

TRANSISTOR

by A.AsunthaA.P(O.G)

Department of EIESRM University

FET ( Field Effect Transistor)

Few important advantages of FET over conventional Transistors

1.Unipolar device i. e. operation depends on only one type of charge carriers (h or e)

2. Voltage controlled Device (gate voltage controls drain current)

3. Very high input impedance (≈109-1012 Ω)

4. Source and drain are interchangeable in most Low-frequency applications

5. Low Voltage Low Current Operation is possible (Low-power consumption)

FET ( Field Effect Transistor)

6. Less Noisy as Compared to BJT

7. No minority carrier storage (Turn off is faster)

8. Self limiting device

9. Very small in size, occupies very small space in Ics

10.Low voltage low current operation is possible in MOSFETS

11. Zero temperature drift of out put is possible

Types of Field Effect Transistors (The Classification) 

MOSFET(IGFET)

n-Channel EMOSFET

p-Channel EMOSFET

Enhancement MOSFET

Depletion MOSFET

n-Channel DMOSFET

p-Channel DMOSFET

FETJFET n-Channel JFET

p-Channel JFET

The Junction Field Effect Transistor (JFET)

Gate

Drain

Source

SYMBOLS

n-channel JFET

Gate

Drain

Source

n-channel JFETOffset-gate symbol

Gate

Drain

Source

p-channel JFET

Biasing the JFET

Operation of JFET at Various Gate Bias Potentials 

P P+

-

+

-+

-

N

N

Operation of a  JFET

Gate

Drain

Source

Non‐saturation (Ohmic) Region: 

The drain current is given by ⎥⎥⎥

⎦

⎤

⎢⎢⎢

⎣

⎡−⎟

⎠⎞⎜

⎝⎛ −=

2

2 2

2DS

DSPGSP

DSSDS

VVVV

V

II

⎥⎥⎦

⎤

⎢⎢⎣

⎡⎟⎠⎞⎜

⎝⎛ −=

2

2 PGSP

DSSDS

VVV

II

2

1 and⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛−=

P

GSDSSDS V

VII

Where, IDSS is the short circuit drain current, VP is the pinch off voltage

Output or Drain (VD‐ID) Characteristics of n‐JFET

Saturation (or Pinchoff) Region:

⎟⎠⎞⎜

⎝⎛ −<

PGSDSVVV

⎟⎠⎞⎜

⎝⎛ −≥

PGSDSVVV

Simple Operation and Break down of n‐Channel JFET

Break Down Region

N‐Channel JFET Characteristics and Breakdown

Figure: Typical drain characteristics of an n‐channel JFET.

VD‐ID Characteristics of EMOS FET

Saturation or Pinch off Reg.

2

1 ⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛−=

P

GSDSSDS V

VII

IDSS

Transfer (Mutual) Characteristics of n‐Channel JFET

Biasing Circuits used for JFET

Fixed bias circuit

Self bias circuit

Potential Divider bias circuit 

Circuit symbol for an enhancement‐mode n‐channel MOSFET.

n‐Channel Enhancement MOSFET showing channel length L and channel width W.

For vGS < Vto the pn junction between drain and body is reverse biased and iD=0.

Current‐Voltage Relationship of n‐EMOSFET

Drain characteristics

Variables determining capacitance

p‐Channel FET circuit symbols.  These are the same as the circuit symbols for n‐channel Devices, except for the directions of the arrowheads.

Drain current versus vGS for several types of FETs. iD is referenced into the drain terminal for n‐channel devices and out of the drain for p‐channel devices.

Thank you