FEMTOCLOCKS™ CRYSTAL-TO-LVDS ICS844071 · PDF file3.3V LVDS Output Load AC Test Circuit...

FEMTOCLOCKS CRYSTAL-TO-LVDSCLOCK GENERATOR
ICS844071
IDT / ICS LVDS CLOCK GENERATOR 1 ICS844071AG SEPTEMBER 26, 2007
General Description
The ICS844071 is a Serial ATA (SATA)/Serial Attached SCSI (SAS) Clock Generator and a member of the HiPerClocksTM family of high performance devices from IDT. The ICS844071 uses an 18pF parallel resonant crystal over
the range of 20.833MHz - 28.3MHz. For SATA/SAS applications, a 25MHz crystal is used and either 75MHz or 150MHz may be selected with the FREQ_SEL pin. The ICS844071 has excellent

ICS844071FEMTOCLOCKCRYSTAL-TO-LVDS CLOCK GENERATOR
Table 1. Pin Descriptions
NOTE: Pullup refers to intenal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 VDDA Power Analog supply pin.
2 GND Power Power supply ground.
3,4
XTAL_OUTXTAL_IN
Input Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
5 FREQ_SEL Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
6, 7 nQ, Q Output Differential output pair. LVDS interface levels.
8 VDD Power Core supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
CIN Input Capacitance 4 pF
RPULLUP Input Pullup Resistor 51 k

Absolute Maximum RatingsNOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characterisitcs is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DC Electrical CharacteristicsTable 3A. Power Supply DC Characteristics, VDD = 3.3V 10%, TA = 0C to 70C
Table 3B. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = 0C to 70C
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 10% or 2.5V 5%, TA = 0C to 70C
Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI -0.5V to VDD + 0.5V
Outputs, IOContinous CurrentSurge Current
10mA15mA
Package Thermal Impedance, JA 101.7C/W (0 mps)
Storage Temperature, TSTG -65C to 150C
VDD Core Supply Voltage 2.97 3.3 3.63 V
VDDA Analog Supply Voltage VDD 0.12 3.3 3.63 V
IDD Power Supply Current 135 mA
IDDA Power Supply Current 12 mA
VDD Core Supply Voltage 2.375 2.5 2.625 V
VDDA Analog Supply Voltage VDD 0.12 2.5 2.625 V
IDD Power Supply Current 120 mA
IDDA Power Supply Current 12 mA
VIH Input High VoltageVDD = 3.3V 2 VDD + 0.3 V
VDD = 2.5V 1.7 VDD + 0.3 V
VIL Input Low VoltageVDD = 3.3V -0.3 0.8 V
VDD = 2.5V -0.3 0.7 V
IIH Input High Current VDD = VIN = 3.63V or 2.625V 5 A
IIL Input Low Current VDD = 3.63V or 2.625V, VIN = 0V -150 A

Table 3D. LVDS DC Characteristics, VDD = 3.3V 10%, TA = 0C to 70C
Table 3E. LVDS DC Characteristics, VDD = 2.5V 5%, TA = 0C to 70C
Table 4. Crystal Characteristics
VOD Differential Output Voltage 275 365 455 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 1.125 1.3 1.55 V
VOS VOS Magnitude Change 50 mV
VOD Differential Output Voltage 205 335 465 mV
VOD VOD Magnitude Change 50 mV
VOS Offset Voltage 0.89 1.2 1.48 V
VOS VOS Magnitude Change 50 mV
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 20.833 28.3 MHz
Equivalent Series Resistance (ESR) 50
Shunt Capacitance 7 pF
Drive Level 1 mW

AC Electrical CharacteristicsTable 5A. AC Characteristics, VDD = 3.3V 10%, TA = 0C to 70
NOTE 1: Please refer to Phase Noise Plots.
Table 5B. AC Characteristics, VDD = 2.5V 5%, TA = 0C to 70
NOTE 1: Please refer to Phase Noise Plots.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 62.5 170 MHz
tjit()RMS Phase Jitter, Random; NOTE 1
150MHz, Integration Range: 900kHz 7.5MHz
0.45 ps
0.46 ps
tR / tF Output Rise/Fall Time 20% to 80% 150 400 ps
odc Output Duty Cycle 48 52 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
fOUT Output Frequency 62.5 170 MHz
tjit()RMS Phase Jitter, Random; NOTE 1
0.56 ps
0.60 ps
tR / tF Output Rise/Fall Time 20% to 80% 150 400 ps
odc Output Duty Cycle 48 52 %

Typical Phase Noise at 150MHz (3.3V)
Raw Phase Noise Data
150MHzRMS Phase Jitter (Random)
900kHz to 7.5MHz = 0.45ps (typical)
Noi
se P
ower
dBc
Hz
Offset Frequency (Hz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100 1k 10k 100k 1M 10M 100M

Parameter Measurement Information
3.3V LVDS Output Load AC Test Circuit
RMS Phase Jitter
Output Rise/Fall Time
2.5V LVDS Output Load AC Test Circuit
Output Duty Cycle/Pulse Width/Period
Offset Voltage Setup
-
SCOPEQx
nQx
3.3V10% POWER SUPPLY+ Float GND LVDS
VDDVDDA
Phase Noise Mask
Offset Frequencyf1 f2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noi
se P
ower
Clock Outputs
20%
80% 80%
20%
tR tF
VOD
-
SCOPEQx
nQx
2.5V5% POWER SUPPLY+ Float GND LVDS
VDDVDDA
tPW
tPERIOD
tPW
tPERIOD
odc = x 100%
nQ
Q
out
out
LVDSDC Input
VOS/ VOS
VDD

Parameter Measurement Information, continued
Differential Output Voltage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS44071 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a 0.01F bypass capacitor should be connected to each VDDA pin.
Figure 1. Power Supply Filtering
100
out
out
LVDSDC Input VOD/ VOD
VDD
VDD
VDDA
3.3V or 2.5V
10
10F.01F
.01F

Crystal Input Interface
The ICS844071 has been characterized with 18pF parallelresonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts.
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50.
Figure 3. General Disgram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X118pF Parallel Crystal
C133p
C222p
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50 0.1f
R1
R2
VDD VDD

IDT / ICS LVDS CLOCK GENERATOR 10 ICS844071AG SEPTEMBE

FEMTOCLOCKS™ CRYSTAL-TO-LVDS ICS844071 · PDF file3.3V LVDS Output Load AC Test Circuit...

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