Hoang Lan Nguyen and Uyen Trang Nguyen Presenter: Hoang Lan Nguyen
FDSOI Technology Overview BY Nguyen Sept 25, 2017 Shanghai...
Transcript of FDSOI Technology Overview BY Nguyen Sept 25, 2017 Shanghai...
FD-SOI TechnologyBich-Yen NguyenSoitec
Agenda
1 FD-SOI technology overview
2 Markets, foundries offers
3 FD-SOI material & roadmap
10/10/2017 SOITEC Confidential FD-SOI technology2
4 Summary
10/10/2017 SOITEC Confidential FD-SOI technology3
Challenge of Traditional Planar Bulk Transistor Scaling
• Increased standby power dissipation
• Amplified V th variability ⇒Impact Yield⇒Limit Vdd scaling
Source: IBM, T.C. Chen, ISSCC 2006
new transistor architectures and materials are needed
Continue Moore Law with New Materials & Device Architectures
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2003 2005 2007 2009 2011
90nm
65nm
45 nm
32nm
22nm
Strained Silicon
High-K / Metal Gate
Fully Depleted Devices
Introduction of New DeviceArchitecture
Introduction of New Materials
2012
Hartmann, GSA12
Leakage Power is still a Major Issue Despite the Us e of Hi-K Dielectric
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Source: IBS
Technology node
High-K/Metal Gate Stack
SiON/Poly Gate Stack
Leakage power is still tremendously growing after insertion of the High-K/MG gate stack at 28nm node as demands for more performance and functionality
New Device Architecture: Planar FDSOI or Multi-Gate Transistor
Thin channels (Fully depleted) with multi gates for better gate or short channel (SCE) control
Better gate control ⇒ better transistors scaling
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S D
G
Bulk Si
Buried OXS DG
S DG
Minimum Design Disruption
Max scalability
Conventional Planar Bulk Transistor
Planar Single-or double Gate FDSOI
Multiple-Gate, FinFET or Nanowire Transistor
Bulk SiBuried oxide
FDSOI : Fully Depleted Silicon-on Insulator
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FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage• Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL)
• No History Effect
• Lower SER
No channel doping• Improved VT variability• Improved mismatch (SRAM & analog)• Better analog gain• Reduced process cost
Ultra thin BOX option • Enables Extended body biasing
Channel mobility boost • Scalable down to 10nm
Conventional planar processing
• Lower manufacturing risk• Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
Body BiasingCourtesy of STM
Knobs to control Perf/Power:� Gate bias� Back Bias
FDSOI Device Physics
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Body factor: n = …1.05… in FDSOI; …1.5… in Bulk
ID = µ CoxW
LVG − VTH( ) VD −
1
2n VD
2
IDsat =1
2nµ Cox
W
LVG − VTH( )2( )
S = nkT
qln(10 )
gm
IDVA =
2 µ Cox W L
n IDVA
Linear current:
Saturation current:
Sub-threshold slope:
Gain (strong inversion):
S
G
DS
G
DOxide
SiliconF
s
VgBulk/PDSOI
Cox
Cdepl
Fs1
Vg
Fs2
FDSOI
Coxf
Csi
Coxb
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FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage• Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL)
• No History Effect
• Lower SER
No channel doping• Improved VT variability• Improved mismatch (SRAM & analog)• Better analog gain• Reduced process cost
Ultra thin BOX option • Enables Extended body biasing
Channel mobility boost • Scalable down to 10nm
Conventional planar processing
• Lower manufacturing risk• Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
Body BiasingCourtesy of STM
Knobs to control Perf/Power:� Gate bias� Back Bias
FD-SOI Transistor Level Benefits
Vth and SCE defined by complex and heavilychannel and halo doping techniques
Large Vt mismatch due to random dopant fluctuation => limit Vdd scaling
Strong sensitivity to short channel effect
Large junction capacitance (Cj), GIDL and Didode leakage
Limited well bias capability
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Vertical transistor layout determined by FD-SOI engineered substrate and undoped channel
Significant improved Vt mismatch due to minimize random dopant fluctuation => enableVd scaling down to 0.4V or lower
Excellent SCE
Minimum Cj, GIDL & diode leakages
Extensive back bias capability
Bulk wafer
Source Drain
Gate
Top Si
FD-SOI base wafer
BOXSource Drain
Gate
BOX
BULK FD-SOIThin and excellent
uniformity SOI definedchannel
2nd gate throughultra thin BOX
FD-SOI superior SER enables high reliability requiredapplications
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Neu
tron
-SE
Rin
FT
/Mb
28nm F
D-S
OI
ST65nmBulk
Vendor A45nmBulk
ST45nmBulk
Vendor A28nmBulk
ST28nmBulk
ST28nm
FD-SOI
FD-SOI = 20x SER improvement vs. bulk
“Attractive SEU resistance due to very low charge collection volumes in FD-SOI”
Michael L. Alles Vanderbilt University, S3S conference, 2015
CPU#2
CPU#1Memory
Memory
CPU#1
CPU#2
CPU#2
CPU#1
Memory
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FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage• Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL)
• No History Effect
• Lower SER
No channel doping• Improved VT variability• Improved mismatch (SRAM & analog)• Better analog gain• Reduced process cost
Ultra thin BOX option • Enables Extended body biasing
Channel mobility boost • Scalable down to 10nm
Conventional planar processing
• Lower manufacturing risk• Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
Body BiasingCourtesy of STM
Knobs to control Perf/Power:� Gate bias� Back Bias
13
Lg= 25nm
Tsi= 6nm
Tinv=1.6nm
Ioff= 3nmA/um
Ion-N=570um/um
Ion-P=550uA/um
Vdd=0.9v
FDSOI Structure by IBM - VLSI 2009
Insitu doped SiGe S/D:
⇒Lower S/D resistance
⇒Reduces parasitic capacitance
B - SiGe
BY Nguyen, Soitec Apr. 22, 2011
IBM: 28LP Bulk vs. FDSOI 20LP
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Parameter 28LP Bulk IBM et al. (*) ETSOI IBM et al. (**)
Lg 30nm 22nm
VDD 1V 1V
nFET pFET nFET pFET
Ion @
Ioff=300pA/um
660µA/µm 380µA/µm 760µA/µm 590µA/µm
Ion @
Ioff = 1nA/um
740µA/µm 420µA/µm 920µA/µm 880µA/µm
DIBL 120mV/V 130mV/V 85 mV/V 90 mV/V
AVt 2mV.µm 1.25mV.µm
VDD 1.1V
Ion @
Ioff=1nA/um,
920µA/um 525nA/µm 1100µA/µm 1050µA/µm
(*): IBM Alliance 28LP technology as reported at IEDM’09, F Arnaud et al.(**): ETSOI technology for 22/20LP from IBM Research, as reported at FDSOI workshop dec 2010.
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FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage• Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL)
• No History Effect
• Lower SER improvement
No channel doping• Improved VT variability• Improved mismatch (SRAM & analog)• Better analog gain• Reduced process cost
Ultra thin BOX option • Enables Extended body biasing
Channel mobility boost • Scalable down to 10nm
Conventional planar processing
• Lower manufacturing risk• Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
Body BiasingCourtesy of STM
Knobs to control Perf/Power:� Gate bias� Back Bias
SOI value: part of device integrated by substrate engineering
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Ultra-Thin Top Silicon Layer
Ultra-Thin Buried Oxide
Base Silicon
S DG
FD-SOI transistor
Critical dimension: channel thickness
Optimized SOI wafers provide excellent silicon geometry controlTo make the best of FD technology
Soitec FD-2D wafer
Enables:Critical dimension: Top Si thickness
FDSOI Uniformity: Lowest VT variability
Record and reproducible low AVT of 1.25mV.µm @ Lg=25nm (32/28nm GR)
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Gate Length (nm)
Avt
(mV.
µm)
B.Doris et al., FD‐Workshop at SFO, 2012
Cheng et. Al. IBM IEDM 2009
±2.6A, 2mm EE- 721 pts F5X inspection
Planar Bulk vs FDSOI Vt Variation
50-60% Vt variation improvement by using undoped channel retains with technology scaling
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V t V ariation
0
0.005
0.01
0.015
0.02
0.025
0.03
5 15 25 35 45
L g(n m )
sigm
a V
t (V
)
S O I Retro B ulk Uniform B ulk
FDSOI
FDSOI shows best results in variation (throughout gate length)
Retrograde Bulk
Source: UCB/Soitec , SOI 2009 Conference
Single Port 4Mb SRAM: No Back Bias
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�Improved memory minimum voltage
28nm LP Bulk vs 28nm FDSOI from STMicroelectronics (gate-first HKMG Technology)
C2 - Confidential10/10/2017 SOITEC Confidential FD-SOI technology20
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FD-SOI Transistor Advantages
UTBB FDSOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage• Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL)
• No History Effect
• Lower SER
No channel doping• Improved VT variability• Improved mismatch (SRAM & analog)• Better analog gain• Reduced process cost
Ultra thin BOX option • Enables Extended body biasing
Channel mobility boost • Scalable down to 10nm
Conventional planar processing
• Lower manufacturing risk• Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
Body BiasingCourtesy of STM
Knobs to control Perf/Power:� Gate bias� Back Bias
Electrostatic Scaling Rule of FDSOI down to Lg~10nm
Electrostatic control improved by thinning Tbox and TSi
Superior short-channel control maintained with scaling
Scalability possible down to Lg~10nm, thanks to UTBB FDSOI
10/10/2017 SOITEC Confidential FD-SOI technology22
5nm
Multi-VT Solution for FD -SOI with Dual MetalGate/Ground Plane
Multi Vt requirement for SoC can be achieved for FDSOI device using dual WF metal-gate and ground-plane approach without back-bias
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-0,8
-0,6
-0,4
-0,2
0
0,2
0,4
0,6
0,8
Thr
esho
ld v
olta
ge (V
)
LVT RVT HVT SHVT
GP-N GP-P
GP-P GP-N
GP-PGP-N
GP-NGP-P
nMOS
pMOSGP change metal
change
Logic SRAM
TiN TaAlN/TaN
BOX
TiN
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
TiN
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
Metal change
GP change
LVT
RVT
BOX
TiN
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
TiN
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
Metal change
GP change
LVT
RVT
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiN
TiN
HVT
SHVT
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiN
TiN
BOX
nMOS
BOX
TaAlN
pMOS
N-GP P-GP
BOX
nMOS
BOX
TaAlN
pMOS
P-GP N-GP
TiN
TiN
HVT
SHVT
O. Webber et al., IEDM’10
Multi-VT Modulation for FDSOI with Back Bias
VT tuning with BOX = 10nm and VBB , GP
N and PMOS: VT modulation of ≤200mV for 10nm BOX
No degradation of Ion-Ioff trade-off with back-bias up to +/-2V
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Leti- VLSI 2010 Q. Liu, ST, VLSI 2010
Body-Bias enabling wider dynamic operating rangeNXP example (BB level 0)
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Source: NXP presentation at SOI Consortium, Santa Clara, April 2017
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FD-SOI with Back Bias enables 0.4v Operation for IoT
VBB
Q. Liu, et. al. VLSI Symposium 2011 R. Tsuchiya, et. al. IEDM 2007
FDSOI 0.08um2 SRAM (80nm CPP)
• SRAM remains functional down to V DD=0.4V
• Clear SNM modulation from back bias
• Both Stability and Vt variation improved with RBB
• Lower Vdd for logic operation with software controll ed Back-bias enables SoC Product with tremendous power saving (>7 0%)
FDSOI for RF & AnalogBeyond 28nm Bulk
10/10/2017 SOITEC Confidential FD-SOI technology27
Gain @ Lmin Gain @ Id Variability (Undoped Channel) Fmax > 300Ghz
FDSOI
Bulk CMOS
Vgs
FDSOI key analog differentiationsHigher Analog Performance vs BulkLower variability than bulkLower Capacitance enabling higher frequencyLower Phase noiseRemaining planar
On the fly Vt tuningNew circuit topology enabler : double gate transistorAnalog : VT, Fmax, Gm, Ioff, ….
Ideal for next generations transceivers and SoC
22nm FDX Platform Features: ULL, ULP & RF
10/10/2017 SOITEC Confidential FD-SOI technology28
Renesas Electronics also Achieves Industry's Lowest Standby Power of 13.7 nW/Mbit and 1.84 ns High-Speed Readout with New Emb edded SRAM that Implements New Circuit Technology with 65nm FD-SOI
10/10/2017 SOITEC Confidential FD-SOI technology29
22nm FDX Platform Features: ULL, ULP & RF
30C2 - Confidential10/10/2017 SOITEC Confidential FD-SOI technology
10/10/2017 SOITEC Confidential FD-SOI technology31
FD-SOI Transistor Advantages
UTBB FDOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage• Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL)
• No History Effect
• Lower SER
No channel doping• Improved VT variability• Improved mismatch (SRAM & analog)• Better analog gain• Reduced process cost
Ultra thin BOX option • Enables Extended body biasing
Channel mobility boost • Scalable down to 10nm
Conventional planar processing
• Lower manufacturing risk• Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
Body BiasingCourtesy of STM
Knobs to control Perf/Power:� Gate bias� Back Bias
10/10/2017 SOITEC Confidential FD-SOI technology32
FDSOI Scalability: Boosters Roadmap
2nd gen RSD + cSiGe
28nm FDSOI
22/14nm FDSOI
22/14nm FDSOI
12/10nm FDSOI
12/10nm FDSOI
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FDSOI Performance Booster: local Ge Condensation for PMOS
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S. Nakaharai et al, MIRAI, APL, V83, no17, 2003
• Local Ge condensation with various Ge
content/strain level has been used to boost
hole mobility or P-type MOSFET
performance
( )
2 /( )eff G T
DSAT ox sateff sat G T
V VI WC v
v L V V
µµ
−=
+ −Ion
Strain SiGeOI by Ge Condensation of SOI
Source: S. Nakaharai, Appl. Phys. Lett. 83, 3516 (2003);
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Performance of PMOS using cSiGe channel formed by Local Ge Condensation
• NMOS does not degrade with local Ge condensation process
• Compressive SiGe channel PMOS improved by 35% over unstrained Si
FDSOI
Source: IBM, Cheng et. al, IEDM-2012
35%
ARM says 22nm FD -SOI with proper BB optimizationoutperforms FinFET at pure performance standpoint
Selective back-gate biasing is developed by ARM
Using proper BB on 22nm FD-SOI can achieve higher performance/power tradeoff as those of 14 FinFETtechnology for ARM HP CPU (Cortex-A72)
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14FinFET 22FD-SOITota
l Pow
er
PerformanceSource : ARM, SOI Consortium San Jose 2016
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FDSOI Performance Booster: Tension Strain Si Channel for NMOS
Strained Si on Insulator (sSOI) for boosting NMOS Performance
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Source: IBM, Khakifirooz et. al, VLSI-2012
27%
75%
10nm FD-SOI and DC Performance Comparison
10/10/2017 SOITEC Confidential FD-SOI technology39
Source: Q. Liu et. al, IEDM 2014
10/10/2017 SOITEC Confidential FD-SOI technology40
FD-SOI Transistor Advantages
UTBB FDOI Transistor Advantages
Total dielectric isolation • Lower S/D capacitances • Lower S/D leakage• Latch-up immunity
Ultra thin Body • Excellent SCE (SS, DIBL)
• No History Effect
• Lower SER
No channel doping• Improved VT variability• Improved mismatch (SRAM & analog)• Better analog gain• Reduced process cost
Ultra thin BOX option • Enables Extended body biasing
Channel mobility boost • Scalable down to 10nm
Conventional planar processing
• Lower manufacturing risk• Equivalent bulk design
UTBB: Ultra-Thin Body and BOX
Body BiasingCourtesy of STM
Knobs to control Perf/Power:� Gate bias� Back Bias
Simplicity of the FDSOI Integration
10/10/2017 SOITEC Confidential FD-SOI technology41
Shallow Trench isolationSiBOXSi substrate
Gate Process
SEG of SD region
Spacer and NiSi for SD contact
1- Isolation:‒ Shallow Trench Isolation‒ Define the bulk/SOI area (hybrid option)‒ Ground plane implant
2- Gate Stack:‒ Sac Ox and High-K deposition‒ Metal gate & poly Si deposition‒ Gate stack patterning, etch, HfO2 removal
3- Source/Drain formation‒ Selective epitaxy growth (insitu doped or
undoped with extension & S/D implant‒ Salicidation
4- MOL and BEOL‒ ILD/Via/Metal Interconnect Backend
28nm FDSOI Process Migration
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Process steps
Global Foundries 22nm FD -SOI Process Flow
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38 Masks and 8 metal Levels
NMOS
NMOS
NMOS
PMOS
PMOS
PMOS
Ground Plane Ground Plane
N+ Si Epi
Ground Plane
Ground Plane Ground Plane
65/45/28nm FDSOI
22/14nm FDSOI
10nm FDSOI
B-SiGe B-SiGeP-Si(C) P-Si(C)
P-Si(C)P-Si(C) B-SiGe B-SiGe
• UTBB substrate• Elevated Si EPI S/D
• UTBB substrate• SiGe Channel for PMOS• Insitu doped SiGe and SiC
EPI for S/D
• sSOI substrate• SiGe Channel for PMOS• Insitu doped SiGe & Si(C)
EPI for S/D
N+ Si Epi P+ Si Epi P+ Si Epi
10/10/2017
FD-SOI: FinFET performance at lower manufacturing cost
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Agenda
1 FD-SOI technology overview
2 Markets, foundries offers
3 FD-SOI material & roadmap
10/10/2017 SOITEC Confidential FD-SOI technology46
4 Summary
Perfect fit for wireless & ULP / ULL IoT clients in need of :
FD-SOI brings many differentiation in Mobile, IoT, 5G & Automotive markets
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IoTMobility
Automotive5G & Radars
Best Power/Perf/Cost solution for
Ideal technology for Unique advantages in low power/ high reliability (SER)
Low-mid tier Baseband + AP
4G transceiver integration
5G mmWave design
On-demand processing performance
Integrated RF
Embedded memory
5G mmWave low power single chip solution with integrated PA
<6GHz applications w/ 35-50% die shrink (LTE, Wifi,…)
ADAS (<5W) for autonomous driving
Radar - Mid to long range single chip
Infotainment
MCU for Body Electronics
2021 (est.): 1-3M wafers/y.FD-SOI global wafers estimate: Source : Soitec estimates
The FD-SOI Revolution has started in C onsumer & Automobile
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Consumer: a game changer technology for better battery life
Automotive : best power efficiency allowing simpler integration and enhanced reliability
FD-SOI technology unlocks battery-powered device potential
FD-SOI - reference technology for ADAS level 3 applications
Next generation e-Cockpit solution with full management of car infotainment
Level 3 autonomous driving
2.5Tops @ only 3W
Advanced features -object recognition through neural network
FD-SOI based Sony GPS to cut standard GPS power consumption by 5 to 10x
Now, more than a day autonomy with GPS ON
i.MX based reference platform developed by NXP for Amazon’s Alexa
FD-SOI is a key enabler of the i.MX reference platform for always-on applications
FD-SOI: Strong traction from foundries
10/10/2017 SOITEC Confidential FD-SOI technology
Samsung GlobalFoundries
49
28nm FD-SOI cheaper cost per gate & design cost
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FD-SOI – A mainstream solution with many choices
Performance & density at any cost - for Servers, networking &
High-end Mobile
Bulk90/65/45
nm
HK, PolySi28nm
FinFET 16/14nm
FinFET 10 nm
FinFET 7nm
5110/10/2017 SOITEC Confidential FD-SOI technology
R.Martino - Shanghai FD SOI Forum – Sept 2015
FD-SOI – A mainstream solution with many choices
Cost-effective & performance for Low-power applications
Performance & density at any cost - for Servers, networking &
High-end Mobile
Bulk90/65/45
nm
HK, PolySi28nm
FD-SOI 65 nm
FD-SOI 28 nm
FD-SOI 12 nm
eMRAM
FD-SOI 22 nm
FinFET 16/14nm
FinFET 10 nm
FinFET 7nm
FD-SOI 18 nm
eMRAM
eMRAM
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Agenda
1 FD-SOI technology overview
2 Markets, foundries offers & ecosystems
3 FD-SOI material & roadmap
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4 Summary
FD-SOI Substrate Maturity
Long collaborative history on FD-SOI
FD-SOI substrate reached production maturity since 2013
Proven manufacturing capability on more than 70000 wafers+/-5Å top silicon uniformity specification met with CpK>1: all wafers, all points
Differential Reflective Metrology defined to predict / protect variability on device
Defectivity in line with foundry requirements
>95% device wafer yield demonstrated at foundry
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Full wafer thickness deviation (Å)(41 points per wafer, ~15k wafers)
Top silicon thickness
Donorsubstrate
2005
Smart Cut & device experts
2005
Industrialisation
2010
Advanced R&D2008
ResearchInstitute2005
28FD foundry offer2014
22FD foundry offer2015
Thickness control>70 000 Wafers @ ± 1 Atomic Layer !
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Silicon thickness uniformity is guaranteed to within just a few atomic layers:
Target
+5Å
-5Å
±5Å
Soitec FD-SOI wafer
SOITEC Confidential FD-SOI technology
±1,4cm
Standard Smart-Cut™ process flow and FD -SOI specifics enabling ultra thin SOI film and BOX
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High quality top wafer for
thin SOI film compatibility
Adapted to thin BOX
Adapted to thin SOI film
Adapted to thin BOX
Adapted to thin SOI film
SOITEC Confidential FD-SOI technology
Efficient collaboration with equipment makersExample of FD -SOI roughness management
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〉 Tool customized with new deposit management for SOI manufacturing
〉 New tool redesign ongoing for enhanced flow managment to achieve ultimate FD-SOI roughness & uniformity
〉 Collaboration on Differential Reflective Metrology development
〉 Full map thickness measurement – a critical parameter for FD-SOI
F.De Crecy – CEA/LETISimulation of silicon smoothing under high temp anneal HSEB Baldur tool
DRM 6σ (A)< 3.0
< 4.0< 4.5< 5.0< 5.5< 6.0< 6.5< 7.0> 7.0
< 3.5
FD-SOI Local Thickness VariabilityWithin Wafer Uniformity
Enhanced smoothing with Kokusai batch anneal technology
Unique chip scale thickness measurement developed with HSEB
A multi-nodes FD -SOI Product Roadmap
10/10/2017 SOITEC Confidential FD-SOI technology
Top Si unifTop Si unif
Box thick.Box thick.
Top Si Mob.Top Si Mob.
Top Si thick.Top Si thick.
Industrial status
FD-SOIsubstrate
Target node 28FD
Prod.
25nm
± 0.5 nm
12 nm
Siunstrained
22FD
Prod.
20nm
± 0.5 nm
12 nm
Siunstrained
Beyond 12FD
Pending device
R&D
≤ 20nm
tbd
Si / SiGeStrained / relaxed
15 – 20nm
Siunstrained
Dev.
± 0.4 nm
12FD
12 nm
65FD
Prod.
15nm
± 1.0 nm
30 nm
Siunstrained
58
SOITEC FD-SOI wafer capacity
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UP TO 1.5MWAFERS/YEAR CAPACITY WITHIN EXISTING FACTORY
Soitec Capacity only.Not taking into account SOITEC licensees
Detailed Capex and Operational plans are defined for Bernin 2 (up to 500kw) and Singapore (up to 1Mw)
Will be triggered in coordination with foundries demand
Phase 2: Singapore fab will get full qualification at customer level in first half 2019
Phase 3 (additional >1,5Mw) is in planning stage – different options (locations, partners) are being considered
estimated time to qualified fab: 24 months
timing will be coordinated with foundries
100 Kw/y500 Kw/y
1.5 Mw/y
3Mw/y
Today +6 months +18 months Next Phase*
Phase 1 Phase 2 Phase 3
FD-SOI: ecosystem getting stronger
SAMSUNG
Extension of current 28 nm FD-SOI platform by incorporating RF and embedded MRAM
18 nm FD-SOI process technology targeted for risk production in 2019
GLOBALFOUNDRIES
GLOBALFOUNDRIES and the Chengdu municipality to invest 100M$ to build a world-class FD-SOI ecosystem including multiple design centers and accelerate adoption of 22 FD-SOI (FDX) in China
Increasing 22 FD-SOI capacity: +40% est. in Germany by 2020New 300 mm fab. in China with expected volume production in 2019
Focus on 12 FD-SOI development
A rapidly growing FD-SOI ecosystem
Latest Announcements
Research Technology &
IP
Substrates
Tools & EDA IP & Design Services
Fabless & OEMs
Consumer Products
& Licensees
+60 fabless under development
Foundries&IDM
CEA - LETI
Presented path to 10nm FD-SOI
IP/ EDA Vendors
Active position in promoting FD-SOI
6010/10/2017 SOITEC Confidential FD-SOI technology
Summary
FD-SOI enables far better scalability and transistor characteristics than planar bulk � higher performance
� lower power
� better reliability
� wider operating range through its back-bias capability
FD-SOI is a simpler and cost-efficient process/design than other fully depleted approaches
FD-SOI allows very strong differentiation in low power & 5G markets
FD-SOI roadmap down to 12nm is already definded by foundry
The value of FD-SOI is now recognized by fabless and is about to be introduced in high volume consumer products
FD-SOI is enabled by SOITEC engineered substrates
SOITEC has the capacitity to support multi-million wafers/year supply chain
FD-SOI ecosystem is getting ready
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Even the simplest thing can be beautiul!
10/10/2017
Even the simplest approach can be powerful!
THANK YOU
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