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![Page 1: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/1.jpg)
FAMUFAMU--FSUFSU College of EngineeringCollege of Engineering
EEL 3705 / 3705LEEL 3705 / 3705LDigital Logic DesignDigital Logic Design
Fall 2006Instructor: Dr. Michael Frank
Module #12: Combinational Logic Cost & Timing Analysis
(Thanks to Dr. Perry for some slides)
![Page 2: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/2.jpg)
FAMU-FSU College of Engineering
Combinational Logic – Cost AnalysisCombinational Logic – Cost Analysis In practice, accurately calculating the manufacturing
cost of a given design may be very complicated… Some factors:
General type of logic technology used: Custom VLSI vs. ASIC vs. FPGA vs. old-school TTL/MSI
Many precise details of the specific technology used Nonlinear effects of wiring cost
Average wire length tends to grow as # of devices increases Nonlinear effects of die area on IC yield
May be ameliorated by fault-tolerant architectural techniques
Still, a simple, first-order, back-of-the-envelope estimate of circuit cost can be obtained by modeling cost as linear in the number of gates or transistors used.
![Page 3: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/3.jpg)
FAMU-FSU College of Engineering
Number of Transistors per Logic GateNumber of Transistors per Logic Gate
Example for a typical, simple static CMOS VLSI technology: NOT gate (inverter) 2 transistors Buffer 4 trans. NAND/NOR: 4 T AND/OR: 6 T XOR/XNOR: 8-10 T
8 if complement of input signal is already available
![Page 4: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/4.jpg)
FAMU-FSU College of Engineering
Cost/Transistor Figures TodayCost/Transistor Figures Today Typical ballpark figures for a leading-edge,
high-performance CPU with plenty of cache today (2007): Cost per IC: ~$500 Number of transistors: ~1 billion
Thus, the average cost per transistor is: $500 / 109 T = $10−7/ T = 10−5 ¢/T = .00001 ¢/T
Note this includes an amortized share of the cost due to wiring, yield considerations, etc.
![Page 5: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/5.jpg)
FAMU-FSU College of Engineering
Cost Estimation ExampleCost Estimation Example Estimate the cost of a simple 64-bit ripple-
carry adder in a modern VLSI process. Half-adder = AND+XOR = 6+10 T = 16 T Full adder = 2 HAs + OR = 2×16 + 6 = 38 T 64 Full adders = 64 × 38T = 2,432 Ts 2,432 T × .00001¢/T = .02432 ¢
Thus, a simple 64-bit adder costs about two one-hundredths of a cent to manufacture This may also be further optimized
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FAMU-FSU College of Engineering
Cost-performance AnalysisCost-performance Analysis An important figure of merit for many digital
systems is their cost-performance, meaning performance (operations performed per unit of time) per unit of manufacturing cost A.k.a. cost-efficiency, hardware efficiency Can be measured in e.g. ops/sec/$
Example: Suppose the 64-bit adder of the previous slide can be clocked at 1 GHz. What is its cost-performance, in terms of 64-bit add operations? (109 ops / sec /adder)/(0.024 ¢/adder)×(100¢/$)
= 4.2 × 1012 ops/sec/$
![Page 7: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/7.jpg)
FAMU-FSU College of Engineering
Power-performance AnalysisPower-performance Analysis As power consumption becomes a dominant limiting factor
on performance, power-performance (performance per unit power dissipated) becomes increasingly important. A.k.a. (computational) energy efficiency Measured in ops/sec/Watt, or ops/Joule
Example: Suppose each logic gate in the previous example consumes 1 fJ = 6,241 eV on each clock cycle. What then is its power-performance for 64-bit adds? Number of logic gates in adder design: 5×64 = 320 Energy dissipated per 64-bit add operation:
320 × 6,241 eV = 2 MeV = 3.2 × 10−13 J Power-performance:
1/(3.2×10−13 J) = 1.95 × 1013 ops/Joule = 3.125×1012 ops/sec/Watt
![Page 8: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/8.jpg)
FAMU-FSU College of Engineering
Cost vs. Power ExampleCost vs. Power Example Suppose that, using the technology of the previous
examples, I wish to design a massively parallel 3D graphics processing unit (GPU) for a handheld videogame unit. In this GPU, most of the cost and power budget goes to 64-bit add ops. But it must cost no more than $50, and dissipate no more than 10 Watts of power. Which is the major limiting factor on performance: Hardware cost, or power? Cost-limited performance on 64-bit add operations:
(4.2×1012 ops/s/$)×($50) = 210 T adds/sec Power-limited performance on 64-bit add operations :
(3.125×1012 ops/s/W)×(10W) = 31.25 T adds/sec Power is by far the dominant limiting factor!
![Page 9: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/9.jpg)
Timing Analysis for Combinational Logic
![Page 10: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/10.jpg)
Delay TimeDef: Time required for output signal Y to change due to change in input signal X
Up to now, we have assumed this delay time has been 0 seconds.
F(x)X Y
t=0 t=0
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Delay Time
In a “real” circuit, it will take tp seconds for Y to change due to X
F(x)X Y
t=0 t=tp
tp is known as the propagation delay time
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Timing Diagram
We use a timing diagram to graphically represent this delay
X
Y
time,s
time,s
t=0
t=tp
0
1
0
1
Horizontal axis = time axisVertical axis = Logical level axis (Logic One or Logic Zero)
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Timing Diagram
We see a change in X at t=0 causes a change in Y at t=tp
Horizontal axis = time axisVertical axis = Logical level axis (Logic One or Logic Zero)
X
Y
time,s
time,s
t=0
t=tp
0
1
0
1
t=T
t=T+tp
![Page 14: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/14.jpg)
Timing Diagram
We also see a change in X at t=T causes another change in Y at t=T+tp
We see that logic circuit F causes a delay of tp seconds in the signal
X
Y
time,s
time,s
t=0
t=tp
0
1
0
1
t=T
t=T+tp
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Simple Example – Not Gate
X Y
Let tp=2 ns Where ns = nanosecond = 1x10-9 seconds
X
Y
time,ns
time,ns
0
2
2ns
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Simple Example – 2 Not GatesLet tp=2 ns
X
Z
4
Y0 2 6 8 t,ns
X Z Y
Total Delay = 2ns + 2ns = 4ns
2ns
2ns
4ns
![Page 17: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/17.jpg)
Simple Example – 2 Not GatesNotes:
Time axis is shared among signals Logic levels (1 or 0) are implied, not shown
X
Z
4
Y0 2 6 8 t,ns
![Page 18: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/18.jpg)
Simple Example – 2 Not GatesSometimes dashed vertical lines are added to aid reading diagram
X
Z
4
Y0 2 6 8 t,ns
2ns 2ns 2ns 2ns 2ns
![Page 19: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/19.jpg)
Where does this delay come from?
Circuit Delay
![Page 20: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/20.jpg)
Circuit Delay
All electrical circuits have intrinsic resistance (R) and capacitance (C).
C R
Let’s analyze a simple RC circuit
![Page 21: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/21.jpg)
Circuit Delay – Simple RC Circuit
R
CVin(t)
Vout(t)
1 expout dd
tV t V
RC
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7
Vout
Vin
0.69 0.5
2.3 0.9
4.6 0.99
x out x dd
x out x dd
x out x dd
t V t V
t V t V
t V t V
Note:
timeconstantRC
![Page 22: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/22.jpg)
Circuit Delay – ExampleR
CVin(t)
Vout(t)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7
Vout
Vin
Let R=1ohm, C=1F, so that RC=1 second
Time Delay is 0.7s or 700 ms for 0.5VddTime Delay is 2.3s for 0.9VddTime Delay is 4.6s for 0.99 Vdd
![Page 23: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/23.jpg)
How do we relate this to logic diagrams?
![Page 24: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/24.jpg)
Def: tplhtplh = low-to-high propagation delay time This is the time required for the output to rise from 0V to ½ VDD
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7
tplh
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Def: tphlTphl = high-to-low propagation delay time This is the time required for the output to fall from Vdd to ½ VDD
tphl
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 1 2 3 4 5 6 7
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Def: tp (propagation delay time)
Let’s define tp = propagation delay time as
1
2p plh phlt t
This will be the “average” delay through the circuit
![Page 27: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/27.jpg)
Gate Delay – Simple RC Model
R
Vin(t)
Vout(t)
C
Vout(t)Vin(t)
Ideal gate with RC network Equivalent model withGate delay of tp_not
Ideal gate with tp=0 delayRC network
Tp=tp_not
![Page 28: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/28.jpg)
Gate Delay - Example
X
0 25ns
0 5ns 30ns
Y
X Y
5ns
tp_not
We indicate tp on the gate
![Page 29: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/29.jpg)
Combinational Logic Delay
A
B
CD
Y
5ns
5ns
5ns
5ns
5ns
Shortest delay
Longest delay
Longest delay = 20nsShortest delay = 5ns
This circuit has multiple delay pathsA-Y = 5ns+5ns+5ns=15nsB-Y = 5ns+5ns+5ns+5ns=20nsC-Y = 5ns+5ns+5ns=15nsD-Y = 5ns
, , ,F a b c d D AB B C
![Page 30: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/30.jpg)
Combinational Logic Delay
A
B
CD
Y
5ns
5ns
5ns
5ns
5ns
Shortest delay
Longest delay
Longest delay = 20ns
We’ll use the longest delay to representthe logic function F.
Let’s call it Tcl for time, combinational logic
, , ,F a b c d D AB B C
![Page 31: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/31.jpg)
Combinational Logic (CL) Cloud Model
A
B
C
DE
Y
5ns5ns
5ns
5ns
5ns
F
tcl
X Y
Tcl=20ns
Tcl=20ns
, , ,F a b c d D AB B C
![Page 32: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/32.jpg)
Logic Simulators
Used to simulate the output response of a logic circuit.
![Page 33: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/33.jpg)
Logic Simulations
Three primary types Circuit simulator (e.g. PSPICE)
“Exact” delay for each gate Most accurate timing analysis Very slow compared to other types
Functional Simulation (e.g. Quartus ) Assumes one unit delay for each gate Very fast compared to other types Most inaccurate timing analysis
Timing Simulation (e.g. Quartus) Assumes “average” tp delay for each gate Not the fastest or slowest timing analysis Provides “pretty good” timing analysis
![Page 34: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/34.jpg)
TPS Quizzes
![Page 35: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/35.jpg)
Timing Quiz 1
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Calculate all delay paths through the circuit shown below
A
B
CD
Y
2ns
5ns
8ns
5ns
10ns
What is the shortest and longest delay?
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Solution: Calculate all delay paths through the circuit shown below
A
B
CD
Y
2ns
5ns
8ns
5ns
10ns
This circuit has multiple delay pathsA-Y = 5ns+5ns+10ns=20nsB-Y = 2ns+5ns+5ns+10ns=22nsB-Y = 8ns+5ns+10ns=23nsC-Y = 8ns+5ns+10ns=23nsD-Y = 10ns
Shortest path=10nsLongest path=23ns
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Timing Quiz 2
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Given the circuit below, find(a) Expression for the logic function(b) Longest delay in original circuit
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Solution: Given the circuit below, find(a) Original logic function(b) Longest delay in original circuit
Y AC B C C Longest Delay = 7ns+7ns = 14ns
![Page 41: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/41.jpg)
Timing Quiz 3
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Given the circuit below,(a) Using Boolean Algebra, minimize the logic function(b) Longest delay in minimized circuit
Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns
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Solution: Given the circuit below, find(a) Minimized logic function(b) Longest delay in minimized circuit
Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns
You can show
Y AC
![Page 44: FAMU-FSU College of Engineering EEL 3705 / 3705L Digital Logic Design Fall 2006 Instructor: Dr. Michael Frank Module #12: Combinational Logic Cost & Timing.](https://reader030.fdocuments.net/reader030/viewer/2022032722/56649f505503460f94c7344c/html5/thumbnails/44.jpg)
Solution: Given the circuit below, find(a) Minimized logic function(b) Longest delay in minimized circuit
Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns
Y AC
Longest delay is 7ns
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Y AC
Solution Expanded
Y AC B C C
( )
Y AC B C C AC B C C
AC C A C C AC
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Given the circuit below,(a) Using a Truth Table and a K-map, minimize the logic function
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Solution
Do yourself!