Fall 2011

cave3 News NSF-CAVE3 Electronics Research Center

cave.auburn.edu; tel: (334) 844-3424

INSIDE

1 Message from Director

2 CAVE3 Review

3-8 Research Highlights

9-10 Announcements

11 Selected Publications

SAMUEL GINN COLLEGE OF ENGINEERING

Mission Statement

CAVE is dedicated to working with industry in developing and implementing new technologies for

the packaging and manufacturing of electronics, with special emphasis on the cost, harsh environment,

and reliability requirements of the automotive, aerospace, military, computing, portable and other in-

dustries.

Message from Director

Newer tin-silver-copper lead-

free systems exhibit signifi-cantly high propensity for

whisker formation. While tin

whisker growth is believed to

be largely mechanical, there is

currently no general agree-

ment on the mechanism gov-

erning the growth of tin

whiskers. Tin whiskers have

been reported in variety of

applications including aero-

space systems and automo-biles retrieved after a few years of use. The whiskers

form in various locations including connectors and

components. While, the potential impact of the

whiskers on equipment operation may vary with the

location of whiskers and with system design – it is

clear that the susceptibility to whisker formation is

higher in the newer leadfree interconnects and plat-

ings than eutectic tin-lead systems used in the past.

Previous solutions for mitigation of tin whiskers in-

cluding conformal coats and addition of dopants have

met with limited to no-success. Multiple material

and processing variables interact to create whiskers which makes it difficult to produce effective mitiga-

tion schemes and develop a comprehensive picture of

whisker growth. CAVE3 has been working on the

underlying physics related to the factors producing tin

whiskers. Factors studied include the effect of sur-

face oxides, surface roughness, and stress state on the

propensity for growth of tin-whiskers.

Design life horizon for several consumer prod-

ucts such as smartphones and laptops is generally

perceived to be in the 1-5 year range. Army, Navy

and Aerospace electronic systems share some com-mon needs of longer design life which are quite dif-

ferent from consumer grade automotive systems.

Sustainment of the long life military electronic sys-

tems also have unique reliability needs with signifi-

cantly higher stakes. The military community has

come together to form the leadfree risk mitigation consortium (PERM). CAVE3 has been a regular par-

ticipant in the consortium. These harsh environment

applications often need higher damage tolerance than

consumer grade products which are expected to oper-

ate in office benign environments. CAVE3 has

shown that the tin-silver-copper based leadfree alloys

widely being used as replacements for the eutectic tin

-lead alloys are susceptible to degradation in the elas-

tic modulus and ultimate tensile strength. The materi-

al properties of the commonly used leadfree alloys are

continuously evolving under exposure to high ambi-

ent temperature. In addition to prolonged design life, these harsh

environment applications require prolonged exposure

to high temperature, vibration exposure at high tem-

perature, and high-g survivability. CAVE3 research-

ers recently tested the advanced micro-coil intercon-

nect for NASA’s space electronics. The electronic

modules have been tested at accelerations up to

50,000g. Transient dynamic motion of the modules

has been studied using high-speed cameras at 60,000

frames per sec. Prognostication of leading indicators

has been used to quantify the damage tolerance of interconnects. Finite element models have been de-

veloped to model the survivability of the electronic

assemblies under the high-g loads.

Our Spring 2012 Review is March 7-8, 2012.

We have a number of exciting results in the research

thrust areas. I look forward to seeing you at the re-

view.

Pradeep Lall

T. Walter Professor and Director

CAVE3 Consortium Spring Technical Review Meet-

ing

The Center for Advanced Vehicle and Extreme Environment Elec-

tronics (CAVE3) will hold its Spring Technical Review and Project

Planning Meeting on March 7-8, 2012 in Auburn University Hotel

& Conference Center. All current members of the Consortium are

invited to attend. The agenda for this event is available at

cave.auburn.edu under CAVE3 Reviews. The following projects

will be presented at the meeting:

Acceleration Factors and Life Prediction Models for on-chip

and off-chip Failure Mechanisms

Advanced Interconnect Systems and 3D-Packaging Architec-

tures in Harsh Environments

Prognostic Health Monitoring Methodologies for Damage Esti-

mation in Leaded and Lead-Free Solder Alloys

PHM for Field-Deployed Electronics Subjected to Multiple

Thermal Environments

Leadfree Part Reliability, Crack Propagation and Life Predic-

tion under Extreme Environments

The Effects of Environmental Exposure on Underfill Behavior

and Flip Chip Reliability

Models for Underfill Stress-Strain and Failure Behavior with Aging Effects

Insitu Die Stress Measurements in Flip Chip Packaging

Modeling and Material Characterization for Flip Chip Packag-ing

Theoretical and Experimental Investigation on Fretting Corro-sion and Thermal Degradation for Hybrid and Electric Vehicles

Complaint Pin/Press Fit Technology

Model Simulation and Validation for Vibration-Induced Fret-ting Corrosion

Vibration Based Interfaces for Information Transmission

Microstructural and Mechanical Studies of SAC/Sn-37Pb Mixed Solders

Aging Behavior of Next Generation Pb-Free Alloys

Extreme Low Temperature Behavior of Solders

Composition, Microstructure, and Reliability of Mixed Formu-

lation Solder Joints

QFP Reliability on Powered and Non-powered Thermal Cycle Environment

Harsh Environment Substrate Performance

Module Overmolding for Harsh Environments

Systems Reliability of Lead Free for Harsh Environment Elec-

tronics A block of rooms has been reserved for Review attendees at the

preferred group rate. Room block will expire on February 12, 2012.

Contact Information:

Auburn University Hotel & Conference Center

241 South College Street

Auburn, AL 36830

Call: (334) 821-8200

SPECIAL EVENTS

AIMS Harsh Environments Symposium

SMTAI 2011, Ft. Worth TX

Contact: J. Evans and P. Lall, Auburn University

October 17, 2011

Fort Worth Convention Center, Fort Worth, Texas

The SMTA announced that the AIMS Harsh Environments Sympo-

sium will be held on October 17, 2011 as a focused symposium at

SMTA International in Ft. Worth, TX. The AIMS Harsh Environ-ments Symposium addresses the concerns related to harsh environ-

ment electronics and the challenges within the electronics commu-

nity, with an added emphasis on military and space. It is intended to

bring together the needs of “end-users” with the capabilities of the

research community and the industrial supply base. Specifically, the

Symposium addresses the challenges of meeting expanding temper-

ature ranges (-55C to +150C/+200C) with increased vibration, high-

er package density and longer reliability. Session topics include

Thermo-Mechanical Analysis and Prognostics of Lead-Free Sol-

ders, Metallization and Connector Failure Mechanisms, Lead-Free

Component and Solder Joint Reliability Testing, and Reliability of SAC Solder Joints. Papers will be presented by speakers from IBM,

Celestica, Intel, and Alcatel-Lucent among others. Two internation-

al papers as well as three university papers help to round out the

program. The Harsh Environments Keynote Lunch will feature An-

thony Rafanelli, Ph.D., P.E., Raytheon Integrated Defense Systems,

presenting "How the Defense/Aerospace Industry is Responding to

the Lead-Free Challenge."

Selected Papers:

How the Defense/Aerospace Industry is Responding to the Pb-

Free (Lead-Free) Challenge, Anthony Rafanelli, Ph.D., P.E., Ray-

theon Integrated Defense Systems

Health Monitoring of Pb-Free Electronics Under Mechanical

Shock and Vibration with Particle Filter Based Resistance Spec-

troscopy, Pradeep Lall, Ryan Lowe, Kai Goebel, Auburn Univer-sity

NASA-DoD Lead-Free Electronics Rework Project: Effect of 1X

and 2X Eutectic Solder Rework on Vibration Reliability, J. P.

Tucker, C. A. Handwerker, Purdue University; W. Russell, Ray-

theon; D. D. Fritz, SAIC; A. Ganster, Crane Division-NSWC; P.

Snugovsky, J. Bragg, Z. Bagheri, M. Romansky, Ceestica Inc.

NASA/DoD Lead-Free Electronics Project: -20°C to +80°C Ther-

mal Cycle Test , Thomas Woodrow, Boeing.

Details of the AIMS Harsh Environments Symposium can be found

at http://www.smta.org/smtai/symposium.cfm#he

CAVE3 Review

CAVE3NEWS Fall 2011 2

High Strain-Rate Mechanical Properties of SAC and

Pb-free Alloys

Electronic products are subjected to high G-levels during mechani-

cal shock and vibration. Failure-modes include solder-joint failures,

pad catering, chip-cracking, copper trace fracture, and under-fill

fillet failures. The second-level interconnects may be experience high-strain rates and accrue damage during repetitive exposure to

mechanical shock. Industry migration to lead-free solders has re-

sulted in a proliferation of a wide variety of solder alloy composi-

tions. Few of the popular tin-silver-copper alloys include

Sn1Ag0.5Cu and Sn3Ag0.5Cu. The high strain rate properties of

lead-free solder alloys are scarce. Typical material tests systems are

not well suited for measurement of high strain rates typical of me-

chanical shock. Previously, high strain rates techniques such as the

Split Hopkinson Pressure Bar (SHPB) can be used for strain rates of

1000 per sec. However, measurement of materials at strain rates of

1-100 per sec which are typical of mechanical shock is difficult to

address. In the current research, a new test-technique developed by the authors has been used for the measurement of material constitu-

tive behavior. The instrument enables attaining strain rates in the

neighborhood of 1 to 100 per sec. High speed cameras operating at

50,000 fps have been used in conjunction with digital image corre-

lation for the measurement of full-field strain during the test.

Constancy of cross-head velocity has been demonstrated during the

test from the unloaded state to the specimen failure. Solder alloy

constitutive behavior has been measured for SAC105, SAC305 sol-

ders. Constitutive model has been fit to the material data. The con-

stitutive model has been embedded into an explicit FE framework

for the purpose of life-prediction of Pb-free interconnects.

Drop Reliability of Electronic under Ultra-High G

Shock Loads Ultra high-reliability components maybe experience very high G

levels. Examples of such cases include space shuttle launch and

reentry and high speed aircrafts such as jets. A novel type of inter-

connect, the micro-coil spring (MCS), is being tested for drop relia-

bility with minimum and maximum loadings from 10,000G to

40,000G respectively. To achieve such high levels, a special instru-

ment termed the Dual Mass Shock Amplifier (DMSA) must be used

in conjunction with accelerated drop speed using bungee cords. It

can be seen in Figure 1a that along with the base table there is also a

secondary drop table. This secondary drop table allows a longer

drop time. Bungee cords are attached to the base table to accelerate

the table towards the seismic instead allowing a free fall. Digital Image Correlation (DIC) is used to observed in-plane and out of

plane displacement. DIC is used to get full field displacement and

strain date, see Figure 1b. A global-local type model is being used

to simulate the MCS interconnect during drop testing. See figure 1c

for the finite element model.

Research Highlights

CAVE3 NEWS Fall 2011 3

(c)

Figure-1: (a) & (b) Time to failure and failure mode predicted by

FEM for SAC305 specimens at strain rate 55 sec-1. (c) Stress vs.

Strain for pristine SAC305 specimens at strain rates 20sec-1 & 55

sec-1

(a) (b)

Figure-2: (a) Ultra High-G (40000 G’s) Shock testing Set up. (b)

Sample Out of plane displacement from digital image correlation. ©

High speed imaging and Finite element model of Micro-coil spring.

FE Modeling of the Buildup of Compressive Stresses

in a Microprocessor Chip

Microprocessor packaging in modern workstations and servers of-

ten consists of one or more large flip chip die that are mounted to a

high performance ceramic chip carrier. The final assembly configu-

ration features a complex stack up of flip chip area array solder in-

terconnects, under-fill, ceramic substrate, lid, heat sink, thermal

interface materials, second level CBGA solder joints, organic PCB,

etc., so that a very complicated set of loads is transmitted to the

microprocessor chip. Several trends in the evolution of this packag-

ing architecture have exacerbated die stress levels including the

transition to larger die, high CTE ceramic substrates, lead free sol-

der joints, higher level of power generation, and larger heat sinks. Die stress effects are of concern due to the possible degradation of

silicon device performance (mobility/speed) and due to the possible

damage that can occur to the copper/low-k top level interconnect

layers.

In this work, we have used finite element analysis to predict the

stresses induced in microprocessor die after various steps of the

assembly process, as well as to as well as due to heat sink clamping

and subsequent powered operation (stress evolution during thermal

cycling and power cycling). The developed normal stresses are

compressive (tri-axial compression) across the die surface, with

significant in-plane and out-of-plane (interfacial) shear stresses also

present at the die corners. The compressive stresses increase with

each assembly step (flip chip solder joint reflow, under-fill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink

clamping). For extremely high heat sink clamping forces, we ex-

pect to see a big stress level in the die. A novel sequential modeling

approach has been utilized to predict the build-up of compressive

stress. The utilized method incorporates precise thermal histories of

the packaging process, element creation, and nonlinear temperature

and time dependent material properties.

Extended Kalman Filter Models for PHM Pb-Free

Electronics Under Vibration

A technique has been developed for monitoring the structural dam-

age accrued in BGA interconnects during operation in vibration

environments. The technique uses resistance spectroscopy based

state space vectors, rate of change of the state variable, and acceler-

ation of the state variable in conjunction with Extended Kalman

Filter and is intended for the pre-failure time-history of the compo-

nent. Condition monitoring using the presented technique can pro-

vide knowledge of impending failure in high reliability applications

where the risks associated with loss-of-functionality are too high to bear. The methodology has been demonstrated on SAC305 Pb-free

area-array electronic assemblies subjected to vibration. Future state

of the system has been estimated based on a second order Extended

Kalman Filter model and a Bayesian Framework. The measured

state variable has been related to the underlying interconnect dam-

age using plastic strain. Performance of the prognostication health

management algorithm during the vibration test has been quantified

using performance evaluation metrics. Model predictions have

been correlated with experimental data. The presented approach is

applicable to functional systems where corner interconnects in area-

array packages may be often redundant. Prognostic metrics includ-

ing metric, beta, and relative accuracy have been used to assess the performance of the damage proxies. The presented approach ena-

bles the estimation of RUL based on level of risk averseness.

Research Highlights

CAVE3NEWS Fall 2011 4

Figure 3: Device Side Die Stress Distribution After Lid Attachment

Process

Figure 4: Device Side Die Stress After CBGA Assembly and Heat

Sink Clamping

Figure 5: Particle Filter Framework for Prognostication.

Supervised Learning of Damage Initiation and Pro-

gression in Electronics under Shock by Neural Nets

Electronic systems under extreme shock and vibration environments

including shock and vibration may sustain several failure modes

simultaneously. Previous experience of the authors indicates that

the dominant failure modes experienced by packages in a drop and

shock frame work are in the solder interconnects including cracks at

the package and the board interface, pad catering, copper trace fa-

tigue, and bulk-failure in the solder joint. In this project, a neural

network base frame work is developed for failure mode classifica-

tion in electronics under mechanical shock. Figure-1 represents the

designed network used for fault mode parity in test assemblies. The

pre-failure feature space is de-correlated using KL-transform. Hard parity between different failure modes is achieved using stepwise

supervised training of a perceptrons. Pre-failure feature space has

been formed by joint time frequency distribution for the classifica-

tion of different fault modes in electronic assemblies subjected to

drop and shock. Since the cumulative damage may be accrued un-

der repetitive loading with exposure to multiple shock events, the

area array assemblies have been exposed to shock and feature vec-

tors constructed to track damage initiation and progression. The

classified failure modes and failure regions belonging to each par-

ticular failure modes in the feature space are also validated by simu-

lation of the designed neural network used for parity of feature space. The methodology adopted in this paper can perform real-

time fault monitoring with identification of specific dominant fail-

ure mode. The supervised learning approach presented in this work

is scalable to system level reliability. Supervised methodology pro-

posed in this work is capable/inclusive of addressing damage initia-

tion and progression as well as fault isolation is new in prognostics

and health management framework for electronics.

The Effects of Variations in Manufacturing on PCB

Thermal Properties

The thermal performance of an electronic device is heavily depend-

ent on the properties of the printed circuit board (PCB) to which it

is attached. However, even small variations in the process used to

fabricate a PCB can have drastic effects on its thermal properties.

Therefore, it is necessary to experimentally verify that each stage in

the manufacturing process is producing the desired result. Two ven-

dors were asked to produce PCBs from the same design. The steady

state thermal resistances of 1” by 1” sections of these PCBs were

then measured with a comparative cut bar apparatus based on

ASTM D 5470-06 and the thickness of each of the layers was meas-ured. Despite being fabricated from the same design, there were

significant differences between the stack-ups of the two boards, as

shown in Figure 9, and the thermal resistances varied by as much as

30%. The vendor with the higher thermal resistance was then asked

to produce a second set of boards with an identical stack-up to the

one used by the other vendor. However, even with the same design

and identical stack-ups, the thermal resistance still varied by as

much as 20%. A vendor was asked to produce two identical PCBs

with the exception that one was to have the vias filled with an

epoxy while the vias in the other boards were to be left empty. It

was expected that, even though the epoxy did not have an especially

high thermal conductivity, it would still conduct more heat than the air it was replacing, and therefore the PCBs with the filled vias

would have a lower thermal resistance that the PCBs with the un-

filled vias. However, after measuring the thermal resistances with a

comparative cut bar apparatus, the opposite turned out to be true:

the unfilled vias had a lower thermal resistance than the filled vias.

After further investigation, it was found that the PCBs with the

epoxy filled vias had a thinner layer of copper around the walls of

the vias than did the unfilled vias, as shown in Figure 10. This was

a side effect of the order in which the vendor chose to perform the

fabrication steps, i.e. the vias were filled prior to the final plating

step. As a result, the thermal improvement provided by the epoxy was counteracted by the degradation of the thermal path through the

via walls.

Research Highlights

CAVE3 NEWS Fall 2011 5

(a) (b)

Figure 6: Fault Mode Classification by Supervised Learning (a) Hard

Parity of Failure modes (b) Validation of Classified Failure Modes.

Figure 7: Cross sections showing variations in stack up between

vendors.

Figure 8: Cross sections of filled and unfilled vias showing a thicker

layer of copper lining the inside wall of the vias in the unfilled

boards than in the filled boards.

The Effect of Dopants on the Aging Behavior of Lead

Free Solders

The microstructure, mechanical response, and failure behavior of

lead free solder joints in electronic assemblies are constantly evolv-

ing when exposed to isothermal aging and/or thermal cycling envi-

ronments. Over the past several years, we have demonstrated that

the observed material behavior variations of Sn-Ag-Cu (SAC) lead

free solders during room temperature aging (25 C) and elevated

temperature aging (50, 75, 100, 125, and 150 C) were unexpectedly

large and universally detrimental to reliability. The measured stress

-strain data demonstrated large reductions in stiffness, yield stress,

ultimate strength, and strain to failure (up to 50%) during the first 6

months after reflow solidification. In addition, even more dramatic evolution was observed in the creep response of aged solders, where

up to 100X increases were found in the steady state (secondary)

creep strain rate (creep compliance) of lead free solders that were

simply aged at room temperature. For elevated temperature aging

at 125 C, the creep strain rate was observed to change even more

dramatically (up to 10,000X increase).

There is much interest in the industry on establishing optimal SAC-

based lead free solder alloys that minimize aging effects and thus

enhance thermal cycling and elevated temperature reliability. Dur-

ing the past year, we have extended our previous studies to include

several doped SAC alloys (SAC-X) where the standard SAC alloys

have been modified with small percentages of one or two additional

elements (X). Materials under consideration include SAC0307-X,

Sn-.7Cu-X, SAC305-X, SAC3595-X and SAC3810-X. Using do-

pants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, etc.) has become

widespread to enhance shock/drop reliability, and we have extended this approach to examine the ability of dopants reduce the effects of

aging and extend thermal cycling reliability.

In the current work, we concentrate on showing results for

SACXTM, which has the composition Sn-0.3Ag-0.7Cu-X with X =

0.1Bi. We have performed aging under 5 different conditions in-

cluding room temperature (25 C), and four elevated temperatures

(50, 75, 100 and 125). We have also extended the duration of ag-ing considered in our experiments to up to 12 months of aging on

selected alloys. Variations of the mechanical and creep properties

(elastic modulus, yield stress, ultimate strength, creep compliance,

etc.) have been observed. We have correlated the aging results for

the doped SAX-X alloy with our prior data for the “standard” lead

free alloys SACN05 (SAC105, SAC205, SAC305, SAC405). The

doped SAC-X alloy shows improvements (reductions) in the aging-

induced degradation in stiffness, strength, and creep rate when com-

pared to SAC105, even though it has lower silver content. In addi-

tion, the doped SAC-X alloy has been observed to reach a stabilized

microstructure more rapidly when aged. Mathematical models for

the observed aging variations have been established so that the vari-ation of the stress-strain and creep properties can be predicted as a

function of aging time and aging temperature.

Effects of Aging on the Cyclic Stress-Strain Behavior

and Hysteresis Loop Evolution of Lead Free Solders

Solder joints in electronic assemblies are typically subjected to ther-

mal cycling, either in actual application or in accelerated life testing

used for qualification. Mismatches in the thermal expansion coeffi-cients of the assembly materials leads to the solder joints being sub-

jected to cyclic (positive/negative) mechanical strains and stresses.

This cyclic loading leads to thermo-mechanical fatigue damage that

involves damage accumulation, crack initiation, crack propagation,

and failure. While the effects of aging on solder constitutive behav-

ior (stress-strain and creep) have been examined in some detail,

there have been no prior studies on the effects of aging on solder

Research Highlights

CAVE3NEWS Fall 2011 6

Figure 9: Variation of Ultimate Tensile Strength with Aging at 100

deg C (SAC-X, SAC105, SAC205)

Figure 10: Creep Rate Evolution with Aging at 100 deg C (SAC-X,

SAC105, SAC205)

Experimental Characterization & Visco-plastic Mod-

eling of Temperature Dependent Under-fill

In this work, the visco-plastic mechanical response of a typical un-

derfill encapsulant has been characterized via rate dependent stress-

strain testing over a wide temperature range, and creep testing for a

large range of applied stress levels and temperatures. A specimen

preparation procedure has been developed to manufacture 80 x 5

mm uni-axial tension test samples with a specified thickness of .5

mm. The test specimens are dispensed and cured with production

equipment using the same conditions as those used in actual flip

chip assembly, and no release agent is required to extract them from

the mold.

failure and fatigue behavior.

In this investigation, we have examined the effects of several pa-

rameters (aging, temperature, strain/stress limits, and solder alloy

composition) on the cyclic stress-strain behavior of lead free sol-

ders. Uniaxial SAC lead free solder specimens were subjected to cyclic (tension/compression) mechanical loading. Samples were

cyclically loaded under both strain control (constant positive and

negative strain limits) and stress control (constant positive and neg-

ative stress limits). The hysteresis loop size (area) was calculated

from the measured cyclic stress-strain curves for a given solder al-

loy and temperature. This area represents the strain energy density

dissipated per cycle, which can be typically correlated to the dam-

age accumulation in the joint. Most tests in this investigation were

performed with SAC105 solder alloy. However, the effect of solder

composition was examined in a limited way by testing four SAC

alloys (SAC105, SAC205, SAC305, SAC405) with varying silver

content (1-4%) under strain controlled cycling. In addition, the effect of the testing temperature has also been studied by perform-

ing cyclic testing of SAC405 samples at four different temperatures

(25, 50, 75, and 100 oC).

Prior to cyclic loading, the specimens in this study were aged

(preconditioned) at 125 oC for various aging times (0-6 months).

From the recorded cyclic stress-strain curves, we have been able to

characterize and empirically model the evolution of the solder hys-

teresis loops with aging. Similar to solder stress-strain and creep

behaviors, there is a strong effect of aging on the hysteresis loop

size (and thus the rate of damage accumulation) in the solder speci-

mens. The observed degradations in the fatigue/cyclic behavior of the lead free solders are highly accelerated for lower silver content

alloys (e.g., SAC105), and for aging and testing at higher tempera-

tures. In our current work, we are also subjecting aged solder sam-

ples to cyclic loading until failure occurs. Our ultimate goal is to

understand the effects of aging on the thermo-mechanical fatigue

life.

Research Highlights

CAVE3 NEWS Fall 2011 7

Figure 11: Typical Cyclic Stress-Strain Test Results for SAC Solder

(Strain Controlled)

Figure 12: Comparison of Hysteresis Aging Behaviors of Reflowed

and Water Quenched Samples (SAC105, Strain Controlled Cycling)

Figure 13: Correlation of Prony Series Viscoelastic Model Predic-

tions with Underfill Stress-Stain Data

Using the manufactured test specimens, a microscale tension-

torsion testing machine has been used to evaluate stress-strain and

creep behavior of the underfill material as a function of tempera-

ture. Stress-strain curves have been measured at 5 temperatures

(25, 50, 75, 100 and 125 C), and strain rates spanning over 4 orders of magnitude. In addition, creep curves have been evaluated for the

same 5 temperatures and several stress levels. With the obtained

mechanical property data, several viscoelastic and viscoplastic ma-

terial models have been fit to the data, and optimum constitutive

models for subsequent use in finite element simulations have been

determined.

Encouraging News for Whisker Prevention Using

Selective Ni Cap

We are currently investigating whether topside Ni can stop/suppress

whisker growth on sputtered Sn films. The results will lend experi-

mental verification/refutation of the “Landman-Davy-Fritz” proce-

dure of using selective Ni caps to stop whiskers.

Using masking techniques, Ni layers of 350, 700, 1500, and 3100 Å

were sputter deposited on compressively stressed ~1600 Å Sn films

on Si, leaving the other half of the coupon Sn. After about three

months of incubation at room temperature/humidity, all the Sn sides are producing whiskers at densities > 10,000 whiskers/cm2; howev-

er, all the Ni sides have completely suppressed whisker growth,

with the exception of the 350 Å film, where a single, 181 µm long

whisker has penetrated through the Ni.

Development of Lamination Theory for Composite

Substrates

The research is tend to develop theoretical approaches for estimat-

ing the global/bulk coefficients of thermal expansion and mechani-

cal properties of printed circuit boards based on layer properties and

stack-up configuration lamination theory. Moreover, the experi-

ments are measuring properties of individual carbon fiber PCB lay-

ers (plies), coefficient of thermal expansion, elastic moduli, Pois-son’s Ratios, shear modulus correlate predictions with experimental

measurements for actual PCBs. The carbon fiber layers feature high

stiffness and high thermal conductivity, as well as near zero thermal

expansion coefficients. The material properties have be obtained

through out varies experiments and testing. In this case, the charac-

teristic of the bulk PCBs can be predicted by lamination theory.

Furthermore, a well established lamination theory may even have

the ability to tailor-made PCBs for different usage.

Figure 16: Images of Composite Laminate

Research Highlights

CAVE3NEWS Fall 2011 8

Figure 14: Correlation of Prony Series Viscoelastic Model Predic-

tions with Underfill Creep Data

Figure 15: A single, 181 Å m whisker penetrating the 350 Å Ni

layer after ~ 90 days of incubation.

Dr. Lall Presents Keynote at EuroSime 2011

Professor Lall presented a Keynote address at the 12th EuroSIME

Conference held in Linz, Austria, April 18-20, 2011. The keynote

address on the topic of prognostics and health monitoring for elec-

tronic systems focused on a broad class of techniques developed at the CAVE3 Electronic Research Center. Topics presented included

in-situ estimation of residual life in fully-functional electronic sys-

tems using physics-based leading indicators, feature vectors, failure

-mode classification and remaining useful life estimation tech-

niques. The conference wide keynote was well attended.

CAVE3 Team Presents Professional Development Course at

IEEE-PHM 2011 Conference

Professor Lall and doctoral student Ryan Lowe presented a profes-

sional development course on the topic of prognostics health moni-

toring for electronic systems at the PHM 2011 Conference. The

conference was held in Denver, Colorado from June 20-23, 2011. Topics covered included: Approaches for monitoring system health,

Methods for data analysis, Leading indicators of failure for various

types of failure mechanisms, Algorithms for data reduction and

parameter extraction, Approaches for residual life estimation, and

Statistical assessment of uncertainty of system survivability in fu-

ture deployment.

CAVE3 Researchers Win Best Paper Award at ECTC 2010

CAVE3 Paper titled, Reduction of Lead Free Solder Aging Effects

using Doped SAC Alloys, Z. Cai, Y. Zhang, J. C. Suhling, P. Lall,

R. W. Johnson, M. J. Bozack, ECTC, pp. 1493-1511, 2010, won the Best Paper Award. The paper focuses on the characterization of

lead-free solder materials under high-temperature exposure of elec-

tronics. The award was conferred at the ECTC 2011 conference

held in Orlando, Florida from May 31-June3, 2011. ECTC is a

premier electronic packaging conference sponsored by the Institute

of Electrical and Electronics Engineers (IEEE).

CAVE3 Faculty and Researchers Present at ASME IN-

TERPACK’11

Several Students and Faculty attended the ASME InterPACK Con-

ference held in Portland, Oregon from July 6-8, 2011. CAVE3 stu-

dents presented several papers at the conference. Paper Topics in-

clude: (a) The Effects of Dopants on the Aging Behavior of Lead

Free Solders [IPACK2011‑52184] (b) Characterization of Die

Stresses in CBGA Packages due to Component Assembly and Heat

Sink Clamping [IPACK2011‑52185] (c) Characterization of Hyste-

resis Loop Evolution in Aged Lead Free Solders

[IPACK2011‑52186] (d) Constitutive Behavior of SAC Leadfree

Alloys at High Strain Rates [IPACK2011‑52194] (e) Ridge Regres-

sion Based Development of Norris-Landzberg Acceleration Factors

and Goldmann Constants for Leadfree Electronics

[IPACK2011‑52195] (f) SIF Evaluation Using XFEM and Line

Spring Models Under High Strain Rate Environment for Leadfree

Alloys [IPACK2011‑52196] (g) PHM of Leadfree Interconnects

Using Resistance Spectroscopy Based Particle Filter Models for

Shock and Vibration Environments [IPACK2011‑52197] (h) KL

Transform and Neural-Net Based Framework for Failure Modes

Classification in Electronics Subjected to Mechanical-Shock

[IPACK2011‑52198] (i) Experimental Characterization and Visco-

plastic Modeling of the Temperature Dependent Material Behavior

of Underfill Encapsulants [IPACK2011‑52209] (j) Reliability Stud-

ies for Package-on-Package Components in Drop and Shock Envi-

ronments [IPACK2011‑52231] (k) The Effects of Variations in

Manufacturing on PCB Thermal Properties [IPACK2011‑52113].

CAVE3 Researchers Win Best Paper Award at SMTAI 2010

CAVE3 Researchers received the Best of Session-Paper Award for their paper titled: Interrogation Of Damage-State in Lead-Free Elec-

tronics Under Sequential Exposure to Thermal Aging and Thermal

Cycling, Lall, P., Vaidya, R., More, V., Goebel, K., SMTA Interna-

tional, Orlando, Florida, pp. 405-418, October 24-28, 2010. The

award winning paper developed a PHM technique based on non-

linear least-squares method called Levenberg-Marquardt (LM) al-

gorithm which has been developed for two different damage prox-

ies. Prognostic model performance based on standard prognostic

metrics has also been evaluated for both the damage proxies to de-

termine which leading indicator of failure can be employed for ac-

curate life prediction. Results of interrogation of system state have been compared with a second set of experimental-matrix to validate

the proposed methodology. SMTAI is a premier electronic packag-

ing conference focusing on materials and processing, assembly,

design, system level engineering, and supply chain management.

The award will be conferred at the SMTAI 2011.

Dr. Lall serves as Steering Committee Vice-Chair Elect at

ASME International Mechanical Engineering Congress 2011

Professor Lall will serve as the Vice-Chair Elect of the Steering

Committee of the ASME for the International Mechanical Engi-

neering Congress and Exhibition to be held in Denver, Colorado

from November 11-17, 2011. The annual ASME International Me-chanical Engineering Congress and Exposition is a premier global

conference that focuses on technical challenges, research updates

and breakthrough innovations that are shaping the future of engi-

neering. The Congress convenes engineers, scientists and technolo-

gists of all disciplines for the purposes of exploring solutions to

Announcements

CAVE3 NEWS Fall 2011 10

global challenges and for the advancement of engineering excel-

lence worldwide.

CAVE3 Student Wins Student Poster Competition

Jordan Roberts received the Outstanding Poster Award at the ASME 2011 Pacific Rim Technical Conference and Exposition on

Packaging and Integration of Electronic and Photonic Systems

(ASME InterPACK 2011). The poster titled “Characterization of

Die Stresses in CBGA Packages due To Component Assembly and

Heat Sink Clamping,” was part of the international student competi-

tion in the Mechanics and Reliability division. Over 40 participants

from 17 universities took part in the competition.

Dr. Lall served as Tutorial Committee Chair at IEEE Confer-

ence on Prognostics and Health Management

Professor Lall served as the tutorials chair at the IEEE PHM 2011

Conference held at Denver, Colorado from June 20-23, 2011. The

tutorials track included 8-tutorials in two parallel tracks over the course of first-day of the conference.

CAVE3 Receives DOE Grant on SSL Luminaries

Professor Lall, Director of CAVE3 received a DOE grant on the

topic of “System Reliability Model for SSL Luminaires”. The three

-year grant was received jointly with RTI technologies. Solid-state

lighting (SSL) is an emerging illumination technology that offers

the promise of greater energy efficiency and longer product life-

times. Studies by the U.S. Department of Energy (DOE) have con-

cluded that 22% of all electricity consumed in the United States

goes to provide general illumination. Improvements in the energy efficiency of SSL products over incandescent and fluorescent light-

ing could provide significant reductions in fossil fuel consumption

and the accompanying carbon dioxide (CO2) emissions.

CAVE3 Receives NSF FRP Grant

Professor Lall, Director of CAVE3 received a two-year fundamen-

tal research grant from the National Science Foundation on the top-

ic of Survivability Envelopes for Lead-Free Interconnects in Fine-

Pitch Electronics under Combined Extreme Environments of Shock,

Vibration and Temperature. Electronics in extreme environments

may be subjected to overlapping stresses during normal usage and

unanticipated operation. Failure-modes include solder-joint fail-

ures, pad cratering, chip-cracking, copper trace fracture, and under-

fill fillet failures. Potential benefits of the proposed research are

highlighted by the relevance of combined environments to automo-tive applications and increased reliance on electronics for safety

systems such as collision avoidance and lane departure.

CAVE3 Receives DARPA Grant on Sensors

Professors Lall, Hamilton and Dean received a DARPA Phase-II

sub-contract from Streamline Automation. The research contract

requires the development of sensors, sensor electronics, and an elec-

tronics nose for detection of hydrogen, ammonia and hydrazine.

Dr. Lall to serve as Guest Editor for Special Section on PHM of

Electronics in IEEE Transactions on Reliability

Professor Lall will serve as the Guest Editor of the Special Section of the IEEE Transaction on Reliability on the topic of Prognostic

Health Management Systems. PHM has emerged as a key enabling

technology to provide an early warning of failure in a variety of

applications including electronics, smart grid, distributed, net-

worked and cloud computing, aerospace and defense applications,

and fleet-industrial maintenance. Topics to be included in this spe-

cial section on Prognostic Health Management include the three

topical areas of principles, systems design and implementation and

applications.

CAVE3 NEWS Fall 2011 11

Announcements

1. Roberts, J.C., Motalab, M., Hussain, S., Suhling, J., Jaeger,

R.C., Lall, P., Squeezing the Chip: The Buildup of Compres-

sive Stress in a Microprocessor Chip by Packaging and Heat

Sink Clamping, Electronic Components and Technology Con-

ference, 2011. ECTC 2011. 61st, pp.406-423, 2011. 2. Lall, P., Shantaram, S., Kulkarni, M., Limaye, G., Suhling, J.,

High Strain-Rate Mechanical Properties of SnAgCu Leadfree

Alloys, Electronic Components and Technology Conference,

2011. ECTC 2011. 61st, pp.684-700, 2011.

3. Lall, P., Harsha, M., Kumar, K., Goebel, K., Jones, J., Suhling,

J., Interrogation of Accrued Damage and Remaining Life in

Field-Deployed Electronics Subjected to Multiple Thermal

Environments of Thermal Aging and Thermal Cycling, Elec-

tronic Components and Technology Conference, 2011. ECTC

2011. 61st, pp.775-789, 2011.

4. Mustafa, M., Cai, Z., Suhling, J., Lall, P., The Effects of Aging

on the Cyclic Stress-Strain Behavior and Hysteresis Loop Evo-lution of Lead Free Solders, Electronic Components and Tech-

nology Conference, 2011. ECTC 2011. 61st, pp.927-939, 2011.

5. Lall, P., Lowe, R., Goebel, K., Particle Filter Models and Phase

Sensitive Detection for Prognostication and Health Monitoring

of Leadfree Electronics under Shock and Vibration, Electronic

Components and Technology Conference, 2011. ECTC

2011.61st, pp.1097-1109, 2011.

6. Lall, P., Gupta, P., Goebel, K., Identification of Failure Modes

in Portable Electronics Subjected to Mechanical-Shock using

Supervised Learning of Damage Progression, Electronic Com-

ponents and Technology Conference, 2011. ECTC 2011. 61st, pp.1944-1957, 2011.

7. Zhang, R., Zhang, J., Evans, J., Johnson, W., Vardaman, J.,

Fujimura, I., Tseng, A., Knight, R., Tin-Bismuth Plating for

Component Finishes, Electronic Components and Technology

Conference, 2011. ECTC 2011. 61st, pp.2060-2066, 2011.

8. Cai, Z., Suhling, J., Lall, P., Bozack, M.J., The Effects of Do-

pants on the Aging Behavior of Lead Free Solders, ASME In-

terPACK, pp. 1-16, Portland, Oregon, USA, July 6-8, 2011.

9. Roberts, J.C., Motalab, M., Hussain, S., Suhling, J., Jaeger,

R.C., Lall, P., Characterization of Die Stresses in CBGA Pack-

ages due to Component Assembly and Heat Sink Clamping,

ASME InterPACK, pp. 1-14, Portland, Oregon, USA, July 6-8, 2011.

10. Mustafa, M., Cai, Z., Suhling, J., Lall, P., Characterization of

Hysteresis Loop Evolution in Aged Lead Free Solders, ASME

InterPACK, pp. 1-12, Portland, Oregon, USA, July 6-8, 2011.

11. Lall, P., Shantaram, S., Kulkarni, M., Limaye, G., Suhling, J.,

Constitutive Behavior of SAC Leadfree Alloys at High Strain

Rates, ASME InterPACK, pp. 1-18, Portland, Oregon, USA,

July 6-8, 2011.

12. Lall, P., Arunachalam, D., Suhling, J., Ridge Regression Based

Development of Norris-Landzberg Acceleration Factors and

Goldmann Constants for Leadfree Electronics, ASME In-terPACK, pp. 1-11, Portland, Oregon, USA, July 6-8, 2011.

13. Lall, P., Shantaram, S., Kulkarni, M., Suhling, J., SIF Evalua-

tion Using XFEM and Line Spring Models Under High Strain

Rate Environment for Leadfree Alloys, ASME InterPACK, pp.

1-17, Portland, Oregon, USA, July 6-8, 2011.

14. Lall, P., Lowe, R., Goebel, K., PHM of Leadfree Interconnects

Using Resistance Spectroscopy Based Particle Filter Models

for Shock and Vibration Environments, ASME InterPACK, pp.

1-14, Portland, Oregon, USA, July 6-8, 2011. 15. Lall, P., Gupta, P, Goebel, K., KL Transform and Neural-Net

Based Framework for Failure Modes Classification in Electron-

ics Subjected to Mechanical-Shock, ASME InterPACK, pp. 1-

16, Portland, Oregon, USA, July 6-8, 2011.

16. Chhanda, N.J., Lall, P., Suhling, J., Experimental Characteriza-

tion and Viscoplastic Modeling of the Temperature Dependent

Material Behavior of Underfill Encapsulants, ASME In-

terPACK, pp. 1-13, Portland, Oregon, USA, July 6-8, 2011.

17. Lall, P., Angral, A., Suhling, J., Reliability Studies for Package

-on-Package Components in Drop and Shock Environments,

ASME InterPACK, pp. 1-12, Portland, Oregon, USA, July 6-8,

2011. 18. Maddox, J. F., Knight, R. W., Bhavnani, S. H., The Effects of

Variations in Manufacturing on PCB Thermal Properties,

ASME InterPACK, pp. 1-7, Portland, Oregon, USA, July 6-8,

2011.

19. Lall, P., Lowe, R., Goebel, K., Prognostics and Health Moni-

toring of Electronic Systems, IEEE 12th. Int. Conf. on Ther-

mal, Mechanical and Multiphysics Simulation and Experiments

in Microelectronics and Microsystems, EuroSimE 2011, pp. 1-

17, 2011.

20. Lall, P., Lowe, R., Goebel, K., Extended Kalman Filter Models

and Resistance Spectroscopy for Prognostication and Health Monitoring of Leadfree Electronics Under Vibration, IEEE

International Conference on Prognostics and Health Manage-

ment (PHM), 2011.

21. Lall, P., Gupta, P., Goebel, K., Decorrelated Feature Space and

Neural Nets Based Framework For Failure Modes Clustering in

Electronics Subjected to Mechanical-Shock, IEEE International

Conference on Prognostics and Health Management (PHM),

2011.

22. Crandall E. R., Flowers G. T., Lall P. and Bozack M. J., Oxida-

tion-Induced Growth of Sn Whiskers in a Pure Oxygen Gas

Environment, IEEE Electrical Contacts, 56th Holm Confer-

ence, pp.1-5, 2010. 23. Crandall E. R., Flowers G. T., Lall P. and Bozack M. J.,

Whisker Growth During Exposure to Controlled Humidity,

IEEE Electrical Contacts, 56th Holm Conference, pp.1-6, 2010.

24. Crandall E. R., Flowers G. T., Lall P. and Bozack M. J., Oxida-

tion-Induced Growth of Sn Whiskers in a Pure Oxygen Gas

Environment, IEEE Electrical Contacts, 56th Holm Confer-

ence, pp.1-5, 2010.

25. Crandall E. R., Flowers G. T., Lall P. and Bozack M. J.,

Whisker Growth During Exposure to Controlled Humidity,

IEEE Electrical Contacts, 56th Holm Conference, pp.1-6, 2010.

All other published CAVE3 articles are available at cave.auburn.edu

under Publications

Selected Recent Publications

CAVE3 NEWS Fall 2011 12

cave3 News Fall 2011

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