Fairness via Source Throttlingusers.ece.cmu.edu/~omutlu/pub/ebrahimi_asplos10_talk.pdfB1 A1 A2 A3...

Fairness via Source Throttling:

A configurable and high-performance fairness substrate for multi-core memory systems

Eiman Ebrahimi*

Chang Joo Lee*

Onur Mutlu‡

Yale N. Patt*

* HPS Research Group

The University of Texas at Austin

‡ Computer Architecture Laboratory

Carnegie Mellon University

Wednesday, March 17, 2010

Background and Problem

Core 0 Core 1 Core 2 Core N...

2



Core 0 Core 1 Core 2 Core N

Shared Cache

Memory Controller

DRAMBank 0

DRAMBank 1

DRAM Bank 2

... DRAMBank K

...

Chip BoundaryOn-chipOff-chip

2



Core 0 Core 1 Core 2 Core N

Shared Cache

Memory Controller

DRAMBank 0

DRAMBank 1

DRAM Bank 2

... DRAMBank K

...

Shared MemoryResources

Chip BoundaryOn-chipOff-chip

2


•Applications slow down due to interference from memory requests of other applications

3



• A memory system is fair if slowdowns of same-priority applications are equal(MICRO ’06, MICRO ’07, ISCA ’08)


3





3


SharedTi

•Slowdown of application i = Ti

Alone




3


SharedTi


Alone

Max{Slowdown i} over all applications i

Min{Slowdown i} over all applications i(MICRO ’07)

•Unfairness =


4



• Magnitude of each application’s slowdown depends on concurrently running applications’ memory behavior

4



0

1

2

3

4

5

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Slow

dow

n• Magnitude of each application’s slowdown depends on

concurrently running applications’ memory behavior

4



0

1

2

3

4

5

zeus art

Slow

dow



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0

1

2

3

4

5

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Slow

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• Large disparities in slowdowns are unacceptable

01234567


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4



0

1

2

3

4

5

zeus art

Slow

dow



• Large disparities in slowdowns are unacceptable• Low system performance

01234567


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4



0

1

2

3

4

5

zeus art

Slow

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• Large disparities in slowdowns are unacceptable• Low system performance • Vulnerability to denial of service attacks

01234567


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4



0

1

2

3

4

5

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Slow

dow



• Large disparities in slowdowns are unacceptable• Low system performance • Vulnerability to denial of service attacks• Difficult for system software to enforce priorities

01234567


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4



•Background and Problem

•Motivation for Source Throttling

• Fairness via Source Throttling (FST)

•Evaluation

•Conclusion

5

Outline


6

Prior Approaches


• Primarily manage inter-application interference in only one particular resource

• Shared Cache, Memory Controller, Interconnect, etc.

6

Prior Approaches




• Combining techniques for the different resources can result in negative interaction

6

Prior Approaches





• Approaches that coordinate interaction among techniques for different resources require complex implementations

6

Prior Approaches





• Approaches that coordinate interaction among techniques for different resources require complex implementations

Our Goal: Enable fair sharing ofthe entire memory system by dynamically detecting and controlling interference in a coordinated manner

6

Prior Approaches


7

Our Approach


• Manage inter-application interference at the cores, not at the shared resources

7

Our Approach



• Dynamically estimate unfairness in the memory system

7

Our Approach



• Dynamically estimate unfairness in the memory system

• If unfairness > system-software-specified target thenthrottle down core causing unfairness & throttle up core that was unfairly treated

7

Our Approach


A:B:

Unmanaged Interference

A:

B:Fair Source Throttling


Oldest ⎧｜｜⎩


A:B:


A:


queue of requests to shared resources


Oldest ⎧｜｜⎩


A: Compute

ComputeB:Unmanaged Interference

A:




Oldest ⎧｜｜⎩


A: Compute

ComputeB:

Request Generation Order: A1, A2, A3, A4, B1


A:




A4B1

A1

A2

A3

Oldest ⎧｜｜⎩


A: Compute

ComputeB:



A:




A4B1

A1

A2

A3

Oldest ⎧｜｜⎩


A: Compute Stall on A1 Stall on A2 Stall on A3 Stall on A4

ComputeB:



A:




A4B1

A1

A2

A3

Oldest ⎧｜｜⎩



ComputeB:



Core A’s stall time

A:




A4B1

A1

A2

A3

Oldest ⎧｜｜⎩



Compute Stall waiting for shared resourcesB:




A:




A4B1

A1

A2

A3

Oldest ⎧｜｜⎩



Compute Stall waiting for shared resources Stall on B1B:




A:




A4B1

A1

A2

A3

Oldest ⎧｜｜⎩






Core A’s stall timeCore B’s stall time

A:




A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A:



Intensive application A generates many requests and causes long stall times for less intensive application B


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A: Compute

ComputeB:Fair Source Throttling

Request Generation OrderA1, A2, A3, A4, B1




A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A: Compute


Request Generation OrderA1, B1, A2, A3, A4



Throttled Requests


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







⎧｜｜⎩


A: Compute





Oldest


Throttled Requests


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A4

B1

A1

A2

A3

⎧｜｜⎩


A: Compute





Oldest


Throttled Requests


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A4

B1

A1

A2

A3

⎧｜｜⎩


A: Compute Stall on A1

Compute Stall wait.B:Fair Source Throttling




Oldest


Throttled Requests


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A4

B1

A1

A2

A3

⎧｜｜⎩



Compute Stall wait. Stall on B1B:Fair Source Throttling

Stall wait.




Oldest


Throttled Requests


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A4

B1

A1

A2

A3

⎧｜｜⎩



Compute Stall wait. Stall on B1B:

Core B’s stall time

Fair Source Throttling

Stall wait.




Oldest


Throttled Requests


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A4

B1

A1

A2

A3

⎧｜｜⎩


A: Compute Stall on A1 Stall on A2




Stall wait.




Oldest


Throttled Requests

Stall on A4Stall on A3


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A4

B1

A1

A2

A3

⎧｜｜⎩







Stall wait.




Oldest


Throttled Requests


Extra Cycles Core A


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A4

B1

A1

A2

A3

⎧｜｜⎩







Stall wait.




Saved Cycles Core BOldest


Throttled Requests


Extra Cycles Core A


A4B1

A1

A2

A3

Oldest ⎧｜｜⎩







A4

B1

A1

A2

A3

⎧｜｜⎩




Dynamically detect application A’s interference for application B and throttle down application A




Stall wait.




Saved Cycles Core BOldest


Throttled Requests


Extra Cycles Core A





•Evaluation

•Conclusion

9

Outline


10

Fairness via Source Throttling (FST)


•Runtime Unfairness Evaluation• Dynamically estimates the unfairness in the

memory system

10



•Runtime Unfairness Evaluation• Dynamically estimates the unfairness in the

memory system

•Dynamic Request Throttling• Adjusts how aggressively each core makes

requests to the shared resources

10



Runtime UnfairnessEvaluation

DynamicRequest Throttling

FST

TimeInterval 1 Interval 2 Interval 3





FST

｜ ⎨ ｜ ⎧⎩Slowdown Estimation






1- Estimating system unfairness

FST








1- Estimating system unfairness 2- Find app. with the highest slowdown (App-slowest)

FST








1- Estimating system unfairness 2- Find app. with the highest slowdown (App-slowest)3- Find app. causing most interference for App-slowest (App-interfering)

FST









FSTUnfairness Estimate

App-slowestApp-interfering









if (Unfairness Estimate >Target) {











if (Unfairness Estimate >Target) { 1-Throttle down App-interfering











if (Unfairness Estimate >Target) { 1-Throttle down App-interfering 2-Throttle up App-slowest}














12



13

SharedTi


Alone


Min{Slowdown i} over all applications i•Unfairness =

Estimating System Unfairness


•How can be estimated in shared mode?TiAlone

13

SharedTi


Alone






13

SharedTi


Alone



TiExcess

• is the number of extra cycles it takes application i to execute due to interference




13

SharedTi


Alone



TiExcess

• is the number of extra cycles it takes application i to execute due to interference

TiShared

=TiAlone

- TiExcess

•



14

Tracking Inter-Core Interference


Core 0 Core 1 Core 2 Core 3

Bank 0 Bank 1 Bank 2 Bank 7...

Memory Controller

Shared Cache

14





Memory Controller

Shared Cache

Three interference sources:

14





Memory Controller

Shared Cache

Three interference sources:1. Shared Cache

14





Memory Controller

Shared Cache

Three interference sources:1. Shared Cache2. DRAM bus and bank

14





Memory Controller

Shared Cache

Three interference sources:1. Shared Cache2. DRAM bus and bank3. DRAM row-buffers

14

Bank 2


Row


0 0 0 0

Interference per corebit vector

Core # 0 1 2 3



Memory Controller

Shared Cache

Three interference sources:1. Shared Cache2. DRAM bus and bank3. DRAM row-buffers

FST hardware

14

Bank 2


Row


Core 0 Core 1

15

Tracking DRAM Row-Buffer Interference


Bank 2Bank 0 Bank 1 Bank 7...

Core 0 Core 1

15



Row B

Row A

Bank 2Bank 0 Bank 1 Bank 7...

Core 0 Core 1

Row Aqueue of requests to bank 2

15



Row B

Row A

Bank 2

Row B

Bank 0 Bank 1 Bank 7...

Core 0 Core 1


Row Buffer:

15



Row B

Row A

Bank 2

Row B


Core 0 Core 1


FST additions

Row Buffer:

15



Row B

Row A

Bank 2

Row B


Core 0 Core 1

Row A


0 0Core # 0 1

queue of requests to bank 2

FST additions

Row Buffer:

15



Row B

Row A

Bank 2

Row B


Core 0 Core 1

Row A

Shadow Row Address Register(SRAR) Core 0 :


0 0Core # 0 1



FST additions

Row Buffer:

15



Row B

Row A

Bank 2

Row B


Core 0 Core 1

Row Hit

Row A



0 0Core # 0 1



FST additions

Row Buffer:

15



Row B

Row A

Bank 2

Row B


Core 0 Core 1

Row Hit

Row A

Row BShadow Row Address Register(SRAR) Core 0 :


0 0Core # 0 1



FST additions

Row Buffer:

15



Row B

Row A

Bank 2

Row B


Core 0 Core 1

Row ConflictRow A


Row A


0 0Core # 0 1



FST additions

Row Buffer:

15



Row B

Row A

Bank 2

Row B


Core 0 Core 1

Row ConflictRow A

Row BRow B


Row A


0 0Core # 0 1



FST additions

Row Buffer:

15



Row BRow A

Bank 2

Row B


Core 0 Core 1

Row A

Row Hit

Row BRow B


Row A


0 0Core # 0 1



FST additions

Row Buffer:

15



Row BRow A

Bank 2

Row B


Core 0 Core 1

Row ARow Conflict

Row B


Row A


0 0Core # 0 1



FST additions

Row Buffer:

15



Row BRow A

Bank 2

Row B


Core 0 Core 1

Row ARow Conflict

Row B


Row A

Interference inducedrow conflict


0 0Core # 0 1



FST additions

Row Buffer:

15



Row BRow A

Bank 2

Row B


Core 0 Core 1

Row ARow Conflict

Row B


Row A

Interference inducedrow conflict


0Core # 0 1

1



FST additions

Row Buffer:

15



0 0 0 0


Core # 0 1 2 3

FST hardwareCore 0 Core 1 Core 2 Core 3


Memory Controller

Shared Cache

16



0 0 0 0


Core # 0 1 2 3

0

0

0

0

Excess Cycles Counters per core



Memory Controller

Shared Cache

16

TiExcess

｜⎨｜⎧

⎩



0 0 0 0


Core # 0 1 2 3

0

0

0

0


TCycle Count



Memory Controller

Shared Cache

16

TiExcess

｜⎨｜⎧

⎩



0 0 0


Core # 0 1 2 3

0

0

0

0


1

TCycle Count



Memory Controller

Shared Cache

16

TiExcess

｜⎨｜⎧

⎩



0 0 0


Core # 0 1 2 3

0

0

0


1

Cycle Count T+2

2FST hardware



Memory Controller

Shared Cache

16

TiExcess

｜⎨｜⎧

⎩



0 0 0


Core # 0 1 2 3

0

0

0


1

Cycle Count T+2

2FST hardware

1



Memory Controller

Shared Cache

16

TiExcess

｜⎨｜⎧

⎩



0 0 0


Core # 0 1 2 3

0

0

0


1

Cycle Count T+2

2FST hardware

1

T+3

3

1



Memory Controller

Shared Cache

16

TiExcess

｜⎨｜⎧

⎩









17



18



• To identify App-interfering, for each core i

18



• To identify App-interfering, for each core i• FST separately tracks interference

caused by each core j ( j ! i )

18



0


Core # 0 1 2 3



0 0 0

18



0

0 0 0 -


Core # 0 1 2 3



0 0 - 0

0 - 0 0

- 0 0 00123

18



0

0 0 0 -


Core # 0 1 2 3



0 0 - 0

0 - 0 0

- 0 0 0

｜⎨｜⎧ ⎩

｜⎨｜⎧

⎩

Interfered with core

Interfering core

0123

18



Cnt 3Cnt 2Cnt 1Cnt 00

0 0 0 -


Core # 0 1 2 3




0 0 - 0

0 - 0 0

- 0 0 0

｜⎨｜⎧ ⎩

｜⎨｜⎧

⎩


Interfering core

0123

18




0 0 0 -


Core # 0 1 2 3-

Cnt 1,0

Cnt 2,0

Cnt 3,0




0 0 - 0

0 - 0 0

- 0 0 0

｜⎨｜⎧ ⎩

｜⎨｜⎧

⎩


Interfering core

Cnt 0,1

-

Cnt 2,1

Cnt 3,1

Cnt 0,2

Cnt 1,2

-

Cnt 3,2

Cnt 0,3

Cnt 1,3

Cnt 2,3

-

0123

18




0 0 0 -


Core # 0 1 2 3-

Cnt 1,0

Cnt 2,0

Cnt 3,0




0 0 - 0

0 - 0 0

- 0 0 0

｜⎨｜⎧ ⎩

｜⎨｜⎧

⎩


Interfering core

Cnt 0,1

-

Cnt 2,1

Cnt 3,1

Cnt 0,2

Cnt 1,2

-

Cnt 3,2

Cnt 0,3

Cnt 1,3

Cnt 2,3

-

1

0123

18




0 0 0 -


Core # 0 1 2 3-

Cnt 1,0

Cnt 2,0

Cnt 3,0




0 0 - 0

0 - 0 0

- 0 0 0

｜⎨｜⎧ ⎩

｜⎨｜⎧

⎩


Interfering core

Cnt 0,1

-

Cnt 2,1

Cnt 3,1

Cnt 0,2

Cnt 1,2

-

Cnt 3,2

Cnt 0,3

Cnt 1,3

Cnt 2,3

-

1core 2

interfered with

core 1

0123

18




0 0 0 -


Core # 0 1 2 3-

Cnt 1,0

Cnt 2,0

Cnt 3,0




0 0 - 0

0 - 0 0

- 0 0 0

｜⎨｜⎧ ⎩

｜⎨｜⎧

⎩


Interfering core

Cnt 0,1

-

Cnt 3,1

Cnt 0,2

Cnt 1,2

-

Cnt 3,2

Cnt 0,3

Cnt 1,3

Cnt 2,3

-

1core 2

interfered with

core 1

Cnt 2,1++

0123

18




0 0 0 -


Core # 0 1 2 3-

Cnt 1,0

Cnt 2,0

Cnt 3,0




0 0 - 0

0 - 0 0

- 0 0 0

｜⎨｜⎧ ⎩

｜⎨｜⎧

⎩


Interfering core

Cnt 0,1

-

Cnt 3,1

Cnt 0,2

Cnt 1,2

-

Cnt 3,2

Cnt 0,3

Cnt 1,3

Cnt 2,3

-

1core 2

interfered with

core 1

Cnt 2,1++

0123

App-slowest = 2

18




0 0 0 -


Core # 0 1 2 3-

Cnt 1,0

Cnt 2,0

Cnt 3,0




0 0 - 0

0 - 0 0

- 0 0 0

｜⎨｜⎧ ⎩

｜⎨｜⎧

⎩


Interfering core

Cnt 0,1

-

Cnt 3,1

Cnt 0,2

Cnt 1,2

-

Cnt 3,2

Cnt 0,3

Cnt 1,3

Cnt 2,3

-

1core 2

interfered with

core 1

Cnt 2,1++

0123

Row with largest count determines App-interfering

App-slowest = 2

18









19



20

Dynamic Request Throttling


• Goal: Adjust how aggressively each core makes requests to the shared resources

20




•Mechanisms:• Miss Status Holding Register (MSHR) quota

20




•Mechanisms:• Miss Status Holding Register (MSHR) quota• Controls the number of concurrent requests

accessing shared resources from each application

20






• Request injection frequency

20






• Request injection frequency• Controls how often memory requests are issued

to the last level cache from the MSHRs

20



• Throttling level assigned to each core determines both MSHR quota and request injection rate

21



• Throttling level assigned to each core determines both MSHR quota and request injection rate

Throttling level MSHR quota Request Injection Rate

100% 128 Every cycle50% 64 Every other cycle25% 32 Once every 4 cycles10% 12 Once every 10 cycles5% 6 Once every 20 cycles4% 5 Once every 25 cycles3% 3 Once every 30 cycles2% 2 Once every 50 cycles

Total # ofMSHRs: 128

21



Time

Runtime UnfairnessEvaluation Dynamic

Request Throttling


App-slowest

App-interfering

Throttling Levels

Core 0 Core 1 Core 3Interval i

Interval i + 1Interval i + 2

Core 0 Core 2

System software fairness goal: 1.4

22

FST at Work


TimeInterval i


Request Throttling


App-slowest

App-interfering

Throttling Levels

Core 0 Core 1 Core 350% 100% 10% 100%Interval i


Core 0 Core 2


22

FST at Work

Slowdown Estimation

｜ ⎨ ｜ ⎧⎩


TimeInterval i


Request Throttling


App-slowest

App-interfering

Throttling Levels



3

Core 2

Core 0

Core 0 Core 2


22

FST at Work

Slowdown Estimation

｜ ⎨ ｜ ⎧⎩


TimeInterval i


Request Throttling


App-slowest

App-interfering

Throttling Levels



3

Core 2

Core 0

Core 0 Core 2Throttle down Throttle up


22

FST at Work

Slowdown Estimation

｜ ⎨ ｜ ⎧⎩


TimeInterval i Interval i+1


Request Throttling


App-slowest

App-interfering

Throttling Levels

Core 0 Core 1 Core 350% 100% 10% 100%25% 100% 25% 100%

Interval iInterval i + 1Interval i + 2

3

Core 2

Core 0

Core 0 Core 2Throttle down Throttle up


22

FST at Work

Slowdown Estimation

｜ ⎨ ｜ ⎧⎩




Request Throttling


App-slowest

App-interfering

Throttling Levels

Core 0 Core 1 Core 350% 100% 10% 100%25% 100% 25% 100%


Core 0 Core 2

2.5

Core 2

Core 1


22

FST at Work

Slowdown Estimation

｜ ⎨ ｜ ⎧⎩




Request Throttling


App-slowest

App-interfering

Throttling Levels

Core 0 Core 1 Core 350% 100% 10% 100%25% 100% 25% 100%


Core 0 Core 2

2.5

Core 2

Core 1

Throttle down Throttle up


22

FST at Work

Slowdown Estimation

｜ ⎨ ｜ ⎧⎩


TimeInterval i Interval i+1 Interval i+2


Request Throttling


App-slowest

App-interfering

Throttling Levels

Core 0 Core 1 Core 350% 100% 10% 100%25% 100% 25% 100%25% 50% 50% 100%


Core 0 Core 2

2.5

Core 2

Core 1

Throttle down Throttle up


22

FST at Work

Slowdown Estimation

｜ ⎨ ｜ ⎧⎩


23

System Software Support


•Different fairness objectives can be configured by system software

23



•Different fairness objectives can be configured by system software• Estimated Unfairness > Target Unfairness

23




• Estimated Max Slowdown > Target Max Slowdown

23





• Estimated Slowdown(i) > Target Slowdown(i)

23






•Support for thread priorities

23






•Support for thread priorities• Weighted Slowdown(i) =

Estimated Slowdown(i) x Weight(i)

23



•Total storage cost required for 4 cores is ! 12KB

• FST does not require any structures or logic that are on the processor’s critical path

24

Hardware Cost





•Evaluation

•Conclusion

25

Outline


• x86 cycle accurate simulator

• Baseline processor configuration• Per-core• 4-wide issue, out-of-order, 256 entry ROB

• Shared (4-core system)• 128 MSHRs • 2 MB, 16-way L2 cache

• Main Memory• DDR3 1333 MHz• Latency of 15ns per command (tRP, tRCD, CL)• 8B wide core to memory bus

26

Evaluation Methodology


0

1

2

3

4

5

6

7

Syst

em U

nfai

rnes

s

No FairnessFair Cache Capacity (VPC)Parallelism-Aware Batch Scheduling+VPCFairness via Source Throttling (FST)

grom+a

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264

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64

lbm+o

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+gam

es+g

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afty

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ortex

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mgrid+

parse

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gcc0

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27

System Unfairness Results


0

1

2

3

4

5

6

7

Syst

em U

nfai

rnes

s


grom+a

rt+ast

ar+h

264

art+

games

+Gem

s+h2

64

lbm+o

mnet+

apsi+

vorte

x

art+

leslie

+gam

es+g

rom

art+

astar

+lesli

e+cr

afty

art+

milc+v

ortex

+calc

ulix

lucas+

ammp+

xalan

c+gro

m

lbm+G

ems+

astar

+mes

a

mgrid+

parse

r+so

plex+

perlb

gcc0

6+xa

lanc+

lbm+c

actu

s

gmea

n

44.4%

27



0

1

2

3

4

5

6

7

Syst

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nfai

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s


grom+a

rt+ast

ar+h

264

art+

games

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s+h2

64

lbm+o

mnet+

apsi+

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x

art+

leslie

+gam

es+g

rom

art+

astar

+lesli

e+cr

afty

art+

milc+v

ortex

+calc

ulix

lucas+

ammp+

xalan

c+gro

m

lbm+G

ems+

astar

+mes

a

mgrid+

parse

r+so

plex+

perlb

gcc0

6+xa

lanc+

lbm+c

actu

s

gmea

n

44.4%

36%

27



0

0.4

0.8

1.2

1.6

2

Syst

em P

erf.

Nor

mal

ized

to

No

Fair

ness Fair Cache Capacity (VPC)

Parallelism-Aware Batch Scheduling + VPCFairness via Source Throttling (FST)

gmea

n

grom+a

rt+ast

ar+h

264

art+

games

+Gem

s+h2

64

lbm+o

mnet+

apsi+

vorte

x

art+

leslie

+gam

es+g

rom

art+

astar

+lesli

e+cr

afty

art+

milc+v

ortex

+calc

ulix

lucas+

ammp+

xalan

c+gro

m

lbm+G

ems+

astar

+mes

a

mgrid+

parse

r+so

plex+

perlb

gcc0

6+xa

lanc+

lbm+c

actu

s

28

System Performance Results


0

0.4

0.8

1.2

1.6

2

Syst

em P

erf.

Nor

mal

ized

to

No

Fair



gmea

n

25.6%

grom+a

rt+ast

ar+h

264

art+

games

+Gem

s+h2

64

lbm+o

mnet+

apsi+

vorte

x

art+

leslie

+gam

es+g

rom

art+

astar

+lesli

e+cr

afty

art+

milc+v

ortex

+calc

ulix

lucas+

ammp+

xalan

c+gro

m

lbm+G

ems+

astar

+mes

a

mgrid+

parse

r+so

plex+

perlb

gcc0

6+xa

lanc+

lbm+c

actu

s

28



0

0.4

0.8

1.2

1.6

2

Syst

em P

erf.

Nor

mal

ized

to

No

Fair



gmea

n

25.6%

14%

grom+a

rt+ast

ar+h

264

art+

games

+Gem

s+h2

64

lbm+o

mnet+

apsi+

vorte

x

art+

leslie

+gam

es+g

rom

art+

astar

+lesli

e+cr

afty

art+

milc+v

ortex

+calc

ulix

lucas+

ammp+

xalan

c+gro

m

lbm+G

ems+

astar

+mes

a

mgrid+

parse

r+so

plex+

perlb

gcc0

6+xa

lanc+

lbm+c

actu

s

28



• Fairness via Source Throttling (FST) is a new fair and high-performance shared resource management approach for CMPs

• Dynamically monitors unfairness and throttles down sources of interfering memory requests

• Eliminates the need for and complexity of multiple per-resource fairness techniques

• Improves both system fairness and performance

• Incorporates thread weights and enables different fairness objectives

29

Conclusion


Fairness via Source Throttling:

A configurable and high-performance fairness substrate for multi-core memory systems

Eiman Ebrahimi*

Chang Joo Lee*

Onur Mutlu‡

Yale N. Patt*

* HPS Research Group

The University of Texas at Austin

‡ Computer Architecture Laboratory

Carnegie Mellon University


Fairness via Source Throttlingusers.ece.cmu.edu/~omutlu/pub/ebrahimi_asplos10_talk.pdfB1 A1 A2 A3...

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Transcript of Fairness via Source Throttlingusers.ece.cmu.edu/~omutlu/pub/ebrahimi_asplos10_talk.pdfB1 A1 A2 A3...