FABRICATION AND DEVICE CHARACTERIZATION OF …

ABSTRACT

HAN, Sungkee. Fabrication and Device Characterization of Alternative Gate Stacks

Using the Non Self-Aligned Gate Process (Under the direction of Carlton M. Osburn)

In order to improve MOSFET transistor performance, aggressive scaling of

devices has continued. As lateral device dimensions continue to scale down, gate oxide

thicknesses must also be scaled down. According to the 2001 International Technology

Roadmap for Semiconductor (ITRS) for sub-micron technology, an equivalent oxide

thickness (EOT) less than 1.0 nm is required for high performance devices. However, at

this thickness SiO2 has reached its scaling limit due to the high tunneling current,

especially in low power devcies. The use of high K dielectrics may circumvent this

impediment since physically thicker dielectrics can be used to reduce gate leakage while

maintaining the same level of inversion charge. In this study, we used an alternative, non

self-aligned gate process to fabricate both NMOS and PMOS devices with a variety of

high K gate dielectric and metal gate electrode materials; finally their electrical properties

were characterized.

Most high K gate dielectric and gate metal candidates have limited thermal

stability. As a result, conventional transistor fabrication process flows cannot be used.

Here we developed a non self-aligned gate process, which reverses the order of the

junction and the gate stack formation steps and thus allow the use of dielectrics and

electrode materials that are not able to sustain high junction activation temperatures. A

new mask set, ERC-6, was designed to facilitate the non-self aligned gate process.

Wet and dry etching process for alternative high K gate dielectrics (HfO2, ZrO2,

La2O3, Y2O3) and metal gate electrodes (Pt, Ru, RuO2, Ta, TaN) were studied. Wet

etching of Pt and TaN required periodic re-baking of the photoresist to re-establish

adhesion to the substrate. Reactive ion etch (RIE) processes were developed for RuO2,

Ru/W, Ta/W gate electrodes. A mixture of oxygen and fluorine plasma was effective in

patterning RuO2 electrodes. However, for Ru gate electrodes, etch rates only up to 6.7

nm/min could be obtained even with the optimized addition of a few percent Cl2 to O2;

this etch rate was considerably slower than that of photoresist. Rather than using a hard

mask to etch the Ru gate, a laminated gate composed of a thin Ru layer (3 nm) covered

with a thicker W film (100 nm) was successfully dry etched. The etching characteristics

of various high K gate dielectrics depended not only on the materials, but also on how

they were deposited, including the substrate pretreatment and post deposition anneal

conditions. For instance, jet vapor deposited (JVD) HfO2 would etch in BOE (10% HF),

while other HfO2 films required dry etching. Similarly, rapid thermal CVD (RTCVD)

ZrO2 required dry etching while other ZrO2 films could be wet etched in BOE.

The electrical properties, including capacitance vs. voltage (C-V), gate leakage

current (Ig-Vg), drain current vs. gate voltage (Id-Vd) and drain current vs. drain voltage

(Id-Vd) characteristics, were measured on devices having a variety of high K gate

dielectrics and gate metal electrodes. These electrical measurements were used to

compare not only the different higk K dielectrics but also the different deposition systems.

First, oxide control devices were fabricated to produce baseline data and to verify the non

self-aligned process. The gate leakage current and channel mobility of the 1 nm thick

control oxides were in good agreement with previously reported values. Reasonably

good C-V characteristics were observed for HfO2 (JVD) and ZrO2 (JVD and RTCVD)

except for the devices having TaN gate electrodes. Due to over-etching, a large die-to-

die variability was observed with TaN gated capacitors. The measured EOT values for

HfO2 and ZrO2 films ranged from 1.28 to 2.25 nm and 1.86 to 2.62 nm, respectively. The

RTCVD HfO2 and JVD ZrO2 had the same gate leakage as reported values, while slightly

higher leakages were observed with JVD HfO2 and RTCVD ZrO2. Nevertheless, most of

the devices having HfO2 or ZrO2 dielectrics met the low operating power gate leakage

specifications (0.81 A/cm2 at 1.0 V) for the 100 nm and 70 nm ITRS technology nodes in

our experimental splits. Devices made with physical vapor deposited (PVD) HfO2 had

the thinnest EOT (0.9 nm with Ru/W gate and 1.2 nm with poly-silicon gate).

The effect of forming gas annealing, 10% H2 in 90 % N2, on PVD HfO2 was

studied. We found that H2 annealing showed significant enhancements in drive current

and channel mobility. But even with H2 annealing, HfO2 still had lower mobility than

high quality SiO2. In order to further enhance its interface quality, D2 forming gas

annealing, 10% H2 in 90 % N2, was performed. Even though the detailed mechanism has

not been revealed, D2 annealing gave a greater increase in device current and mobility

than H2.

The gate leakage characteristics of HfO2 and Hf silicate with poly-silicon and

metal gates were measured and compared. For both HfO2 and Hf silicate, large device-

to-device gate leakage variations were observed with poly-silicon gate electrodes. In

contrast to the poly-silicon gate devices, relatively small variations were observed with

metal gates, where the gate leakages scaled with area. The statistical variations of gate

leakage for poly-silicon and metal electrodes clearly showed that HfO2 and Hf silicate

degrade during the poly-silicon process. Experiments were designed with Hf silicate

dielectrics to separately examine the thermal degradation during the high temperature

poly-silicon activation cycle and chemical reaction during and after the poly-silicon CVD

process. Al gated Hf silicate devices revealed no significant degradation even with pre-

metal annealing temperatures up to 1000 ºC. Devices having different sources of poly-

silicon gates (LPCVD poly-silicon, LPCVD amorphous silicon, and sputter deposit

amorphous silicon) and metal gates were compared to examine the chemical reactions

with the poly-silicon. Regardless of the depositions method, all devices with poly-silicon

gates showed considerable degradation. Even though the high thermal budget itself had a

negligible effect, the combination of high temperature annealing and the presence of

silicon gates degraded Hf-based dielectrics.

The gate leakage of Hf silicate measured as a function of composition. The leakage

current showed a minimum at an intermediate silicate composition (~ 50 %), verifying

theoretical predictions. To retard additional oxidation during processing, nitridaiton was

performed at the bottom interface or on the surface of Hf silicate dielectrics. Both of

these nitridation steps influenced the final EOT and charge in the Hf silicate. Surface

nitridiaion resulted in 10 % lower EOT than un-nitrided films, while interfacial nitridaion

gave more effective reduction (~2 nm) in EOT. Interfacial and surface nitridation

removed positive charges. On the other hand, surface nitridation alone introduced

positive charges into the Hf silicate dielectrics.

FABRICATION AND DEVICE CHARACTERIZATION OF ALTERNATIVE GATE STACKS USING THE NON SELF-ALIGNED

GATE PROCESS

by SUNGKEE HAN

A dissertation submitted to the Graduate Faculty of North Carolina State University

in partial fulfillment of the requirements for the Degree of

Doctor of Philosophy

MATERIALS SCIENCE AND ENGINEERING

Raleigh, NC

April 2003

APPROVED BY:

____________________________ ____________________________

Dr. Carlton M. Osburn Dr. Jon-Paul Maria Co-chair of Advisory Committee Co-chair of Advisory Committee

____________________________ ____________________________

Dr. Gerald Lucovsky Dr. George Rozgonyi

BIOGRAPHY

Sungkee Han was born on April 24, 1971 in Seoul Korea. When he was 18, his

family moved to New York City. He attended John Bowne High School in Flushing,

New York and graduated in 1991. In that same year, he entered Rensselaer Polytechnic

Institute, Troy, New York. In 1995, he completed his bachelor of science in Materials

Science and Engineering and began graduate school at North Carolina State University in

Raleigh, North Carolina. In May 1998, he received his Master of Science degree in

Materials Science and Engineering. In June of 1998, he enrolled in the Materials Science

and Engineering Ph.D. program. During the course of his research under the direction of

Dr. Carlton Osburn, he studied new device integration strategies for high K gate

dielectric and new gate electrode materials that meet the 70 and 50 nm technology nodes

at the SRC/SEMATECH Center for Front End Processes. In August 2003, he received

his Doctor of Philosophy degree in Materials Science and Enginerring.

ii

ACKNOWLEDGMENTS

I would like to express my sincere appreciation to my advisory committee

members, Dr. Carlton Osburn, Dr. Jon-Paul Maria, Dr. Gerald Lucovsky and Dr. George

Rozgonyi for providing guidance in the research and review of this thesis. I owe special

thanks to my advisor, Dr. Carlton Osburn. Without his guidance and financial support

this work would not have been possible. I also thank Dr. Jon-Paul Maria who serves as

co-chairman of my advisory committee.

My sincere thanks are extended to members of the North Carolina State

University Microelectronics Laboratory. In particular, my sincere thanks go to J.

O’Sullivan, Harold Morton and Dr. D.Ginger Yu who provided invaluable assistance in

the clean room.

I am grateful to current and former member of Dr.Osburn’s group, Kam Y. Lee,

Indranil De and Indong Kim who have been excellent friends and colleagues throughout

the years.

Sufficient thanks cannot be given to my parents, Moo Woo and Yon Ja Han, for

their love and support. Special thank also goes to my one and only brother and his wife,

Sung Dal Han and Yon Hee Han. Without their support, it would have been impossible

to succeed in my study.

Last, but not least, I would like to thank to all of my friends, especially Se-Hwan

Chung, Hoon Jae Yim, Ha Joon Hwang, Seung Wook Moon, Sung Joon Doh, Hyung

Min Bae, Sung Won Ha, Dong Wook Jung, Joon Goo Hong, Jae Hoon Lee, You Seok

iii

Suh, Ji Sang Hwang, Jin Ho Lee and Hyung Jik Lee, for their encouragement and support

during my graduate study at NCSU.

iv

TABLE OF CONTENTS

List of Tables…………………………………………………………………………....vii List of Figures………………………………………………………………………….viii Chapter 1: Introduction 1.1. Scaling of Gate Oxide………………………………………………….……………1 1.2. Alternative High Dielectric Constant Gate Insulator Materials……………………..4 1.3. Metal Gate Candidates…………………………………………………………….....7 1.4. Outline of the Dissertation………………………………………………………...…9 1.5. Reference……………………………………………...……………………………11 Chapter 2: Device Fabrication Incorporating Alternative Gate Stack 2.1. Processing Issues Related to MOS Device Fabrication and Performance………….23 2.2. Replacement Gate Process………………………………………………………….24 2.3. Non-self Aligned Gate Process……………………………………………………..25 2.4. ERC 6 Mask Set…………………………………………………………………….26 2.5. Device Fabrication using the Non-self Aligned Gate Process……………………...28 2.6. Gate Dielectrics and Gate Metal Electrodes Deposition Methods………………….30 2.7. Reference……………………………………………………………………………33 Chapter 3: Etching of High K Gate Dielectrics and Gate Metal Candidates 3.1. Introduction…………………………………………………………….…………...38 3.2. Experimental Procedure…………………………………………………………….39 3.3. Results and Discussion……………………………………………………………...41 3.3.1. Metal Gate Electrode Etching…………………………………………….41 3.3.1.1. Platinum………………………………………………………...41 3.3.1.2. Tantalum Nitride………………………………………………..42 3.3.1.3. Ruthenium Oxide……………………………………………….43 3.3.1.4. Ruthenium, Tungsten, and Tantalum……………………… …..44 3.3.2. High K Dielectric Etching………………………………………………..45 3.3.3. Device Characteristics……………………………………………………46 3.4. Summary and Conclusion…………………………………………………………..47 3.5. Reference…………………………………………………………………………...49 Chapter 4: Device Characterizations of Alternative Gate Stacks Using the Non-self Aligned Process 4.1. Introduction…………………………………………………………………………59 4.2. Experimental Procedure…………………………………………………………….59 4.3. Results and Discussion……………………………………………………………...62

v

4.3.1. Device Characteristics of Control Oxide………………………………….62

4.3.2. Capacitance Voltage (C-V) and Gate Leakage (Ig-Vg) Characteristics of HfO2 and ZrO2………………………………………………………….62

4.4.3. Device Characteristics…………………………………………………….62 4.4.3. Effect of Forming Gas Anneal: H2 vs. D2…………………………………66 4.4. Conclusions………………………………………………………………………….67 4.5. Reference……………………………………………………………………………69 Chapter 5: Gate Leakage Current Behavior of HfO2 and Hf Silicate with Poly-silicon and Metal Gate Electrode 5.1. Introduction…………………………………………………………………..…….104 5.2. Experimental……………………………………………………………………….105 5.3. Results…………………………………………………………………….………..107 5.3.1. Variability of Gate Leakage Current with Poly-silicon Gate…………….107 5.3.2. Compatibility of Poly-silicon Gate on Hf Silicate……………………….109 5.4. Summary and Conclusion………………………………………………………….111 5.5. Reference…………………………………………………………………………..113 Chapter 6: Gate Leakage Characteristics of Hf Silicate Alloys and Effect of Nitridation 6.1. Introduction………………………………..……………………………………….129 6.2. Experimental……………………………………………………………………….131 6.3. Results………………………………………………………………….…………..132 6.3.1. Gate Leakage of Hf Silicate Alloys……………………………………...132 6.3.2. Effect of Nitridation……………………………………………………...132 6.4. Conclusion…………………………………………………………………………134 6.5. Reference…………………………………………………………………………..136 Chapter 7: Summary and Conclusion 7.1. Non-self Aligned Gate Process and ERC 6 Mask Set……………………………..151 7.2. Etching of High K Gate Dielectrics and Gate Metal Electrodes…………………..152 7.3. Device Characterization of Alternative Gate Stacks Using the Non-self Aligned Gate Process………………………………………………………………153 7.4. Gate Leakage Current Behavior of HfO2 and Hf Silicate with Poly-silicon and Metal Gate Electrode…………………………………………………………..154 7.5. Gate Leakage Characteristics of Hf Silicate and Effect of Nitridation…………….155 7.6. Future Work………………………………………………………………………..155 Appendix A…………………………………………………………………………….157 Appendix B…………………………………………………………………………….164 Appendix C…………………………………………………………………………….173

vi

LIST OF TABLES

Table 1.1. Key properties of high K dielectric candidates…………………………..6 Table 2.1. Summary of structures in ERC 6 mask set……………………………...27 Table 2.2. Matrix of high K dielectrics and gate electrode materials………………28

Table 2.3. High K dielectrics and metal gate electrodes deposition methods

and their deposition condition…………………………………………..31

Table 3.1. Deposition methods and conditions for high K dielectric and gate electrodes candidates…………………………………………..40

Table 3.2. Etch rate, resistivity and their corresponding nitrogen content…………43 Table 3.3. Optimized etching recipes for metal gate electrode candidates…………45 Table 3.4. Etch process and etch rate for high K gate dielectrics candidates………46 Table 4.1. Deposition sources and their deposition methods for high K

Dielectric………………………………………………………………...60 Table 4.2. Deposition sources and their deposition methods for gate

Electrodes………………………………………………………………..61 Table 4.3. Equivalent oxide thickness of each dielectrics (the values

extracted from C-V measurements)……………………………………..63 Table 4.4. Summary of peak mobility and universal mobility scattering

parameters of before and after D2 and H2 forming gas annealing (substrate doping = 3x1018/cm3)………………………………………...67

Table 5.1. HfO2 and Hf silicate deposition methods and their deposition

condition……………………………………………………………….106

vii

LIST OF FIGURES

Figure 1.1. Measured and simulated gate leakage currents for SiO2 dielectrics…..…21 Figure 1.2. Conduction and valance band calculations for high K gate

dielectric candidate materials………………………………………….…21 Figure 1.3. Energy level diagram of (a) midgap metal gates and (b) dual metal

Gate………………………………………………………………………22 Figure 1.4. Work function of metal gate candidates…………………………………22 Figure 2.1. Schematic illustration of replacement gate process: a) conventional device fabrication using sacrificial gate oxide; b) oxide deposition and CMP planarization etch back; c) etch out sacrificial gate stack; d) deposit new gate stack and pattern gate electrode……….……..35 Figure 2.2. Non-self aligned gate process chip layout (ERC6)………………………36 Figure 2.3. Schematic illustration of non-self aligned gate process: (a) grow and pattern 1000 Å thick oxide and form junction; (b) deposit LPCVD oxide over diffusions and pattern gate and contact regions; (c) deposit gate dielectric and electrode; (d) pattern and etch gate electrode/dielectric and deposit and pattern contact metal…….37 Figure 3.1. AES analysis of: a) as deposited Pt film; (b) Pt film after standard

descum (300 Watts, 1 min of O2 Plasma); (c) Pt film after Ar+ ion milling (80 Watts, 20 sccm at 60 mtorr for 3 minutes)…………….…….52

Figure 3.2 XPS analysis of : a) TaN film on 4 inch wafer (low nitrogen

concentration); and b) TaN film on 6 inch wafer (high nitrogen concentration……………………………………………………………..53

Figure 3.3. The cross-section TEM view of the transistor with SiO2/TaN gate stack: (a) overall view, (b) magnified TaN left edge view and (c) magnified TaN right edge view………………………………………54 Figure 3.4. Etch rate of RuO2 film in O2/CHF3 plasma as a function of

CHF3/(O2+CHF3) ratio…………………………………………...………55 Figure 3.5. Etch rate of Ru film in O2/Cl2 plasma as a function of Cl2/(O2+Cl2)

ratio………………………………………………………………………55

viii

Figure 3.6. a) SEM micrograph Ru/W film etched in O2/Cl2 (20 sccm/1 sccm),

at 40 mtorr, 150 Watts and b) SEM micrograph Ru/W film etched in SF6/O2 (18 sccm/2 sccm), at 40 mtorr, 150 Watts…………………….56

Figure 3.7. a) NMOS subthreshold characteristics of MBE La2O3 with Ta/W gate and b) PMOS ID-VG Characteristics of PVD HfO2 with Ru/W gate……………………………………………………………………….57

Figure 3.8. a). Id-Vd characteristics of La2O3-TaN NMOS device and b) Id-Vd

characteristics of HfO2 (JVD)-Pt PMOS device…………………………58 Figure 4.1. High-frequency C-V characteristics of (a) NMOS capacitance and

(b) PMOS capacitors……………………………………………….…….72 Figure 4.2. NMOS Ig-Vg characteristic of control oxide (EOT = 1.06 nm) from

100 µm x 100 µm capacitor……………………………………….……..73 Figure 4.3. NMOS channel mobility of control oxide (Nif = 4.8 x1010/cm2, HxL

= 29.1 Å2)………………………………………………………………..74 Figure 4.4. C-V characteristics of JVD HfO2. Al samples received 600˚C 20min

FG post-deposition anneal, while Pt samples got 600˚C, 20min N2 annealing…………………………………………………………………75

Figure 4.5. C-V curves of ZrO2 with different metal gates. RTCVD samples

received, 900°C, 30sec N2 annealing while JVD samples got 550°C, 20min FG post-deposition annealing……………………………….……76

Figure 4.6. Gate leakage characteristics of HfO2 with different gate electrodes…….77 Figure 4.7. Gate leakage characteristics of ZrO2 with different gate electrodes……..78 Figure 4.8. C-V characteristics of PVD HfO2 with poly-silicon (NMOS) and Ru/W (PMOS) gate electrodes…………………………………………..79 Figure 4.9. Gate leakage characteristics of PVD HfO2 with (a) poly-silicon gates (NMOS) and (b) Ru/W (PMOS) gates…………………….………80 Figure 4.10. Subthreshold characteristics of (a) NMOS JVD and RTCVD HfO2 and (b) PMOS JVD HfO2 devices…………………………….…………81 Figure 4.11. Subthreshold characteristics of (a) NMOS JVD and RTCVD ZrO2 and (b) PMOS JVD ZrO2 devices……………………………………….82

ix

Figure 4.12. Subthreshold characteristics of (a) NMOS PVD HfO2 with poly-silicon and (b) PMOS PVD HfO2 with Ru/W gate electrodes….….83 Figure 4.13. Subthershold characteristics of La2O3 NMOS device with TaN gate electrode…………………………………………………….…84 Figure 4.14. Id-Vd characteristics of JVD HfO2 with Al gated device………………...85 Figure 4.15. Id-Vd characteristics of RTCVD HfO2 with poly-silicon gated devices…………………………………………………………………...86 Figure 4.16. Id-Vd characteristics of JVD ZrO2 with TaN gated device……………….87 Figure 4.17. Id-Vd characteristics of JVD ZrO2 Al gated NMOS device………………88 Figure 4.18. Id-Vd characteristics of MBE La2O3 with TaN gated NMOS device…….89 Figure 4.19. Id-Vd characteristics of JVD HfO2 Pt gated PMOS device………………90 Figure 4.20. Id-Vd characteristics of JVD ZrO2 with Pt gated PMOS device………….91 Figure 4.21. Extracted NMOS mobility (JVD and RTCVD HfO2, JVD and RTCVD ZrO2, and MBE La2O3 devcies)………………………..………92 Figure 4.22. Extracted NMOS mobility of PVD HfO2 with poly-silicon gate…….….93 Figure 4.23. Extracted PMOS mobility (JVD HfO2 and JVD ZrO2)………………….94 Figure 4.24. Extracted PMOS mobility of PVD HfO2 with poly-silicon gate….……..95 Figure 4.25. Gate leakage characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after H2 annealing……………………….……………..96 Figure 4.26. C-V characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after H2 annealing……………………………………………97 Figure 4.27. Id-Vg characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after H2 annealing……………………………………………98 Figure 4.28. Mobility characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after H2 annealing…………………………..………………..99 Figure 4.29. Gate leakage characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after D2 annealing…………………………………….100

x

Figure 4.30. C-V characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after D2 annealing………………………………….……….101 Figure 4.31. Id-Vg characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after D2 annealing. Id-Vg characteristics with H2 annealing are also shown to compare with D2 annealing………………102 Figure 4.32. MOSFET mobility characteristics of HfO2 (1.2 nm) with poly-silicon gates, before and after D2 annealing. Mobility characteristics with H2 annealing are also shown to compare with D2 annealing……………………………………………………….103 Figure 5.1. Gate leakage characteristics of (a) PVD HfO2 with LPCVD poly-silicon gate electrode deposited at 550 ºC and (b) MOCVD HfO2 with LPCVD poly-silicon gate electrode deposited at 650 ºC…...118 Figure 5.2. (a) PMOS gate leakage characteristics of PVD HfO2 with Ru/W gate electrode and (b) NMOS gate leakage characteristics of JVD HfO2 with Al gate electrode………………………………..…..120 Figure 5.3. Gate leakage characteristics of MOCVD Hf silicate with

(a) LPCVD poly-silicon gate electrodes deposited at 650 ºC and (b) Al metal gate electrodes………………………………………….…122

Figure 5.4. Histogram representations of gate leakage variability for both poly-silicon and metal gate electrodes………………………………….123 Figure 5.5. PVD HfO2 gate leakage characteristics of before and after breakdown..124 Figure 5.6. C-V Characteristics of Hf silicate capacitors with four different

temperatures (600 ºC, 800 ºC, 900 ºC, and 1000 ºC)………………..….125 Figure 5.7. EOT variations with four different annealing temperature (600 ºC, 800 ºC, 900 ºC, and 1000 ºC)…………………………………126 Figure 5.8. C-V characteristics of (a) three different silicon gates (LPCVD

poly-silicon, LPCVD amorphous silicon, and PVD amorphous silicon) and (b) two different (Al and TaSixNy) metal gates……………127

Figure 5.9. Gate leakage characteristics of (a) LPCVD amorphous-silicon,

(c) LPCVD poly-silicon, (c) PVD amorphous silicon, and (d) metal gate electrodes………………………………………………..128

Figure 6.1. Schematic illustration of (ZrO2)•(SiO2) phase separation after

xi

xii

high temperature annealing under oxidizing conditions………………..143 Figure 6.2. Gate leakage current (corrected for 1 nm EOT) at -1 V gate bias

for different silicate composition……………………………………….144 Figure 6.3. (a) C-V characteristics of Hf silicate/poly-silicon gate stack with

different nitridation conditions and (b) C-V characteristics of Hf silicate/Al gate stack with different nitridation conditions……………..145

Figure 6.4. (a) Interfacial and surface nitridation effect on EOT (Hf silicate

with Al gate) and (b) Interfacial and surface nitridation effect on flat band voltages (Hf silicate with Al gate)…………………………...147

Figure 6.5. (a) Interfacial and surface nitridation effect on EOT (Hf silicate with poly-silicon gate) and (b) Interfacial and surface nitridation effect on flat band volgates (Hf silicate with poly-silicon gate)…….....149

1

CHAPTER 1

Introduction

1.1. Scaling of Gate Oxide

SiO2 has served as a nearly perfect gate dielectric for integrated circuit (IC)

applications for more than 40 years. The primary reasons for this are that SiO2 (a)

passivates the Si surface with a low surface-state density ~1-3 x 1010 (eV-cm2)-1; (b)

serves as a patternable mask, forming a amorphous layer, for the localized diffusion of

dopants into Si for p-n junction fabrication; (c) is an insulator with a large energy gap (~9

eV) and very few trap states. In order to meet the demands for improved transistor

performance (e.g. improving circuit speed, reducing power and increasing packing

density) the microelectronics revolution has continued, and IC density is quadrupling

every three years [1-3]. Since the scaling of minimum feature sizes in MOSFETs has

been the major driving for this revolution, gate oxide thickness must also be

approximately linearly scaled down with channel length to maintain the same amount of

gate control over the channel [4-6]. According to the 2002 International Technology

Roadmap for Semiconductor (ITRS) [7] an equivalent oxide thickness (EOT) less than

1.0 nm is needed for a high performance microprocessor (MPU) for sub 100 nm

Technology node. However, the scaling of conventional SiO2 gate dielectric into the sub

100 nm regimes aggravates serious problems.

It is very unlikely that SiO2 can be scaled down much below 1 nm for use in MOS

transistors. Muller et al. studied very thin (7-15 Å) SiO2 layers on Si by energy loss

2

spectroscopy (EELS), and they revealed that the full band gap of SiO2 was obtained for

two monolayers of SiO2 [8]. Since the thickness of each SiO2 monolayer is about 3.5-

4.0 Å, this will set a physical limit of SiO2 of 7-8 Å. Aside from its physical limitation,

there is a practical limit for scaling down of the SiO2 thickness. Even though transistors

with 13-15 Å thick gate oxide are still usable for high performance applications, they

show high gate leakage current density (1-10 A/cm2) and may not be suitable for low

power applications [9-10]. According to the Timp et al. SiO2 gate dielectrics thinner than

10-12 Å result in no improvement in transistor drive current [11-13]. Yu et al. also

reported similar results [14].

High gate tunneling current is a major impediment to use the SiO2 as a gate

dielectric in scaled MOSFETs. As the oxide thickness scales down below 1.5 nm, the

direct tunneling gate-to-channel leakage current for SiO2 increases exponentially with

decreasing oxide thickness [15-17]. Figure 1.1 shows experimental gate oxide tunneling

currents for various oxide thicknesses from 3.5 nm to 1.4 nm, over a voltage range where

direct tunneling dominates. When the gate leakage current becomes equal to the off-state

source to drain sub-threshold leakage, the SiO2 thickness limit will be reached [16]. As

shown in the Figure 1.1, the SiO2 gate dielectric thickness limit occurs at around 1.6 nm

for devices with 100 nm gate length designed for 1.0V operation [15-17].

The use of thinner oxide also aggravates quantum mechanical carrier quantization

[18-20] and poly-silicon depletion effects [21]. Due to an ultra thin oxide and large

substrate doping density in scaled-down MOSFETs, a large electric field is applied to the

oxide/silicon interface that can cause a significant quantization of the carriers

perpendicular to the interface. There are two major aspects of quantum mechanical

3

carrier quantization: (i) since the surface charges are located in localized energy levels

above the edge of conduction band, additional band bending is required for the same

amount of the inversion charge and (ii) the charge distribution is peaked further from the

surface than classical theory would predict [22]. Due to the formation of a depletion

layer near the polysilicon gate/oxide interface, a significant decrease in gate capacitance

in inversion has been observed [21]. Lower polysilicon doping density, thinner gate

oxide and high substrate doping results in an increase the polysilicon depletion effect.

Both quantum mechanical quantization and polysilicon depletion effectively increase the

separation of the gate and the inversion charge. This results in reduced gate control of

channel inversion charge and can be interpreted as an increase in oxide thickness [23].

Dopant diffusion through the thin gate oxide, especially boron diffusion out of p+

polysilicon gate, is another problem in scaled MOSFETs. Boron penetration is enhanced

when the gate oxide is scaled down [24]. In order to minimize gate dopant penetration

through the gate oxide, the thermal cycle following the polysilicon implantation needs to

be minimized.

To overcome the problems with ultra thin SiO2, significant research has been

done on a nitride/oxide dual layer. Since the nitride/oxide dual layer has higher dielectric

constant than SiO2, physically thicker films can be used to prevent high gate leakage

current [25-27]. In addition, incorporation of N into SiO2 drastically reduces boron

penetration, and a one monolayer of N (~7x1014/cm2) near the Si channel interface

improves device performance [28-30]. In spite of this encouraging result, the

oxide/nitride stack can only provide a near term solution for CMOS transistor where the

EOT is in the 1.0-1.5 nm regime. For the sub 100 nm technology node (EOT less than

4

1.0 nm), using an oxide/nitride stack is not beneficial since its high gate leakage and high

interface trap density most likely will degrade device performance [31].

1.2. Alternative High Dielectric Constant Gate Insulator Materials

Higher dielectric constant (K) gate insulators may circumvent the problems

facing conventional SiO2 gate insulators. With these alternative materials, physically

thicker dielectrics can be used while maintaining the same level of inversion charge since

the electric field is inversely related to the thickness of the dielectric layer. This reduces

the probability of electrons and holes tunneling through the dielectric. Provided that band

offsets are sufficiently large, the use of thicker dielectric layers results in less gate

leakage current, thereby permitting further scaling of the dielectric thickness.

1.2.1. Materials Properties Requirements

In order to be used as a gate insulator, the alternative high K gate dielectric must

meet a set of criteria, such as: appropriate barrier height, high dielectric constant, ability

to form a stable interface with Si as well as the gate electrode at thermal stability, and has

a good dielectric-silicon interface (low interface state densities, low fixed charge and

smooth surface) to achieve high channel mobility.

If the high K dielectric system is thermodynamically unstable on Si, it will react

with Si and form an interfacial layer. In order to minimize this reaction, high K materials

may need an additional barrier layer between the dielectric and the Si substrate. Usually

the barrier layer is much lower K than the alternative dielectric and needs to be

eliminated for the most aggressive scaling. If the gate structure contains several

5

dielectrics in series, the lowest capacitance layer will dominate the overall capacitance

and set an oxide thickness-scaling limit. Furthermore, formation of a barrier layer

increases the process complexity since it requires deposition or growth of an additional

ultra thin dielectric. Due to this reason, it is desirable to have a high K dielectric that

will be thermodynamically stable on Si.

It is essential that dielectric with a higher permittivity than SiO2 be used. But at

the same time, the permittivity must be balanced with the band offset, which is the barrier

height for tunneling process. Key properties (dielectric constants, band gaps and band

offsets) of candidate materials are summarized in Table 1.1 and Figure 1.2 [32,33]. In

order to have low gate leakage current, it is desirable to use a high K gate dielectric with

large band offset. It is most likely that those oxide candidates with band offset less than

1.0 eV will not be used in gate dielectric applications.

1.2.2. High Dielectric Constant Gate Insulator Candidates Materials

Substantial research has been done on materials systems such as Ta2O5 [34-36],

TiO2/Si3N4 [37] TiO2 [38], and SrTiO3 [39]. Even though these materials have dielectric

constant values ranging from 10 to 80, most of these oxide systems are not thermally

stable in direct contact with Si [40,41]. Al2O3 has a high band gap (8.7 eV) and it is

stable on Si at high temperature. Due to this reason, it has been considered one of the

primary candidates and has been studied extensively [42-44]. But Al2O3 has a major

draw back: it has a lower K value (~8-10) than other candidates. Therefore, even with its

superior thermal stability, Al2O3 can only be used as a short-term solution.

6

Table 1.1. Key properties of high K dielectric candidates [32,33].

Materials Diele. Constant (K) Band Gap (eV) CB Offset (eV) VB Offset (eV)

SiO2 3.9 8.9 3.5 4.4

Si3N4 7 5.1 2.4 4.4

Al2O3 9 8.7 2.8 4.9

Y2O3 15 5.6 2.3 2.6

La2O3 30 4.3 2.3 2.6

TiO2 80 3.5

Ta2O5 26 4.5 0.3 3.0

ZrSiO4/

HfSiO4

13-26 1.5 3.4

HfO2 25 1.5 1.5 3.4

ZrO2 25 3.4 1.4 3.3

Recently, Group IVA (Hf and Zr) metal oxide and their silicates have received

significant attention as alternative gate dielectrics, due to their thermodynamic stability

on Si and their large barrier heights [45-65]. By using an optimized two-step modulated

reactive dc magnetron sputtering process, Lee et al. achieved ultra thin HfO2 gate

dielectric (EOT = 9Å) with a Pt gate [45]. They found that the dielectric constant was

~28 and that the film EOT was stable up to 700 ºC. Lee et al. also reported thin HfO2

(EOT = 10.4 Å) with polysilicon gate without any barrier layer [46]. They reported that

their HfO2 film remained high quality after high temperature dopant activation (950 ºC

for 30 sec) and it had very low leakage current, 0.23 mA/cm2, at 1V gate bias. Copel et

al. grew ultra thin ZrO2 films by atomic layer chemical vapor deposition (ALCVD) [47].

They examined the structure using medium energy ion scattering and cross-sectional

transmission electron microscopy and found that ZrO2 showed stability against silicate

7

formation to temperatures as high as 900 ºC. C.H. Lee et al. showed ultra thin, high

quality rapid thermal CVD deposition of ZrO2 on Si [48]. They showed for an EOT of 9

Å a low leakage current of 20 mA/cm2 at -1 V gate bias. Wilk et al. reported that an EOT

less than 18 Å for a 50 Å Hf6Si29O65 film, which yields a dielectric constant ~11 [49]. Qi

et al. studied sputtered silicate films (12% Zr); For an EOT of 14.5 Å; they reported a low

leakage of 3.3x10-3 A/cm2 at –1.5 V [63].

In addition to HfO2 and ZrO2, La2O3 and Y2O3 have also been considered as

alternative gate dielectric candidates due to their thermodynamic stability on Si and

relatively high effective dielectric constant (~16-27) [66-70]. Chin at el. achieved ultra

thin (EOT ~4.8 Å) La2O3 layers with good dielectric integrity and relatively low leakage

current of 0.06 A/cm2 at -1 V gate bias [66].

For the past several years, there has been a significant advancement in the field of

alternative high K gate dielectrics. Thermally robust candidates, mainly HfO2 and its

silicates showed very promising results. But in spite of these improvements, no clear

winner has been declared and none of the candidates fulfill all the gate dielectric

requirements such as good interface and reliability, high thermal stability and process

comparability with current CMOS technology.

1.3. Metal Gate Candidates

1.3.1. Problems with Poly-silicon Gates and Needs for Metal Gates

As mentioned earlier, the use of poly-silicon is becoming a major problem for

submicron devices [71]. The major problem is the depletion of carriers within the

polysilicon in the MOS inversion region and the resulting loss of current drive and

8

transconductance of the transistor [72]. A poly-silicon depletion layer is formed at the

poly-silicon/gate oxide interface where the active poly-silicon dopant concentration is

low. Conventional CMOS processes use n+ poly-silicon gates for NMOS and p+ gates for

PMOS, which is accomplished by ion implantation and subsequent annealing. But since

shallow junctions are need for sub micron devices, the energy of implantation and dopant

activation temperatures are substantially constrained. This results in less than desired

active dopant in the poly-silicon gate, especially at the oxide interface. Dopant

segregation during silicidation and dopant evaporation during activation anneals also

reduce the poly-silicon doping density [72]. Even in the absence of dopant depletion, as

poly-silicon thicknesses are scaled down in the sub micron regime, the poly-silicon sheet

resistance gets larger, and can limit the MOSFET circuit’s speed. Dopant penetration is

another problem. During the dopants activation thermal cycle, some of the boron dopant

penetrates through the thin gate oxide and shifts the device threshold voltage.

Using a metal gate electrode can potentially eliminate the limitations of

polysilicon gates. In addition, due to the interface reaction between the polysilicon gate

and some of the high K dielectrics at the high temperatures required for dual doping of

poly-silicon, metal gate electrodes may be required for alternative gate dielectrics.

Replacing the polysilicon gate electrode by a metal gate electrode imposes serious

manufacturing and reliability challenges. New metal electrodes need to have

thermal/chemical stability and process compatibility with high k dielectrics and also have

to withstand the entire CMOS processing sequence [73, 74].

9

1.3.2. Metal Gate Electrode Candidates

To integrate n-channel and p-channel devices, dual metal gate electrodes are

needed in order to have appropriate metal work functions for each device. For

conventional device operation, the optimum work functions are within 0.2 eV of the

conduction and valance band edge of Si [75]. There have been some efforts to use a

single metal gate electrode with mid-gap workfunction to simplify the fabrication

process. These attempts were not successful with deep sub micron devices due to either

threshold voltages that were too large for low voltage operation or degraded short

channel characteristics. The energy diagrams of NMOS and PMOS threshold voltage for

midgap and dual metal gates are illustrated in Figure 1.3.3. Even though a midgap metal

gate can simplify the device fabrication process, it requires a low substrate doping to

achieve reasonable threshold voltage and is not suitable for realistic devices [75]. Misra

et al. extracted work functions of different metals by evaluating the flat band voltages on

SiO2, ZrO2 and ZrSiO4 [73]. As summarized in Figure 1.3.4. they found that the work

function of Al, Ta, TaN, Mo, Ti, Hf, Zr, V were near the conduction band of Si, while Pt,

Ru, Rh, Co, Pb, RuO2 were near the valance band; so that these metals appear to be the

potential candidates for NMOS and PMOS gate electrodes, respectively.

1.4. Outline of the Dissertation

This thesis work is focused on the device fabrications and characterizations of

high K gate dielectrics and gate metal electrodes. The first two chapters of this

dissertation were devoted to discuss the new devices fabrication process and integration

issues associated with alternative materials. Later chapters were given to evaluate

10

NMOS and PMOS devices characteristics of advanced gate stacks and their

thermal/chemical stability through the series of electrical measurements.

I would like to point out that most of the work will be presented in this

dissertation was done with Indong Kim, who is a graduate student of our research group.

We shared many of the results came out of our joint research. I also should mention that

the most of high K dielectrics and metal gate electrodes used in this study were deposited

by SRC/SEMATECH FEP research center member groups.

11

1.5. Reference

[1] G.E. Moore, Cramming More Components Onto Integrated Circuits, Electronics,

38, No.8, p.114 (1965)

[2] G.E. Moore, “Progress in Digital Integrated Electronics,” Tech. Dig. Int. Electron

Device Meet., p.11 (1975)

[3] G.E. Moore, “Lithography and The Future of Moore’s Law,” SPIE, Vol 2438, p.2

(1995)

[4] R.H. Dennard, F.H. Gaensslen, L. Kuhn and H-N Yu, “Design of Micron MOS

Switching Devices,” Tech. Dig. Int. Electron Device Meet., p.168 (1972)

[5] R.H. Dennard, F.H. Gasensslen, H-N Yu, V.L. Rideout, E. Bassous and A.R.

LeBlanc, “Design of Ion Implanted MOSFETs With Very Small Physical Dimensions,”

IEEE J. Solid-State Circuits, SC-9, p.256 (1974)

[6] R.H. Dennard, “Scaling Challenges for DRAM and Microprocessors in The 21st

Century.” ULSI Science and Technology/1997, H.Z. Massoud, H. Iwai, C. Claeys and

R.B. Fair, “The Electrochemical Society, Inc., p.519 (1997)

[7] International Technology Roadmap for Semiconductors (ITRS), 2002 Edition,

Dec., 2002, Semiconductor Industry Association

[8] D.A. Muller, T. Sorsch, S. Moccio, F.H. Baumann, K.Evans-Lutterodt, and G.

Timp, “TITLE”, Nature, 399, p.758 (1999)

[9] R. Chau, J. Kavalieros, B. Roberds, R. Schenker, D. Lionberger, D. Barlage, B.

Doyle, R. Arghavani, A. Murthy, and G. Dewey, “30 nm Physical Gate Length CMOS

Transistors with 1.0 ps n-MOS and 1.7 ps p-MOS Gate Delay”, Tech. Dig. Int. Electron


12

[10] B.E. Weir, P.J. Silverman, M.A. Alam, F. Baumann, D. Monroe, A. Ghetti, J.D.

Bude, G.L. Timp, A. Hamid, T.M. Oberdick, N.X. Zhao, Y. Ma, M. M. Brown, D.

Hwang, T.W. Sorsch, and J. Madic, “Gate Oxides in 50 nm Devices: Thickness

Uniformity Improves Projected Reliability”, Tech. Dig. Int. Electron Device Meet., p.437

(1999)

[11] G. Timp, A. Agarwal, F. H. Baumann, T. Boone, M. Buonanno, R. Cireli, V.

Donnelly, M. Foad D. Grant, M. Green, “Low Leakage, Ultra-thin Gate Oxides for

Extremely High Performance sub-100nm nMOSFETs”, Tech. Dig. Int. Electron Device

Meet., p.930 (1997)

[12] G. Timp, K.K. Bourdelle, J.E. Bower, F.H. Baumann, T. Boone, R. Cirelli, K.

Evans-Lutterodt, J. Garno, A. Ghetti, H. Gossmann, “Progress toward 10nm CMOS

Devices”, Tech. Dig. Int. Electron Device Meet., p.615 (1998)

[13] G. Timp, J.Bude, K.K. Bourdelle, J. Garno, A. Ghetti, H. Gossmann, M. Green,

G. Forsyth, Y. Kim R. Kleimann, “The Ballistic Nano-transistor”, Tech. Dig. Int.

Electron Device Meet., p.55 (1999)

[14] B. Yu, H. Wang, C. Riccobene, Q. Xiang, and M. Lin, “Limits of Gate-Oxide

Scaling in Nano-Transistors” Symp. on VLSI Tech. Dig., p. 90 (2000)

[15] K.F. Schuegraf, C.C. King, and C. Hu, ”Ultra-thin Silicon Dioxide Leakage

Current and Scaling Limit,” Symp. On VLSI Tech. Dig., p. 18 (1992)

[16] S-H. Lo, D.A. Buchanan, Y. Taur and W. Wang, “Quantum-Mechanical

Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide

nMOSFET’s,” IEEE Electron Device Letters, Vol. 18, No. 5, p.209 (1997)

13

[17] P. Zeitzoff, “Front-End Trends, Challenges, and Potential Solutions for The 180 –

100 nm IC Technology Generations,” Semiconductor Fabtech, 10th edition, p.275 (1999)

[18] S-H. Lo, D.A. Buchanan, Y. Taur, L-K. Han, and E. Wu, “Modeling and

Characterization of n+ and p+ polysilicon-Gated Ultra-thin Oxides,” Symp. on VLSI

Tech. Dig., p. 149 (1997)

[19] M.J. van Dort, P.H. Woerlee, and A.J. Walker, “A Simple Model for Quantization

Effects in Heavily-Doped Silicon MOSFET’s at Inversion Conditions,” Solid Sate

Electron., Vol.37, No. 3, p.411 (1994)

[20] J.R. Hauser and K. Ahmed, “Characterization of Ultra-Thin Oxides Using

Electrical C-V and I-V Measurement,” National Institute of Standard and Technology,

Gaitersburg, MD, March 23-26 (1998)

[21] C.-L. Huang and N.D. Aroa, “Measurement and Modeling of MOSFET I-V

Characteristics with Polysilicon Depletion Effect,” IEEE Trans. Electron Devices, Vol

40, p. 2330 (1993)

[22] J.A. Lopez-Villanueva, I. Melchov, F. Gamiz, J. Banqueri, and J.A. Jimeneg-

Tejoda, “A Model For the Quantized Accumulation layer in Metal –Insulator-

Semiconductor Structures“, Solid State Electron., Vol 38, p.203 (1995)

[23] S. Thompson, P. Packan, and M. Bohr, “MOS Scaling: Transistor Challenges for

the 21st Century,” Intel Tech. Journal, p.1, Q3 (1998)

[24] R.B. Fair, ”Oxide Thickness Effect on Boron Diffusion in Thin Oxide P+ Si Gate

Technology,” IEEE Electron Device Letters, Vol. 17, No. 5, p.242 (1996)

14

[25] S.V. Hattangady, R. Kraft, D.T. Grider, M.A. Douglas, G.A. Brown, P.A. Tiner,

J. W. Kuehne, P.E. Nicollian, and M.F. Pas, “Ultrathin nitrogen-profile engineered gate

dielectric films”, Tech. Dig. Int. Electron Device Meet., p.495 (1996)

[26] Y. Wu, and G.Lucovsky, “Ultrathin nitride/oxide (N/O) gate dielectrics for p+-

polysilicon gated PMOSFETs prepared by a combined remote plasma enhanced

CVD/thermal oxidation process”, IEEE Electron Device Letters, Vol. 19, p.367 (1998)

[27] X.W. Wang, Y. Shi, and T.P. Ma, “Extending gate dielectric scaling limit by use

of nitride or oxynitride”, Symp. On VLSI Tech. Dig., p.109 (1995)

[28] K.A. Ellis, and R.A. Buhrman, “Time-dependent diffusivity of boron in silicon

oxide and oxynitride”, Appl. Phys. Lett. Vol 74, p. 967 (1999)

[29] K.A. Ellis, and R.A. Buhrman, “Boron Diffusion in Silicon Oxides and

Oxynitrides”, J. Electrochem. Soc. Vol 145, p. 2068 (1998)

[30] H. Yang, and G. Lucovsky, “Integration of ultrathin (1.6~2.0 nm) RPECVD

oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs”, Tech. Dig. Int.


[31] M. Khare, X.W. Wang, and T.P. Ma, “Transconductance in Nitride-Gate or

Oxynitride Gate Transistor”, IEEE Electron Device Letters, Vol. 20, No. 1, p.57 (1999)

[32] J. Robertson, “Band Offsets of Wide-band-gap Oxides and Implications for

Future Electronic Devices”, J. Vac. Sci. Technol. B, Vol. 18, p.1785 (2000)

[33] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-K gate dielectrics: Current

status and materials properties consideration”, J. Appl. Phys., Vol 89, No 10, p. 5243

(2001)

15

[34] Y. Momiyama, H. Minakata, and T. Sugii, “Ultra-Thin Ta2O5/SiO2 Gate Insulator

with TiN Gate Technology for 0.1 mm MOSFETs,” Symp. On VLSI Tech. Dig., p.135

(1997)

[35] D. Park, Y-C. King, Q. Lu, T-J. King, C. Hu, A. Kalnitsky, S-P. Tay, and C-C.

Cheng, “Transistor Characteristics with Ta2O5 Gate Dielectrics,” IEEE Electron Device

Letters, Vol. 19, No. 11, p.441 (1998)

[36] H.F. Luan, S.J. Lee, C.H. Lee, S.C. Song, Y.L. Mao, Y. Senzaki, D. Robert, and

D.L. Kwong, “High Quality Ta2O5 Gate Dielectrics with Tox,eq<10Å,” Tech. Dig. Int.


[37] X. Guo, T.P. Ma, T. Tamagawa, and B.L. Halpern, “High Quality Ultra-Thin

TiO2/Si3N4 Gate Dielectric for Giga Scale MOS Technology,” Tech. Dig. Int. Electron


[38] S.A. Campbell, D.C. Gilmer, X-C. Wang, M-T. Hsieh, H-S. Kim, W. L.

Gladfelter, and J. Yan, “MOSFET Transistors Fabricated with High Permitivity TiO2

Dielectrics,” IEEE Trans. Electron Devices, Vol 44, p. 104 (1997)

[39] R.A. McKee, F.J. Walker, and M.F. Chisholm, “Crystalline Oxides on Silicon:

The First Five Monolayers,” Phys. Rev. Lett. Vol 81, p. 3014 (1998)

[40] K.J. Hubbard, and D.G. Schlom, “Thermodynamic Stability of Binary Oxides in

Contact with Silicon,” J. Mater. Res., Vol. 11, p. 2757 (1996)

[41] G.B. Alers, D.J. Werder, Y.Chabal, H.C. Lu, E.P. Gusev, E. Garfunkel, T.

Gustafsson, and R.S. Urdahl, “Intermixing at the Tantalum Oxide/Silicon Interface in

Gate Dielectrics Structures.” Appl. Phys. Lett. Vol 73, p. 1517 (1998)

16

[42] A. Chin, C. C. Liao, C. H. Liu, W. J. Chen, and C. Tsai “Device and Reliability of

High-K Al2O3 Gate Dielectric with Good Mobility and Low Dit,” Symp. On VLSI Tech.

Dig., p.135 (1999)

[43] A. Chin, Y. H. Wu, S. B. Chen, C. C. Liao, and W. J. Chen, “High Quality La2O3

and Al2O3 Gate Dielectrics with Equivalent Oxide Thickness 5-10 Å,” Symp. On VLSI

Tech. Dig., p.16 (2000)

[44] D.A. Buchanan, E.P. Gusev, E. Cartier, H. Okorn-Schmidt, K. Rim, M.A.

Gribelyuk, A. Mocuta, A. Ajmera, M. Copel, S. Guha, N. Bojarczuk, A. Callegari, C. D

Emic, P. Kozlowski, K. Chen, R.J. Fleming, P.C. Jamison, J. Browin, and R. Ardnt, “80

nm Poly-silicon Gated n-FETs with Ultra-Thin Al2O3 Gate Dielectric for ULSI

Application,” Tech. Dig. Int. Electron Device Meet., p.223 (2000)

[45] B.H. Lee, L.Kang, W.-J. Qi, R. Nieh, Y. Jeon, K. Onishi, and J.C. Lee, “Ultrathin

Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative Gate

Dielectric Application,” Tech. Dig. Int. Electron Device Meet., p.133 (1999)

[46] S.J. Lee, H.F. Luan, W.P. Bai, C.H. Lee, T.S. Jeon, Y. Senzaki, D. Roberts, and

D.L. Kwong, “High Quality Ultra Thin CVD HfO2 Gate Stack with Poly-Si Gate

Electrode,” Tech. Dig. Int. Electron Device Meet., p. 31 (2000)

[47] M. Copel, M. Gribelyuk, E. Gusev, “Structure and Stability of Ultrathin

Zirconium Oxide Layers on Si(001),” Apple. Phys. Lett. Vol 76, p. 436 (2000)

[48] C.H. Lee, H.F. Luan, S.J. Lee, T.S. Jeon, W.P. Bai, Y. Sensaki, D. Roberts, and

D.L. Kwong, “MOS Characteristics of Rapid Thermal CVD ZrO2 and Zr Silicate Gate

Dielectrics,” Tech. Dig. Int. Electron Device Meet., p. 27 (2000)

17

[49] G.D. Wilk, R.M. Wallace, and J. M. Anthony, “Hafnium and Zirconium Silicates

for Advanced Gate Dielectrics,” J. Appl. Phys. Vol 87, p.484 (2000)

[50] L.K. Kang, Y. Jeon, K. Onishi, B.H. Lee, W.-J. Qi, R. Nieh, S. Gopalan, and J.C.

Lee, “Single-layer Thin HfO2 Gate Dielectric with n+ Polysilicon Gate,” Symp. On VLSI

Tech. Dig., p.44 (2000)

[51] Y. Ma, Y. Ono, L. Stecker, D.R. Evans, and S.T. Hus, “Zirconium Oxide Based

Gate Dielectrics with Equivalent Oxide Thickness of Less Than 1.0 nm and Performance

of Submicron MOSFET using a Nitride Gate Replacement Process,” Tech. Dig. Int.

Electron Device Meet., p. 149 (1999)

[52] W.-J. Qi, R. Nieh, B.H. Lee, L. Kang, Y. Jeon, K. Onishi, T. Nagi, S. Banerjee,

and J.C. Lee, “MOSCAP and MOSFET Characteristics using ZrO2 Gate Dielectric

Deposited Directly on Si,” Tech. Dig. Int. Electron Device Meet., p. 63 (1999)

[53] W.-J. Qi, R. Nieh, B.H. Lee, K. Onishi, L. Kang, Y. Jeon, J.C. Lee, V. Kaushik,

B.-Y. Neuyen, L. Prabhu, K. Eisenbeiser, and J. Finder, “Performance of MOSFETs with

Ultra Thin ZrO2 and Zr Silicate Gate Dielectrics,” Symp. On VLSI Tech. Dig., p.40

(2000)

[54] S.A. Campbell, R. Smith, N. Hoilien, B. He, and W.L. Gladfelter, “Group IVB

Metal Oxides: TiO2, ZrO2, and HfO2 as High Permitivity Gate Insulators,” MRS

Workshop, New Orleans, LI, June 1-2, p.9 (2000)

[55] R.C. Smith, N. Hoilien, C.J. Taylor, T. Ma, S.A. Campbell, J.T. Roberts, M.

Copel, D.A. Buchana, M. Gribelyuk and W.L. Gladfelter, “Low Temperature Chemical

Vapor Deposition of ZrO2 on Si (100) Using Anhydrous Zirconium (IV) Nitrate,” J.

Electrochem. Soc., Vol 147, p. 3472 (2000)

18

[56] M. Houssa, V.V. Afanas’ev, A. Stesmans, and M.M. Heyns, “Variation in the

Fixed Charge Density of SiOx/ZrO2 Gate Dielectric Stacks During Postdeposition

Oxidation,” Appl. Phys. Lett. Vol 77, p. 1885 (2000)

[57] T. Yamaguchi, H. Satake, N. Fukushima, and A. Toriumi, “Band Diagram and

Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by

Pulsed-laser-ablation Deposition,” Tech. Dig. Int. Electron Device Meet., p.19 (2000)

[58] L. Manchanda, M.L. Green, R.B. van Dover, M.D. Morris, A. Kerber, Y. Hu, J.-

P. Han, P.J. Silverman, T.W. Sorsch, G. Weber, V. Donnelly, K. Pelhos, F. Klemens, N.

A. Ciampa, A. Kornblit, Y.O. Kim, J.E. Bower, D. Barr, E. Ferry, D. Jacobson, J. Eng, B.

Bush, and H. Schulte, “Si-Doped Aluminates for High Temperature Metal-Gate

CMOS:Zr-Al-Si-O, A Novel Gate Dielectric for Low Power Applications,” Tech. Dig.

Int. Electron Device Meet., p.23 (2000)

[59] L. Kang, K. Onishi, Y. Jeon, B.H. Lee, C. Kang, W.-J. Qi, R. Nieh, S. Gopalan,

R. Choi, and J.C. Lee, “MOSFET Devices with Polysilicon on Single-Layer HfO2 High-

K Dieletrics,” Tech. Dig. Int. Electron Device Meet., p.35 (2000)

[60] B.H. Lee, R. Choi, L. Kang, S. Gopalan, R. Nieh, K. Onishi, Y. Jeon, W.-J. Qi, C.

Kang, , and J.C. Lee, “Characteristics of TaN Gate MOSFET with Ultrathin Hafnium

Oxide,” Tech. Dig. Int. Electron Device Meet., p.39 (2000)

[61] G.D. Wilk, and R.M. Wallace, “Electrical Properties of Hafnium Silicate Gate

Dielectrics Deposited Directly on Silicon,” Appl. Phys. Lett. Vol 74, p.2854 (1998)

[62] G.D. Wilk, and R.M. Wallace, “Stable Zirconium Silicate Gate Dielectrics

Deposited Directly on Silicon,” Appl. Phys. Lett. Vol 76, p. 112 (2000)

19

[63] W.-J. Qi, R. Nieh, E. Dharmarajan, B.H. Lee, Y. Jeon, L. Kang, K. Onishi, and

J.C. Lee, “Ultrathin Zirconium Silicate Film with Good Thermal Stability for Alternative

Gate Dielectric Application,” Appl. Phys. Lett. Vol 77, p. 1704 (2000)

[64] G. Lucovsky, G.B. Rayner, Jr., “Microscopic Model for Enhanced Dielectric

Constants in Low Concentration SiO2-rich Noncrystalline Zr and Hf Silicate Alloys,”

Appl. Phys. Lett. Vol 77, p. 2912 (2000)

[65] R.Therrien, B. Rayner and G. Lucovsky, “Electrical Performance of MOS

Devices with Plasma Deposited ZrO2-SiO2 Pseudo-Binary Silicate Alloys,” ECS Ext.

Abst. PV 00-1, Abst. No. 490 (2000)

[66] A. Chin, Y.H. Wu, S.B. Chen, C.C. Liao, and W.J. Chen, “High Quality La2O3

and Al2O3 Gate Dielectrics with Equivalent Oxide Thickness 5-10 Å,” Symp. On VLSI

Tech. Dig., p.16 (2000)

[67] S. Guha, E. Cartier, M.A. Gribelyuk, N.A. Bojarczuk, and M.C. Copel, “Atomic

Beam Deposition of Lanthanum and Yttrium Based Oxide Thin Films for Gate

Dielectrics,” Appl. Phys. Lett. Vol 77, p. 2710 (2000)

[68] Y.H. Wu, M.Y. Yang, A. Chin, W.J. Chen, and C.M. Kwei, “Electrical

Characteristics of High Quality La2O3 Gate Dielectrics with Equivalent Oxide Thickness

of 5 Å,” IEEE Electron Device Letters, Vol 21, p. 341 (2000)

[69] J. Kwo, M. Hong, A.R. Kortan, K.T. Queeney, Y.J. Chabal, J.P. Mannaerts, T.

Boone, J.J. Krajewski, A.M. Sergent, and J. M. Rosamilia, “High ε Gate Dielectric

Gd2O3 and Y2O3 for Silicon,” Appl. Phys. Lett. Vol 77, p. 130 (2000)

20

[70] J.J. Chambers, and G.N. Parsons, “Yttrium Silicate Formation on Silicon: Effect

of Silicon Preoxidatioin and Nitridation on Interface Reaction Kinetics,” Appl. Phys.

Lett. Vol 77, p. 2385 (2000)

[71] IEEE Trans. Electron Devices, “High performance damascene metal gate

MOSFETs for 0.1 µm regime”, Vol 47, p. 1028 (2000)

[72] C.Y. Wong, J.Y.Sun, Y. Taur, C.S. Oh, R. Angelucci, and B. Davari, “ “ Tech.

Dig. Int. Electron Device Meet., p.238 (1988)

[73] V. Misra, G. Heuss, and H. Zhong, “Advanced Metal Electrodes for High-K

Dielectrics,” MRS Workshop, New Orleans, LI, June 1-2, p.5 (2000)

[74] H. Zhong, G. Heuss, and V. Misra, “Electrical Properties of RuO2 Gate Electrodes

for Dual Metal Gate Si-CMOS,” IEEE Electron Device Letters, Vol 21, p. 593 (2000)

[75] I. De, D. Johri, A. Srivastava, C.M. Osburn, “Impact of Gate Workfunction on

Device Performance at the 50 nm Technology Node”, Solid-State-Electronics, Vol 44,

No. 6, p. 1077 (2000)

[76] CRC Hand book of Chemistry and Physics, 83rd Edition, 2002, CRC Press

21

Figure 1.1 Measured and simulated gate leakage currents for SiO2 dielectrics [16].

Figure 1.2. Conduction and Valance band calculations for high K gate dielectric candidate materials [32].

22

Figure 1.3. Energy level diagram of (a) midgap metal gates and (b) dual metal gate.

Figure 1.4. Work function of metal gate candidates [76].

Al (4.08) Ta (4.19) Mo (4.20)Sr V (4.30) Ti (4.33)

Sn (4.42) W (4.52) Cr

Ru (4.71)Rh (4.80)Co (4.97) Pb (4.98) Re Ni (5.10)

Ir (5.27) Pt (5.34)

Ec (4.05)

Ev (5.17)

Single Midgap Dual Vacuum

Si

1.1

Ec

Ev

ΦB Ec

Ev

ΦB PtΦB Ta

(a)

(b)

23

CHAPTER 2

Device Fabrication Incorporating Alternative Gate Stack

2.1. Processing Issues Related to MOS Device Fabrication and Performance

Many alternative, high K gate dielectrics and gate metal candidates are degraded

by high junction annealing temperatures, so that conventional MOSFET device

fabrication processes flow can not be used. Successful incorporation of these materials

requires that the thermal budget after the gate stack formation be reduced. New schemes,

required to incorporate these materials during device fabrication, pose an entirely new set

of process constraints. Ideally, the new processing technologies should be such that new

materials can be easily incorporated without requiring major changes. Two alternative

approaches have been identified to achieve this aim: 1) a process requiring the formation

of junctions at low temperatures and 2) a process reversing the order of junction and gate

stack formation.

The low temperature junction approach self aligns the junction to the gate stack

but requires low temperature (450 – 500 ºC) junction activation annealing [1-3]. This

process is essentially the same as conventional device fabrication except the dopant

activation and ion implantation damage removal annealing is done at low temperature.

Even though this approach can easily be integrated into existing processes having self-

align junctions, low temperature annealing has not been established. With low dopant

activation temperatures, not all of the dopant may activate resulting in high sheet

resistance. Furthermore, complete removal of damage created by ion implantation may

24

not be possible at such a low temperature, so that high junction leakage is expected.

Reversing the order of the gate stack and the junction formation processes require

forming the gate dielectric and electrode after the junction annealing step. Thus the

thermal budget after the gate stack formation can be minimized, thereby making the

process compatible with use of high K dielectrics and metal gate electrodes. There are

two different ways to reverse junction and gate stack processes. The first approach is the

non-self aligned gate process, and the other approach is the replacement gate process.

2.2. Replacement Gate Process

Figure 2.1 shows the process flow for the self-aligned replacement gate process

[4-7]. Fabrication starts with the conventional self aligned process using a poly-silicon

gate through junction silicide formation. After that a SiO2 layer is deposited over the

entire wafer and then the wafer is chemical mechanical polished (CMP) down to the

poly-silicon gate level. As shown in Figure 2.1 (c) the sacrificial poly-silicon gate is then

removed followed by the removal of the sacrificial gate oxide. The desired high K

dielectric is deposited over the wafer followed by gate electrode metal. This metal layer

is patterned either by polishing back to the original poly-silicon level using a second

CMP or by lithography and conventional etching. The gate is then self-aligned with

respect to the source and drain, and there is a minimal overlap of the gate metal on thin

dielectric over the heavily doped junctions. Additional oxide is deposited followed by

conventional contact hole opening and the interconnect metallization.

In addition to its process complexity, the replacement gate process poses other

processing concerns. First is the potential etching of the sidewall oxide grown on the

25

sacrificial poly-Si. When the sacrificial gate oxide is etched using BOE, some or all of

the sidewall oxide will also etch. This leads to the increase in the area of the overlap of

the gate electrode over the junction, thus increasing the capacitance, and decreasing the

speed of the device. Another concern with this approach is the selectivity of the CMP

process. It is necessary to remove all the gate metal off the field region without eroding

the electrode in the gate area. Depending on the gate electrode material, entirely new

CMP processes and slurries may be required.

2.3. Non-self Aligned Gate Process

A novel non-self aligned process and a new mask set, ERC-6, has been developed

in this work to facilitate more rapid evaluation of alternative, high K dielectrics and new

gate electrode materials. This process has only 31 steps, as compared to 66 steps for a

replacement gate process. This process forms the junctions before the gate stack and thus

allows the use of dielectrics and gate electrodes that are not able to withstand normal

junction annealing temperatures.

In this process, since the gate is not self-aligned to the junctions, it is necessary

that the gate mask be designed in such a manner that for worst case alignment the

electrode overlaps the junctions. This requires that the gate overlap be quite large

compared to that in a self-aligned process; thus the total layout area and device overlap

capacitance are also larger. Although this non-self aligned gate process is not

competitive for high performance applications, it has been used here to quickly evaluate

alternative high K dielectric materials and narrow options.

26

2.4. ERC 6 Mask Set

A new mask set, ERC 6, was designed to facilitate more rapid evaluation of

alternative, high k dielectrics and new gate electrode materials within FEP Center. An

issue with most of these new candidates is their limited thermal stability. The thermal

cycles associated with junction formation are too long for most of these material systems.

Figure 2.2. shows a superposition of all 4 mask set levels in the ERC 6 mask set.

• Level 10, the dark-field junction level, for junction area definition

• Level 20, the light-field contact level, for source/drain contact and gate area

definition

• Level 30, the light-field gate electrode level, for gate dielectric and gate electrode

definition

• Level 40, the dark-field contact metal level, for source/drain metal contact

formation

The mask set was patterned onto 5X quartz reticles, which were designed for GCA

steppers. Feature dimensions are reduced 5 times when transferred to the wafer. The

reticle dimensions were 5” x 5” and 0.090 mils thick. The mask set was manufactured by

DuPont Photomask, Inc. The ERC 6 chip die is divided into a 5x10 array of 2 mm x 1

mm cells (wafer dimensions), most of which are laid out horizontally. Six cells

containing transistor devices are rotated 90º in order to include orthogonal structures.

The key test structures in the ERC 6 mask set are summarized in Table 2.1.

27

Table 2.1. Summary of structures in ERC 6 mask set

Structures Description Cells Resolution targets Determine the smallest feature size resolved at

each lithography level. A1, J1, F3, A5, F5

24 devices: W=50µm, L=50µm I2, DE4(F), B4, F5

21 devices: W =10 µm, L=0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 6, 7, 10, 15, 25, 30, 50, 70, 100 µm

D1, FG2(B), A4,

Directly probe-able MOSFET

21 devices: W = 3 µm, L=0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 6, 7, 10, 15, 25, 30, 50, 70, 100 µm

CD2(F), E2, I3, I5

24 devices: W = 1 µm, L = 2, 3, 4, 5, 7, 10, 15, 20, 50 µm W = 5 µm, L = 2, 3, 4, 5, 7, 10, 15, 20, 50 µm W = 10 µm, L = 2, 3, 4, 5, 7, 10, 15, 20, 50 µm

FG2(F), D3, H4

21 devices: W =50 µm, L=0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 6, 7, 10, 15, 25, 30, 50, 70, 100 µm

G3, C5

6 devices: W=100µm, L=100µm A3, E5 Indirectly probe-able

MOSFET 16 devices: W = 10 µm, L = 0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 7, 10, 15, 20 µm

E1

16 devices: W = 3 µm, L = 0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 7, 10, 15, 20 µm

CD2(B), B3, G5

MOS Capacitors Three different areas: 105 ,104 , 103 µm2 F1, F4, H3, J3, I4, D5

Sheet resistance Measurement

Van der Pauw and 4-point probe structures for sheet resistance measurement.

I1, E3, B5

structures 4-point probe structures for sheet resistance measurement.

J2, G4

Contact resistance measurement

structures

TLTR-EE and TLTR-CE structures for contact resistance measurement.

BC1, GH1

28

2.5 Device Fabrication using the Non-self Aligned Gate Process

The non-self aligned process has been used to fabricate devices having a variety

of high K gate dielectrics and gate metals produced in the FEP research center. A

detailed matrix of high K dielectrics, gate electrodes and total number of wafers

processed is summarized in Table 2.2. The non-self aligned gate process is schematically

shown in Figure 2.3 and in detail in Appendix A. The starting substrates were (100)

oriented, lightly doped, 100 and 150mm n and p-type silicon wafers. All the wafers went

Table 2.2. Matrix of high K dielectrics and gate electrode materials

Run Name Wafer

Size

Number

of Wafers

Dielectrics Gate Electrodes

NMOS 1 &

PMOS 2

100 mm 50 SiO2, TiO2,

ZrO2,Ta2O5, ZrSiO2

Al & TiN

NMOS 2 &

PMOS 2

100 mm 50 SiO2, HfO2, ZrO2,

SiO2/Si3N4

Al, Pt, TaN and

Poly-silicon

NMOS 3 &

PMOS 3

150 mm 50 SiO2, HfO2,

ZrO2,La2O3

Al, Pt, TaN and

Poly-silicon

NMOS 4 &

PMOS 4

100 mm 50 HfO2, ZrO2 Ru, Ta and n+/p+

Poly-silicon

NMOS 5-7 &

PMOS 5-7

150 mm 150 (HfO2)0.7•(Al)0.3,

(ZrO2)0.7•(Al)0.3,

(TiO2)0.7•(Al)0.3, HfO2,

ZrO2, Y2O3,

and La2O3

Ru, Ta and n+/p+

Poly-silicon

NMOS 8 &

PMOS 8

50 mm 25 Hf Silicate Al, Poly-silicon,

TaSixNy

29

though an RCA clean and then a 6.5 nm sacrificial oxide was grown. The wafers were

implanted through the sacrificial oxide in order to have an appropriate threshold voltage

for 70 nm technology nodes. A boron dose of 3.4x1013 cm-2 at 25 keV was implanted into

the p-type substrates, and a phosphorus dose of 1.3x1013 cm-2 at 28 keV was implanted

into the n-type substrates. After an RCA clean and 30 sec BOE dip to remove the

sacrificial oxide, a 100 nm thick field oxide was thermally grown at 1000 ºC for 6.7 min,

and a subsequent anneal was performed at 950 ºC for 60 min in N2 ambient to give a

uniform channel doping profile near the silicon surface (~1018/cm3). The thick oxide was

then patterned with a GCA800 DSW i-line lithography stepper and etched in a buffered

HF solution to define the source/drain junction. The contact junctions were implanted

with arsenic (As75) at a dose of 1.5x1015 cm-2 at 15 keV for NMOS devices and BF2 at a

dose of 1x1015 cm-2 at 19 keV for the PMOS devices to have a junction depth around 100

nm. Following the junction implantation, the dopants were activated by either rapid

thermal anneal (RTA) at 1000 ºC for 10 sec or furnace anneal at 950 ºC for 10 min in N2

ambient. After the junction formation, 100 nm LPCVD oxide was deposited. Both the

contact holes and the gate regions were then opened using optical lithography and

buffered oxide etching as shown in figure 2.3. Following the gate area definition, the

high K gate dielectrics and gate metals were deposited. The gate stacks were defined by

optical lithography, and appropriately etched. For each gate dielectric and electrode

material, etching recipes had to be developed and optimized. Detailed discussion of

etching of different dielectrics and gate electrodes will be presented later. After the gate

stack was completed, lift-off lithography was performed to pattern contact metal. A

contact metal bi-layer, 200 nm aluminum on top of 50 nm of titanium, was evaporated

30

onto the substrate and patterned by a lift-off process. The thin backside oxide was then

removed and aluminum was evaporated on the backside for substrate contact. A forming

gas anneal at 400 ºC for 30 min was carried out for oxide controls and for some of the

splits.

2.6 Gate Dielectrics and Gate Metal Electrodes Deposition Methods

The deposition methods for the high K dielectrics and metal gate electrodes used

in this work are summarized in Table 2.3. [8-12]. Control oxides for baseline wafers

were grown by rapid thermal oxidation (RTO) in an RTP system at NCSU (N2, 880˚C

50Torr, 30sec). TiO2/Si3N4 was deposited in the jet vapor deposition (JVD) system at

Yale [9]. Diluted silane and a N2+He jet vapor source were used to form the bottom

nitride layer, while the upper TiO2 film was deposited using a jet of titanium and atomic

oxygen vapor. TiO2 gate dielectric was also prepared in a MOCVD system at the

University of Minnesota [10]. Titanium tetrakis-isopropoxide was used as a precursor in

an argon carrier gas and the film received a 30 min post deposition anneal in an oxygen

furnace at 750 ºC. Rapid thermal chemical vapor deposition (RTCVD) was used to

deposit Ta2O5 at the University Texas at Austin using TaC12H30O5N2+O2 precursor [8].

After the deposition, post deposition annealing was performed in O2 or H2/O2 ambient to

improve film quality and reduce leakage current. Three different sources for both ZrO2

and HfO2 were used: Jet Vapor Deposition (JVD) (at Yale), Rapid Thermal CVD

(RTCVD) (at UT Austin) and DC Magnetron Sputtering (PVD) (at UT Austin). For ZrO2

and HfO2 films deposited by RTCVD, NH3-based interface layers were grown at 700 °C

for 10 sec prior to the actual dielectric deposition. The RTCVD depositions of HfO2 and

31

ZrO2 films were performed at 500 °C for 3 min using O2 + C16H36HfO4 and 500 °C for 2

min using O2 + C16H36O4Zr precursors, respectively. After the dielectric deposition, in-

situ post-deposition annealing was performed in an N2 ambient at 700 – 900 °C for 30 sec

for both films. JVD of ZrO2 and HfO2 were performed at room temperature. For JVD

Table 2.3. High K dielectrics and metal gate electrodes deposition methods and their

deposition condition

Materials Deposition Method Deposition Condition

HfO2 DC Magnetron Sputtering at 20°C for 10 sec

ZrO2 Sputtering(PVD) Reoxdiation at 500°C in N2 for 40 sec

HfO2 Rapid Thermal CVD At 500°C for 3 min using O2 and

ZrO2 (RTCVD) C16H36HfO4/C16H36O4Zr/ TaC12H30O5N2

Ta2O5

HfO2 Metal Organic CVD

ZrO2 (MOCVD) 350°C using HF(NO3)4

TiO2

HfO2 Jet Vapor Deposition (JVD) Mixture of Hf/Zr and O2 jet vapor at

ZrO2 350°C

TiO2/Si3N4

Y2O3 Remote Plasma Enhanced

CVD (RPECVD)

At 400°C using O2 and Y(tmhd)3

La2O3 Molecular Beam Epitaxy

(MBE)

La was evaporated in O2 ambient at

900°C

RuO2/Ru/

Ta/W

RF Magnetron Sputtering At 100 W in Ar ambient

Pt DC Magnetron Sputtering At 250W in Ar ambient

TaN Reactive Sputtering At 200 W in Ar ambient

32

HfO2 we compared N2 plasma with an HF last treatment for pre-deposition cleaning, and

we compared N2 to forming gas for the 600˚C post deposition annealing. Films of ZrO2

had the same cleaning process but had different post deposition steps, such as 20min

350˚C forming gas, 10sec. 400˚C forming gas or 5sec. 600˚C, N2 ambient rapid thermal

processing. NH3 surface pre-treatment (700 ˚C for 30 sec at 1 atm) were done for PVD

HfO2 and ZrO2. Both Hf and Zr were deposited by DC magnetron sputtering at 20 ºC, 30

mtorr. After the PVD depositions, in order to form a metal oxide, Hf and Zr films were

oxidized in an N2 ambient for 40 sec at 600 ºC and for 40 sec at 500 ºC, respectively.

For the La2O3 films, La was deposited by reactive co-evaporation in an MBE

system; then the La2O3 film was grown in an O2 ambient of 2×10-5 Torr. For the La2O3

splits, an additional oxide/nitride interface was added before deposition to study the

interface properties. Rapid thermal processing at 900˚C in N2 ambient was performed for

post deposition annealing.

For gate electrodes, low-temperature (800˚C) in-situ doped and conventional disk-

doped poly gates were used as a reference for comparing other metal gate electrodes. For

metal gates, commercially available TaN was used or Pt was deposited using magnetron

sputtering. To enhance Pt adhesion to the dielectric, a 20 min, 500˚C N2 annealing was

performed. Ru films were deposited using a RF magnetron sputtering system. After the

Ru deposition, in-situ W was deposited on top of Ru to have better contact with probe

tips.

33

2.7. Reference [1] T. Ushiki, Y. Hirano, H. Shimada, and T. Ohmi, “High Performance, Metal-Gate

SOI CMOS Fabricated by Ultraclean, Low-Temperature Process Technologies,” SPIE,

Vol. 2875, p.28 (1995)

[2] C. Hashimoto and H. Ushizaka, “A Low Temperature MOS LSI Process,” IEEE

Electron Device Letters, Vol. 9, No.3, p. 130 (1988)

[3] K. Tomita, T. Migita, S. Shimonishi, T. Shibata, T. Ohmi, and T. Nitta,

“Eliminating Metal Sputter Contamination in Ion Implanter for Low-Temperature-

Annealed, Low-Reverse-Bias-Current Junction,” J. Electrochem. Soc., Vol.142, No. 5, p.

1692 (1995)

[4] A. Chatterjee, R.A. Chapman, G. Dixit, J. Kuehne, S. Hattangady, H. Yang, G.A.

Brown, R. Aggrawal, U. Erdogan, Q. He, M. Hanratty, D. Rogers, S. Murtaza, S.J. Fang,

R. Kraft, A.L.P. Rotondaro, J.C. Hu, M. Terry, W. Lee, C. Fernando, A. Konecni, G.

Wells, D. Frystak, C. Bowen, M. Bowen, M. Rodder, and I.-C. Chen, “Sub-100nm Gate

Length Metal Gate NMOS Transistors Fabricated by a Replacement Gate Process,” Tech.


[5] A. Chatterjee, R.A. Chapman, K. Joyner, M. Otobe, S. Hattangady, M. Bevan,

G.A. Brown, H. Yang, Q. He, D. Rogers, S.J. Fang, R. Kraft, A.L.P. Rotondaro, M.

Terry, K. Brennan, S.-W. Aur, J.C. Hu, H-L Tsai, P. Jones, G. Willk, M. Aoki, M.

Rodder and I.-C. Chen, “CMOS Replacement Gate Transistors using Tantalum Pentoxide

Gate Insulator,” Tech. Dig. Int. Electron Device Meet., p.777 (1998)

[6] A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G.

Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, and K. Okumura, “High

34

Performance Metal Gate MOSFETs Fabricated by CMP for 0.1µm Regime,” Tech. Dig.


[7] Y. Ma, D.R. Evnas, T. Nguyen, Y. Ono, and S.T. Hsu, “Fabrication and

Characterization of Sub-Quarter Micron MOSFET’s with a Copper Gate Electrode”,

IEEE Electron Device Letters, Vol. 20, No.5, p. 254 (1999)

[8] H.F. Luan, S.J. Lee, C.H. Lee, S.C. Song, Y.L. Mao, Y. Senzaki, D. Robert, and

D.L. Kwong, “High Quality Ta2O5 Gate Dielectrcis with Tox,eq<10Å,” Tech. Dig. Int.


[9] X. Guo, T.P. Ma, T. Tamagawa, and B.L. Halpern, “High Quality Ultra-Thin

TiO2/Si3N4 Gate Dielectric for Giga Scale MOS Technology,” Tech. Dig. Int. Electron


[10] S.A. Campbell, D.C. Gilmer, X-C. Wang, M-T. Hsieh, H-S. Kim, W. L.

Gladfelter, and J. Yan, “MOSFET Transistors Fabricated with High Permitivity TiO2

Dielectrics,” IEEE Trans. Electron Devices, Vol 44, p. 104 (1997)







35

Deep S/D JuncitonSacrificial Gate Oxide

Dielectric SpacerPoly Si

Silicide

LDD Junction

a)

Deep S/D JuncitonSacrificial Gate Oxide

Poly Si

LDD Junction

Oxide

Deep S/D Junciton LDD Junction

Oxide

Deep S/D JuncitonHigh k Gate Oxide

LDD Junction

OxideMetal Gate

b)

c)

d)

Figure 2.1. Schematic illustration of replacement gate process: a) Conventional device fabrication using sacrificial gate oxide; b) Oxide deposition and CMP planarization etchback; c) Etch out sacrificial gate stack; d) Deposition new gate stack and patterning of gate electrode.

36

Figure 2.2. Non-self aligned gate process chip layout (ERC6)

A

B

C

D

E

F

G

H

I

J

1 2 3 4 5

37

Si W afer

Ju nc tion

Thick O xide

Si W afer

Ju nc tion

LPCVD O xide

Si W afer

G ate M etal

G ate Dielectric

Si W afer

G ate M etal

G ate D ielectric

Contact M etal

a )

b )

c )

d )

Figure 2.3. Schematic illustration of non-self aligned gate process: (a) Grow and pattern 1000 Å thick oxide and form junction; (b) Deposit LPCVD oxide over diffusions and pattern gate and contact regions; (c) Deposit gate dielectric and electrode; (d) Pattern and etch gate electrode/dielectric and deposit and pattern contact metal.

38

CHAPTER 3

Etching of High K Gate Dielectrics and Gate Metal Candidates

3.1 Introduction

As device dimensions are scaled down to the sub micron regime, problems arise

due to limitations of the materials and processes used in conventional MOSFET

fabrication. According to the International Technology Roadmap for Semiconductors

(ITRS) [1], the equivalent oxide thicknesses required for the 50 and 70 nm technology

nodes are 0.7 and 1.0 nm, respectively. At these thickness, pure SiO2 exhibits high gate

leakage currents. The use of higher dielectric constant (K) insulators can potentially

reduce this leakage since they use physically thicker dielectrics while maintaining the

required capacitance. Metal gate electrodes also are needed to minimize dopant

depletion, boron penetration and to lower the sheet resistance of gate lines. Accordingly,

high K gate dielectrics and metal gates are being widely studied for next generation

devices, especially for low-power applications [1-13]. Use of these new materials

requires the development of new integration processes, including selective etching of the

high K gate dielectrics and the metal gate electrodes [13]. First it is necessary to etch the

gate metals stopping on the high K dielectric. In some cases the gate electrode may be

composed of two layers of metal, e.g. W on Ru. Then it is necessary to etch the high K

dielectric layers and stop on the underlying silicon.

This chapter reports reactive ion etching (RIE) and wet etching of HfO2, ZrO2,

La2O3 and Y2O3 high K dielectrics and Ru, RuO2, Pt, Ta and TaN gate electrode

39

materials. Here we report etching process that were successfully developed in order to

fabricate NMOS and PMOS devices. For large area devices some materials were able to

be wet etched; most however, required the development of new dry etching processes.

3.2 Experimental Procedures

All the etching experiments presented in this paper were part of an actual device

fabrication process. A non-self aligned gate process, as described in chapter 2, has been

used to fabricate devices having a variety of high K gate dielectrics and gate metals [2].

Following the active area patterning and junction formation, the high K gate dielectrics

and gate metals were deposited. To replace n+ and p+ poly-silicon and maintain scaled

performance, it is necessary to identify pairs of metal electrodes with workfunctions that

are within 0.2 eV of the conduction and valance band edges of Si [9]. Candidates having

these workfunctions include Pt, RuO2 and Ru for PMOS and TaN and Ta for NMOS [11-

14]. Table 3.1 summarizes the high K dielectric and gate materials evaluated in this

study and their deposition methods.

Two different RIE systems were used to dry etch the gate stacks; A SEMI Group

100TP and a Plasma Therm SLR720. Both the 100TP and the SLR720 systems used

parallel plate electrodes with 13.56 MHz radio frequency (rf) power to generate the

plasma. 100TP system had a plate spacing of 4.5 cm and a water-cooled 50 in2 Al

cathode. The system was pumped by a turbo molecular pump backed by a mechanical

pump. The etching cathode of SLR720 system was an 11 inch diameter anodized,

aluminum electrode with a bare aluminum center. This system had a load lock and a 400

liter/second turbo molecular pump to provide a plasma chamber base pressure

40

Table 3.1. Deposition methods and conditions for high K dielectric and gate electrodes candidates Materials Deposition Method Deposition Condition

HfO2 DC Magnetron Sputtering(PVD) Sputtering at 20°C for 10 sec ZrO2 Reoxdiation at 500°C in N2 for 40 sec HfO2 Rapid Thermal CVD (RTCVD) At 500°C for 3 min using O2 and ZrO2 C16H36HfO4/C16H36O4Zr HfO2 Metal Organic CVD (MOCVD) 350°C using HF(NO3)4 ZrO2 HfO2 Jet Vapor Deposition (JVD) Mixture of Hf/Zr and O2 jet vapor at ZrO2 350°C Y2O3 Remote Plasma Enhanced CVD

(RPECVD) At 400°C using O2 and Y(tmhd)3

La2O3 Molecular Beam Epitaxy (MBE) La was evaporated in O2 ambient at 900°C

RuO2/Ru/Ta/W

RF Magnetron Sputtering At 100 W in Ar ambient

Pt DC Magnetron Sputtering At 250W in Ar ambient TaN Reactive Sputtering At 200 W in Ar ambient

below 2x10-6 torr.

Ta/W gate electrodes were dry etched in the 100TP system using CHF3/O2 gas

mixture. For Ru/W gate electrodes, W was first etched, using SF6/O2 in the 100TP

system; then the SLR720 etcher was used to etch Ru with a Cl2/O2 plasma. The etch rate

of photoresist was measured using an optical interferometer manufactured by

NANOMETRICS, INC (Model 010-0180). Sheet resistance and ellipsomety were used

to monitor the etch rates of metal and dielectric films, respectively.

41

3.3 Results and Discussion

3.3.1 Metal Gate Electrode Etching

3.3.1.1 Platinum

Wet etching of Pt was performed in diluted aqua-regia (H2O:HCl:HNO3 = 4:3:1).

One of the major concerns of Pt etching was photoresist stability. During etching of a

100 nm layer of Pt, about 40% of the photoresist was removed, and the adhesion between

the photoresist and Pt was lost. In order to circumvent the adhesion problem, the

photoresist was periodically re-baked (115°C, 5 minutes). Rebaking after 10 minutes of

etching at 45°C and 1 min at 80°C was satisfactory. The aqua-regia etch rate was

strongly dependent on temperature. To etch a 100 nm thick Pt film took 55-65 and 3.5-

4.0 minutes at 45°C and 80°C, respectively, corresponding to an Arrhenius activation

energy of 0.77 eV/K. The etch rate can be expressed by the following equation;

Pt Etch Rate = 2.62 x 1012 exp (-0.77 eV/kT) (nm/min)

where k is Boltzmann’s constant .

After the gate level lithography, a standard photoresist descum (300 Watts, 1 min

of O2 plasma) was performed. During this descum step, it was determined that Pt

oxidized. This thin layer of oxide on the surface inhibited aqua-regia etching. In order

to remove the oxide layer, Ar+ ion milling was done in the 100TP RIE system (80 Watts,

20 sccm) at 60 mtorr for 3 minutes. After the ion milling, wet etching was restored and

the Pt etch rate increased to 6-6.5 nm/min. Figure 3.1. shows Auger electron

spectroscopy (AES) of Pt films: after deposition, after photoresist decsum and after ion

milling. An oxygen peak clearly appeared after the photoresist descum, while subsequent

Ar+ ion milling completely removed the peak. This ion milling step also eroded

42

the photoresist, reducing the gate length by about 150 nm. Actually ion milling

significantly enhanced the Pt etching rate compared to the etch rate of as-deposited film.

As shown in Figure 3.1, a small oxygen peak is apparent in the as-deposited Pt film after

storage in air for a month, which may explain its lower etch rate.

3.3.1.2 Tantalum Nitride

Diluted commercially available TaN etchant (HNO3:HF:H2O = 4:1:5) was used to

etch TaN gate. Similar to Pt etching in aqua-regia, the adhesion between the TaN and

photoresist was degraded with this etch. Re-baking at 115 ºC for 5 min after every 25

seconds of etching was required to maintain patterns. The nitrogen content in the film

was found to play a major role in the etch rate of the film. Films from two different

deposition runs, performed with nominally the same deposition conditions, had sheet

resistances (for 150 nm film) that differed by a factor of two, and the etch rates differed

by more than 10 %. X-ray photoelectron spectroscopy (XPS) was performed on wafers

from the two runs as shown in Figure 3.2. The relative nitrogen concentrations of the low

and high sheet resistance wafers were 53% and 74%, respectively, as summarized in

Table 3.2. This work shows that as the nitrogen content in the film increased, the

resistivity and the etching rate also increased. Min et al. also demonstrated that as the

nitrogen content in the film is increased, the resistivity of the film also increases [15], but

this is the first report, to our knowledge, of the effect of N concentration on etch rate.

Since the TaN wet etchant contains HF and HNO3, it can etch not only the TaN film but

also many oxide dielectrics and the silicon junction beneath the dielectric. A cross-

43

Table3.2. Etch rate, resistivity and their corresponding nitrogen content

Run Rs (Ω/ ) ρ (µΩ-cm) Etch Rate (nm/sec) N Content (atomic %)1 ~8.5 140 2.7-2.9 53% 2 ~18.3 284 3.2-3.4 74%

sectional TEM picture of an overetched transistor is presented in Figure 3.3 (a). The field

oxide layer which should be at the edge of the TaN layer is not observed. This layer,

along with some other junctions, disappeared during the etching of the TaN layer. The

high roughness of the substrate further confirms overetching of the TaN and oxide layers

and into the surface of the silicon substrate. The gate oxide layer under the TaN

electrode, about 1 nm thick, is continuous. Magnified images at the TaN edges are

presented in Figure 3.3 (b) and (c). The bright layer observed in the top of the substrate

near the TaN edges is due to amorphisation occurring during the FIB specimen

preparation. The top of this bright layer represents the substrate surface. It shows that

etching inside the silicon occurred resulting in a smooth surface near the TaN (up to ~

500 nm away from the edge) and a very rough surface further away.

3.3.1.3 Ruthenium Oxide

Dry etching processes were developed for RuO2, Ru and W/Ru and W/Ta gate

electrodes. It has been reported that etching of RuO2 is possible by oxygen ion assisted

etching through the formation of volatile RuO3 and RuO4 [16-20]. The problem with

oxygen plasma etching is its poor selectivity to photoresist. Several researchers have

reported that the addition of fluorine to oxygen increases the RuO2 etch rate while

suppressing photoresist etching [18,20,21]. Figure 3.4 shows the etch rates of RuO2 and

44

photoresist (Shipley 510A) in O2/CHF3 plasma as a function of CHF3/(CHF3+O2) ratio.

As shown in Figure 3.4, the RuO2 etch rate was found to be dependent on the CHF3

content, indicative of a chemical etching. Addition of 2.5% CHF3 increased the etch rate

of RuO2 by 10%. The etch rate decreased at higher CHF3 flow rate. Apparently, a small

amount of CHF3 dramatically increases the chemically active species to enhance the etch

rate, but high CHF3 gas concentrations decrease the etch reaction by diluting the oxygen

concentration. This type of fluorine concentration dependent etch rate behavior was

observed previously [18,20]. Since photoresist etching during the oxygen plasma was a

major concern, the photoresist etch rate was also monitored as shown in Figure 3.4. The

photoresist etch rate continuously decreased as the CHF3 flow rate increased. The

maximum RuO2/photoresist etch rate ratio (~0.2) occurred at an O2/CHF3 (20 sccm/0.5

sccm) gas mixture at 40 mtorr and 150 Watts.

3.3.1.4 Ruthenium, Tungsten and Tantalum

In contrast to RuO2 etching, the etch rates of Ru electrodes in O2 and O2+CHF3

gases were very slow (2~3 nm/min). To etch Ru films, mixtures of chlorine and oxygen

gas were tested. Figure 3.5 shows the etch rate of Ru as a function of chlorine addition,

where a three times enhancement of etch rate was observed at about 4 % chlorine.

Nevertheless this etch rate was considerably slower than that of photoresist. To avoid

using a hardmask, our strategy was to employ a laminated gate of a thin Ru layer (3 nm)

covered with a thicker W film (100 nm). A high etch rate for W (> 50 nm/min) was

obtained by using a SF6/O2 (18 sccm/2 sccm) gas mixture at 40 mtorr and 150 Watts (V~-

235V). The same etch recipe was used to etch Ta electrodes with an etch rate of ~25

45

nm/min. Since Ta has a tendency to form oxide on its surface, during annealing, Ta (50

nm) was capped with W (50 nm) in a similar manner as Ru/W electrodes. Scanning

electron microscope (SEM) observations were used to investigate the Ru/W and Ta/W

gate stack etch profile. Examples of SEM micrographs are given in Figure 3.6. As

shown in the figures, a smooth SiO2 surface is visible and no undercutting is observed.

Detailed etching process and results for different gate electrodes are summarized in Table

3.3.

Table 3.3. Optimized etching recipes for metal gate electrode candidates

Gate Metals Type Etchant Conditions Etch Rate Pt (MBE) Wet H2O:HCl:HNO3 = 4:3:1 45 ºC

1.5-2.0 n/min

TaN (PVD) Wet H2O:HNO3:HF=7.35:0.6:2.05

20 ºC

2.7-3.3 n/min

RuO2(PVD) Dry O2/CHF3(20sccm/0.5 sccm) 40 mtorr, 150 Watts

~40 nm/min

Ru (PVD) Dry O2/Cl2 (20 sccm/1 sccm) 15 mtorr, 150 Watts

2~5 nm/min

W (PVD) Dry SF6/O2 (18 sccm/2 sccm), 40 mtorr, 150 Watts

> 50 nm/min

Ta (PVD) Dry SF6/O2 (18 sccm/2 sccm), 40 mtorr, 150 Watts

~25 nm/min

3.3.2 High K Dielectric Etching

The etching characteristics of high K gate dielectrics depended not only on the

materials, but also on the deposition system, substrate pretreatment and post deposition

anneal conditions. First, all the dielectrics were screened by wet etching in BOE (10%

HF) to see if they gave a reasonable etch rate. RPECVD Y2O3 and JVD HfO2, as well as

46

PVD and MBE ZrO2 etched in BOE at 20° C. Those dielectrics, which were not etched

by BOE (PVD, RTCVD and MOCVD HfO2 and MBE La2O3), received a dry ion-milling

etching process in at Ar 20 sccm, 15 mtorr. Dry etching was performed at room

temperature; complete film etching was confirmed by electrical contact measurements.

The etching process and etching rate for each dielectric are summarized in Table 3.4.

Table 3.4. Etch process and etch rate for high K gate dielectrics candidates

Dielectrics Type Etchant Conditions Etch Rate HfO2 (PVD, RTCVD,

MOCVD) Dry Ar (20 sccm)

15 mtorr, 150 Watts 2.5~3.0 nm

HfO2 (JVD) Wet BOE (10 %HF)

Atmosphere, 20 ºC ~3.5 n/min

ZrO2 (RTCVD) Dry Ar (20 sccm),


ZrO2 (PVD, MBE, JVD)

Wet BOE (10 %HF)


La2O3 (MBE) Dry Ar (20 sccm),


Y2O3 (RPECVD) Wet BOE (10 %HF)


3.3.3 Device Characteristics

NMOS and PMOS devices were successfully fabricated with various

combinations of high K dielectrics and metal gate electrodes. As a confirmation of good

process control, electrical characterization of these devices were performed. Figure 3.7

shows the subthreshold and linear characteristics of NMOS and PMOS devices,

respectively. As shown in Figure 3.7 (a), good subthreshod slope and low off state and

junction leakage was observed in MBE La2O3 + Ta/W gate stack where both the La2O3

47

and Ta/W were reactive ion etched using the processes discussed earlier. Figure 3.7 (b)

also shows good device characteristics with a PVD HfO2 + Ru/W gate stacks, where both

the dielectric and gate were dry etched. Id-VD Characteristics of other gate stack

combinations are shown in Figure 3.8. These good electrical characteristics confirmed

the good process control achievable with dry etching.

3.4 Summary and Conclusion

The etching characteristics of various high K dielectrics and metal electrodes

were investigated. Pt and TaN wet etching were performed in diluted aqua-regia

(H2O:HCl:HNO3 = 4:3:1) and TaN etchant (HNO3:HF:H2O = 4:1:5), respectively.

During the etching, photoresist was re-baked periodically to prevent adhesion loss. RIE

processes were developed for RuO2, Ru, Ru/W, and Ta/W gate electrodes. Etching of

RuO2 has been shown to occur by O2 ion assisted etching through the formation of

volatile RuO3 and RuO4. However O2 plasma etching has poor selectivity to the

photoresist. In order to enhance etch selectivity, a small amount of CHF3(2.5%) was

added. In contrast to RuO2 etching, the etch rate of Ru electrodes in pure oxygen was

negligible. Etch rates as high as 6.7 nm/min could be obtained by the addition of a few

percent Cl2 to the etch gas. Since this etching rate was considerably slower than that of

photoresist, our strategy was to employ a laminated gate of a thin Ru layer (3 nm)

covered with a thicker W film (100 nm).

The etching behaviors of high K gate dielectrics depended not only on the

materials, but also the deposition methods. RTCVD ZrO2 required dry etching but other

ZrO2 films could be wet etched in BOE. JVD HfO2 etched in BOE, while other

48

HfO2 films received dry etched. Y2O3 and La2O3 were wet etched in BOE and ion

milling, respectively.

49

3.5. References

[1] International Technology Roadmap for Semiconductors (ITRS), 2001 Edition, Dec.,

2001, Semiconductor Industry Association

[2] I. Kim, S.K. Han, W. Kiether, S. J. Lee, C.H. Lee, H.F. Luan, Z. Luo, E. Rying, Z.

Wang, D. Wicaksana, W. Zhu, J. Hauser, A. Kingon, D.L. Kwong, T.P. Ma, J.P. Maria,

and C.M. Osburn, “Device Fabrication and Evaluation of Alternative High-K Dielectrics

and Gate Electrodes Using a Non-Self Aligned Gate Process,” Proceedings of the

Symposium on Rapid Thermal and Other Short-Time Processing Technologies II, The

Electrochemical Socieity, PV 01-9, p.211

[3] E.P. Gusev, D.A. Buchanan, E. Chrtier, A. Kumar, D. DiMaria, S. Guha, A.

Callegari, S. Zafar, P.C. Jamison, D.A. Neumayer, M. Copel, M.A. Gribelyuk, H. Okon-

Schmidt, C. D’Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L-A. Ragnarsson, P.

Ronsheim, K. Rim, R.J. Fleming, A. Mocuta and A.Ajmera, “Ultrathin High-K Gate

Stacks for Advanced CMOS Devices,” IEDM Tech. Dig., p.451 (2001)

[4] S.J. Lee, C.H. Lee, Y.H. Kim, H.F. Luan, W.P. Bai, T.S. Jeon and D.L. Kwong,

“Dual-Poly CVD HfO2 Gate Stack for Sub-100 nm CMOS Technology,” Extended

Abstracts of International Workshop on Gate Insulator., p.80 (2001)

[5] W. Zhu and T.P. Ma, “HfO2 and HfAlO for CMOS: Thermal Stability and Current

Transport,” IEDM Tech. Dig., p.463 (2001)

[6] C. Hobbs, H. Tseng, K. Reid, B. Taylor, L. Dip, L. Herbert, R. Garcia, R. Hegde, J.

Grant, D. Gilmer, A. Franke, V. Dhandapani, M. Azrak, L. Prabhu, R. Rai, S. Bagchi, J.

Conner, S. Backer, F. Dumbuya, B. Nguyen and P. Tobin, “80 nm Poly-Si Gate CMOS

with HfO2 Gate Dielectric,” IEDM Tech. Dig., p.651 (2001)

50

[7] K. Onishi, C.S. Kang, R. Choi, H.-J. Cho, S. Goplan, R. Nieh, E. Dharmarajan and

J.C. Lee, “Reliability Characteristics, Including NBTI, of Polysilicon Gate HfO2

MOSFET’s,” IEDM Tech. Dig., p.659 (2001)

[8] Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J. Lim, B.

Foran, F. Shaapur, A. Agarwal, P. Lysaght, G.A. Brown, C. Yong, S. Borthakur, H.-J. Li,

B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R.W. Murto, A. Hou, H.R.

Huff, E. Shero, C. Pomarede, M. Givens. M. Mazanec and C. Werkhoven, “Conventioal

n-Channel MOSFET Devices using Single Layer HfO2 and ZrO2 as High-K Gate

Dielectrics with Polysilicon Gate Electrode,” IEDM Tech. Dig., p.455 (2001)

[9] Z. Luo, T.P. Ma, E. Cartier, M. Coppel, T. Tamagawa, B. Halpern, “Ultra-thin ZrO2

(or Silicate) with High Thermal Stability for CMOS Gate Applications,” 2001

Symposium on VLSI Tech. Dig., p.135 (2000)

[10] I. De, D. Johri, A. Srivastava, C.M. Osburn, “Impact of Gate Workfunction on

Device Performance at the 50 nm Technology Node”, Solid-State-Electronics, Vol 44,

No. 6, p. 1077 (2000)

[11] V. Misra, G. Heuss and H. Zhong, “Advanced Metal Electrodes for High-K

Dielectrics, ” MRS Workshop, New Orleans, June1-2, p.5 (2000)

[12] H. Zhong, G. Heuss and V. Misra, “Electrical Properties of RuO2 Gate Electrodes

for Dual Metal Gate Si-CMOS,” IEEE Electron Dev. Lett., 21, p.593 (2000)

[13] Y.H. Kim, C.H. Lee, T.S. Jeon, W.P. Bai, C.H. Choi, S.J. Lee, L. Xinjian, R.

Clarks, D. Roberts and D.L. Kwong, “High Quality CVD TaN Gate Electrode for Sub-

100 nm MOS Devices,” IEDM Tech. Dig., p.667 (2001)

[14] G.D. Wilk, R.M. Wallace and J.M. Anthony, “High-K Gate Dielectrics:

51

Current Status and Materials Properties Considerations,” J. Appl. Phys., 89, p.5243

(2001)

[15] K.-H. Min, K.-C. Chun and K.-B. Kim, “ Comparative Study of Tantalum and

Tantalum Nitride as a Diffusion Barrier for Cu Metallization,” J. Vac. Sci. Technol. B.,

14, p.3263 (1996)

[16] T. Yunogami, and K. Nojiri, “Anisotropic Etching of RuO2 and Ru with High

Aspect Ratio for Gigabit Dynamic Random Access Memory,” J. Vac. Sci. Technol. B.,

18, p. 1911 (2000)

[17] E.-J. Lee, J.-W. Kim, and W.-J. Lee, “Reactive Ion Etching Mechanism of RuO2

Thin Film in Oxygen Plasma with the Addition of CF4, Cl2, and N2”, Jpn. J. Appl. Phys.,

37, p. 2634 (1998)

[18] Y.-S. Kim, R.H. Rampersad, and G.R. Tynan, “The Effect of BCl3 addition on

RuO2 Etching in M = 0 Helicon Reactor”, Jpn. J. Appl. Phys., 37, p. 502 (1998)

[19] W. Pan, and S.B. Desu, “Reactive Ion Etching of RuO2 Thin Film Using the Gas

Mixture O2/CF3CFH2”, J. Vac. Sci. Technol. B., 12, p. 3208 (1994)

[20] S. Saito, and K. Kuramasu, “Plasma Etching of RuO2 Thin Film”, Jpn. J. Appl.

Phys., 31, p. 135 (1992)

52

100 200 300 400 500

Kinetic Energy (eV)

Pt Peak

Oxygen Peak

Measured at 3 KeVa)

b)

c)

Figure 3.1. AES analysis of: a) as deposited Pt film; (b) Pt film after standard descum (300 Watts, 1 min of O2 Plasma); (c) Pt film after Ar+ ion milling (80 Watts, 20 sccm at 60 mtorr for 3 minutes).

53

Figure 3.2 XPS analysis of : a) TaN film on 4 inch wafer (low nitrogen concentration); and b) TaN film on 6 inch wafer (high nitrogen concentration.

54

Figure 3.3. The Cross-section TEM view of the transistor with SiO2/TaN gate stack: (a) overall view, (b) magnified TaN left edge view and (c) magnified TaN right edge view. * TEM: Courtesy of IMAC.

(a)

(b) (c)

55

24

26

28

30

32

34

80

100

120

140

160

180

0 5 10 15 20

Ru

PR

RuO

2 Etc

h R

ate

[nm

/min

] PR

Etch R

ate [nm/m

in]

CHF3/ (CHF

3 + O

2) [%]

Figure 3.4. Etch rate of RuO2 film in O2/CHF3 plasma as a function of CHF3/(O2+CHF3) ratio.

2

3

4

5

6

7

0 2 4 6 8 10 12

Ru

Etc

hing

Rat

e [n

m/m

in]

C l2/ (C l

2 + O

2) [% ]

Figure 3.5. Etch rate of Ru film in O2/Cl2 plasma as a function of Cl2/(O2+Cl2) ratio.

56

Figure 3.6. a). SEM micrograph Ru/W film etched in O2/Cl2 (20 sccm/1 sccm), at 40 mtorr, 150 Watts. Figure 3.6. b). SEM micrograph Ru/W film etched in SF6/O2 (18 sccm/2 sccm), at 40 mtorr, 150 Watts.

(

(

57

10-8

10-7

10-6

10-5

10-4

0 0.2 0.4 0.6 0.8 1 1.2

I D [A

]

VG

[V]

La2O

3 + Ta/W

Gate

100 mV/Dec

W = L=50µmEOT=1.5 nm

Figure 3.7. a) NMOS subthreshold Characteristics of MBE La2O3 with Ta/W gate.

1 10-9

2 10-9

3 10-9

4 10-9

5 10-9

6 10-9

7 10-9

1 1.2 1.4 1.6 1.8

I D [A

/ µµ µµm

]

-VG

[V]

HfO2 + Ru/W Gate

Figure 3.7. b) PMOS ID-VG Characteristics of PVD HfO2 with Ru/W gate.

58

0 100

2 10-4

4 10-4

6 10-4

8 10-4

1 10-3

0 0.2 0.4 0.6 0.8 1 1.2

I D [A

]

VD [V]

VG=1.0V

VG=1.2V

VG=0.8V

VG=0.6V

W=10µµµµmL=0.6µµµµm

(a)

Figure 3.8. a). Id-Vd characteristics of La2O3-TaN NMOS device.

0 100

2 10-5

4 10-5

6 10-5

8 10-5

1 10-4

1.2 10-4

-1.2 -1 -0.8 -0.6 -0.4 -0.2 0

VG=-2.0V

VG=-1.8V

VG=-1.6V

VG=-1.4V

VG

=-1.2V

VD [V]

I D [A

]

W=3µµµµ mL=0.6µµµµm

(b)

Figure 3.8. b). Id-Vd characteristics of HfO2 (JVD)-Pt PMOS device.

59

CHAPTER 4

Device Characterizations of Alternative Gate Stacks Using the Non-Self Aligned Process

4.1 Introduction

The non-self aligned gate process has been used to fabricate NMOS and PMOS

devices having a variety of high K gate dielectrics and gate electrodes produced in the

SRC/SEMATECH Front End Processing Research Center [1]. After the devices were

fabricated, their electrical characteristics, capacitance vs. voltage (C-V), gate leakage

current (Ig-Vg), drain current vs. gate voltage (Id-Vg) and drain current vs. drain voltage

(Id-Vd) were measured. After initial device measurements were made, devices having

HfO2 went through the post metallization anneal (PMA) using two different source gases,

Hydrogen and Deuterium, to quantify the effect of this anneal.

4.2 Experimental Procedures

A gate last process, described in chapter 2, was used to fabricate devices having a

variety of high K gate dielectrics and gate metals [3]. The deposition methods and

conditions are summarized in Table 4.1. [2-11]. Gate oxide was deposited on control

wafers in the RTP-I system in NCSU. Baseline control oxide was formed by rapid

thermal oxidation in N2O (N2, 880°C 50 torr, 30 sec). Multiple deposition sources were

used to deposit HfO2 and ZrO2: Metal organic chemical vapor deposition (MOCVD) was

used to deposit HfO2 and Jet vapor deposition (JVD), physical vapor deposition (PVD)

and rapid thermal chemical vapor deposition (RTCVD) were used to deposit for both

60

Table 4.1. Deposition sources and their deposition methods for high K dielectric [2-11] Materials Deposition Method and Source Deposition Condition

HfO2 DC Magnetron Sputtering Sputtering at 20°C for 10 sec ZrO2 (J.Lee’s Group ) [2,3] Reoxdiation at 500°C in N2 for 40 sec HfO2 Rapid Thermal CVD At 500°C for 3 min using O2 and /ZrO2 (D.L. Kwong’s Group) [4,5] C16H36HfO4/C16H36O4Zr HfO2 Metal Organic CVD 350°C using HF(NO3)4/ Zr(NO3)4 /ZrO2 (Campbell’s Group) [9] HfO2 Jet Vapor Deposition Mixture of Hf/Zr and O2 jet vapor at ZrO2 (T.P. Ma’s Group) [7-9] 350°C Y2O3 Remote Plasma Enhanced CVD

(Parson’s Group) [10] At 400°C using O2 and Y(tmhd)3

La2O3 Molecular Beam Epitaxy (Kingon’s Group) [11]

La was evaporated in O2 ambient at 900°C

HfO2 and ZrO2 gate dielectrics. MOCVD (S. Campbell’s group at University of

Minnesota) of HfO2 was performed at 350°C, 4.7 torr with the solid Hf(NO3)4 precursor

[9]. For PVD of HfO2 and ZrO2 (J. Lee’s group at UT Austin), NH3 surface nitridation

(700°C in NH3 ambient for 30 sec at 1 atm) was performed prior to the dielectric

deposition [2,3]. Hf and Zr were deposited by DC magnetron sputtering at 20°C, 30

mtorr for 10 sec. After the sputtering, re-oxidations were preformed in N2 ambient at

600°C for 40 sec and 5 min at 500°C for HfO2 and ZrO2, respectively. NH3-based

interface layers were grown at 700 °C for 10 sec prior to deposition of the high k

dielectric. For JVD (T.P. Ma’s group at Yale) of HfO2 and ZrO2, Zr and Hf vapor were

generated by DC sputtering in Ar ambient at 1 torr, then atomic O2 was generated by a

microwave discharge sustained in a fast flow of O2 through a quartz nozzle [7]. During

the deposition, the substrate was exposed to a jet vapor at 200°C, and post deposition

annealing was performed at 550°C for 20 min. in H2 ambient [6]. RTCVD (D.L.

Kwong’s group at UT Austin) of HfO2 and ZrO2 films were deposited at 500°C for 3

61

min using O2 + C16H36HfO4 and at 500 °C for 2 min using O2 + C16H36O4Zr precursors,

respectively [4,5]. Following the high K dielectric depositions, in-situ post-deposition

annealings were performed in an N2 ambient at 700 – 900 °C for 30 sec for both films.

For MBE of La2O3, La was first deposited by reactive co-evaporation, and then a La2O3

film was grown in an O2 ambient of 2e-5 torr at 600°C [11]. Remote plasma enhanced

chemical vapor deposition was used to prepare Y2O3. O2 (100 sccm)+Y(tmhd)3 was used

as a precursor, and deposition was performed at 400°C, 200 mtorr and 10 Watts [10].

The poly-silicon gate electrodes were prepared by two different methods: thermal

CVD using SiH4+O2 at 550°C for 100 min and LPCVD using SiH4 at 625°C, 135 mtorr

for 27 min to have 200 nm thick poly-silicon. After the poly-silicon depositions,

appropriate dopant was implanted and activated at 950°C for 1min. Ru, RuO2, Ta and W

films were deposited by RF magnetron sputtering. Commercially available TaN (reactive

Sputtering by UHV Sputtering) was used, and Pt was deposited by DC magnetron

sputtering. Table 4.2 summarizes the deposition methods of gate electrode materials. A

forming gas annealing (20 min. 400 ºC) was performed in two different ambients:

Table 4.2. Deposition sources and their deposition methods for gate electrodes [14-17]

Materials Deposition Method and Source Deposition Condition Polysilicon LPCVD (NCSU) Si2H6 at 630°C, 135 mtorr Polysilicon Thermal CVD (UT Austin) SiH4 + O2 at 550°C RuO2/Ru/

Ta/W RF Magnetron Sputtering

(Misra’s Group) At 100 W in Ar ambient

Pt DC Magnetron Sputtering (Kingon’s Group)

At 250W in Ar ambient

TaN Reactive Sputtering (UHV Sputtering, Inc.)

At 200 W in Ar ambient

62

Hydrogen (H2) or Deuterium (D2) in N2. After the device fabrication, C-V, Ig-Vg, Id-Vg

and Id-Vd characteristics were measured. Key MOS device parameters, such as EOT,

substrate doping, channel mobility, number of interface charges and the interface

roughness scattering parameter (L•H product), were extracted.

4.3 Results and Discussion

4.3.1 Device Characteristics of Control Oxide

From the CV data of Figure 4.1, control oxide thicknesses of 1.06 and 1.19 nm

were extracted for NMOS and PMOS, respectively. As shown in the figure, the

capacitance deviates from its modeled value for high gate bias. This deviation is possibly

due to the high gate leakage current, which is commonly observed in oxides less than 1.5

nm thick. Gate leakage current and channel mobility for NMOS oxide control dielectrics

are shown in Figures 4.2 and 4.3, respectively. The measured gate leakage of oxide

controls was in good agreement with published theories [12,13]. The channel mobility of

the thin oxide control fit the universal mobility curve well for reasonable interface

scattering charge, Nif = 4.8e10/cm2 and surface roughness parameters, LxH = 30 Å2.

4.3.2. Capacitance Voltage (C-V) and Gate Leakage (Ig-Vg) Characteristics of HfO2

and ZrO2

As shown in Figures 4.4 and 4.5, reasonably good C-V characteristics were

observed for HfO2 (JVD) and ZrO2 (JVD and RTCVD) dielectrics except for the devices

which had a TaN gate. A large die-to-die variability was observed with TaN gated

capacitors. This is probably due to the large over-etch problems associated with TaN

63

film described in chapter 3. In addition to that, it was difficult to make a good contact to

the TaN gate; poor contacts hindered accurate C-V measurement and its analysis. Using

a non-linear least square fitting program with quantum mechanical effect corrections

(Hauser program)[18,19] was used to extract key MOSFET parameters, such as effective

oxide thickness (EOT), substrate doping, flat band voltage, number of interface trapped

charged, channel mobility and scattering parameters (Nif and L•H product). Table 4.3

summarizes the EOTs of the candidate materials. Although the targeted EOT was around

1 nm, the measured EOT values for the JVD HfO2 ranged from 1.28 to 2.25 nm with the

lowest value observed for TaN gate (NMOS). JVD and RTCVD ZrO2 had EOT ranging

form 1.86 to 2.62 nm.

To compare the gate leakage characteristics of each split, since the EOTs of each

split varied form sample to sample, the gate leakage currents were normalized by the

EOT. Figure 4.6 and 4.7 show the gate leakage characteristics of HfO2 and ZrO2 with

different gate electrodes. RTCVD HfO2 devices showed similar gate leakage currents as

Table 4.3. Equivalent oxide thickness of each dielectric (the values extracted from C-V

measurements).

Gate Electrode JVD HfO2 JVD ZrO2 RTCVD ZrO2 PVD HfO2

Al 1.85 nm 2.22 nm N/A N/A

NMOS TaN 1.28 nm N/A 1.86 nm N/A

Poly-silicon N/A N/A N/A 1.20 nm

Al 2.25 nm 2.07 nm N/A N/A

PMOS Pt 1.63 nm 2.62 nm N/A N/A

Ru/W N/A N/A N/A 0.90 nm

64

previously reported [4], while higher gate leakage was observed with JVD HfO2

(0.1A/cm2 versus 10-2A/cm2 at 1.2V/nm) [20]. For ZrO2 dielectric, JVD ZrO2 had the

same gate leakage, and RTCVD ZrO2 had slightly higher leakage than previously

reported [5,7]. The RTCVD ZrO2 showed slightly higher gate leakage current than HfO2,

but both dielectrics met the 2001 ITRS specifications for high performance (10A/cm2 at

1.2V) [21].

Figures 4.8 and 4.9 show the C-V and Ig-Vg characteristics of PVD HfO2 with

poly-silicon and metal gate electrodes. As shown in Figure 4.8, extracted EOT was

thinner for Ru/W gate electrode (0.9 nm) than poly-silicon (1.2.nm). Since the poly-

silicon gates went through the high temperature activation (950 ºC for 1 minutes), the

EOT difference might be attributed to this additional thermal cycle. Gate leakage

currents of PVD HfO2 with poly-silicon and with Ru/W gate electrodes are shown in

figures 4.9 (a) and (b), respectively. Even though the devices with Ru/W gates had the

lower EOT, they showed lower gate leakage than poly-silicon gated devices. Large

device-to-device gate leakage variations were observed with poly-silicon gates. The

result indicates HfO2 may degrade during the poly-silicon process; the details of this

topic will be discussed in chapter 5.

4.3.3. Device Characteristics

Figures 4.10 –20 show the device characteristics of various experimental splits.

Due to the high gate leakage, some device splits showed considerable die-to-die

variability and high leakage currents which precluded precise extraction of device

parameters. Figures 4.10 and 11 show subtreshold characteristics of HfO2. Good

65

subthreshold slopes (90 – 95 mV/dec) were observed with NMOS JVD, RTCVD (figure

4.10 (a)) and PVD HfO2 devices (figure 4.11 (a)). Unfortunately, as shown in figure 4.10

(b) and 4.11 (b), PMOS HfO2 devices had a very high threshold voltage and

correspondingly low drive current. Futhermore, PMOS HfO2 devcies showed high

junction leakage current which precluded extraction of a meaningful subthreshold slope.

The subthreshold characteristics of ZrO2 are shown in figure 4.12. As the figure

indicates, JVD ZrO2 devices having Al gates showed very high subthreshold slope (144

mV/dec) and large die-to-die threshold voltage variability. Compared to HfO2 devices,

JVD ZrO2 showed higher subthreshold slope and lower channel current. Due to the high

gate leakage current in the negative direction, RTCVD ZrO2 devices showed an

anomalously low subthreshold slope (60 mV/dec). High gate leakage current was also

found in devices with La2O3 dielectrics(figure 4.13). As shown in figure 4.13, this high

leakage current led to negative current at low drain bias, resulting in an unusually low

subthreshold slope.

Figures 4.21-24 show the channel mobility of various gate stacks. As shown in

figure 4.21 and 23, for NMOS and PMOS devices with substrate doping of 1.0x1018/cm3,

JVD HfO2 had a peak mobility of 239 cm2/V-s for NMOS and 36 cm2/V-s for PMOS.

This peak mobility was very close to the peak mobility (256 cm2/V-s) of control devices

with 1.1 nm oxide. Devices with RTCVD HfO2 dielectrics having poly-silicon gates

showed slightly lower peak mobility (214 cm2/V-s) than JVD HfO2. It is not clear

whether this slight difference is due to the differences in deposition systems or if other

factors, such as differences in post deposition annealing or pre-deposition cleaning could

make the difference. Regardless of their deposition methods or substrate types, HfO2

66

showed higher mobility than ZrO2. NMOS and PMOS mobility characteristics of PVD

HfO2 with poly-silicon gate are shown in figure 4.22 and 4.24, respectively. Even though

the peak mobility of PVD HfO2 was much less than JVD or RTCVD HfO2, direct

comparison could not be made since the substrate doping was much higher

(3.0x1018/cm3) for devices with PVD HfO2.

4.3.4. Effect of Forming Gas Anneal: H2 vs. D2

Figures 4.25 and 4.26 show the gate leakage and C-V characteristics before and

after H2 forming gas annealing, respectively. As the figures indicate, PVD HfO2 with

poly-silicon gates exhibited negligible change in gate leakage and C-V after the 400ºC H2

forming gas annealing. On the other hand, drastic changes were observed in Id-Vg and

mobility characteristics. The device current was increased significantly (figure 4.27), and

about 46% higher mobility (figure 4.28) was observed after the annealing. This mobility

improvement was analyzed in terms of reduced surface roughness scattering and reduced

interface scattering charges. Table 4.4 summarizes the number of interface charges and

the L•H product before and after H2 forming gas annealing. As a reference, the values

for high quality SiO2 is also given in Table 4.4. As seen in the table, even though H2

forming gas annealing of HfO2 significantly reduced the number of scattering centers, it

still had lower mobility than good SiO2.

As shown in figures 4.29 and 4.20, no significant change was observed in Ig-Vg

and C-V characteristics of before and after D2 annealing. Figure 4.31 compares device

characteristics after D2 and H2 annealing. Similar to H2 annealing, a drastic improvement

was observed with D2 annealing. D2 annealing gave a greater increase in device current

67

and mobility than H2. Superior mobility was observed with D2 annealing, as seen in

Figure 4.31. The peak mobility and its parameters (Nif and the L•H product) of after D2

and H2 annealing are given in Table 4.4. The result indicates that D2 annealing is much

more effective and its mobility value is 90% of that of control SiO2.

Table 4.4. Summary of peak mobility and universal mobility scattering parameters of

before and after D2 and H2 forming gas annealing. (substrate doping = 3x1018/cm3)

Parameter Before forming

gas annealing

After H2

Annealing

After D2

Annealing

SiO2 control

oxide

Peak mobility 34 cm2/V-s 81 cm2/V-s 108 cm2/V-s 115 cm2/V-s

Nif 1.2x1011/cm2 8x1010/cm2 5x1010/cm2 4.8x1010/cm2

L•H 65Å2 39 Å2 32.3 Å2 30 Å2

4.4. Conclusions

A non-self aligned gate process was used to fabricate devices having high K

dielectrics and metal gates. For most of the experimental splits, working devices were

obtained. But some devices showed large die-to-die variability and relatively large

interface charge, mainly due to the over-etching as described in chapter 3. Most of the

devices with HfO2 and ZrO2 met the high performance gate leakage specifications for

100 nm and 70 nm technology nodes. But most of the EOTs were thicker than the target

value (< 1 nm). PVD HfO2 devices having Ru/W gates showed the lowest EOT (0.9 nm).

JVD HfO2 has seen to give comparable mobility to SiO2 control devices, while ZrO2 was

inferior to SiO2 controls.

Both H2 and D2 forming gas annealing of PVD HfO2 resulted in

68

enhanced drive current and channel mobility: the effect is believed to be due to

eliminating interface states. D2 annealing was more effective than H2 and resulted in a

mobility which was 90% of that of SiO2 control oxide.

69

4.5. Reference

[1] I. Kim, S.K. Han, W. Kiether, S. J. Lee, C.H. Lee, H.F. Luan, Z. Luo, E. Rying, Z.

Wang, D. Wicaksana, W. Zhu, J. Hauser, A. Kingon, D.L. Kwong, T.P. Ma, J.P. Maria,

and C.M. Osburn, “Device Fabrication and Evaluation of Alternative High-K Dielectrics

and Gate Electrodes Using a Non-Self Aligned Gate Process,” Proceedings of the

Symposium on Rapid Thermal and Other Short-Time Processing Technologies II, The

Electrochemical Socieity, PV 01-9, p.211

[2] B.H. Lee, L. Kang, Wen-Jie Qi, R. Nieh, Y. Jeon, K. Onishi and Jack C. Lee,

“Ultra Thin Hafnium Oxide with Low Leakage and Excellent Reliability for Alternative

Gate Dielectric Application,” Tech. Dig. Int. Electron Device Meet., p.133 (1999)




[4] S.J. Lee, H.F. Luan, C.H. Lee, T.S. Jeon, W.P. Bai, Y. Senaki, D. Roberts and


Electrode,” Tech. Dig. Int. Electron Device Meet., p.31 (2000)

[5] C.H. Lee H.F. Luan, S.J. Lee, T.S. Jeon, W.P. Bai, Y. Sensaki, D. Roberts and

D.L. Kwong “MOS Characteristics of RTCVD ZrO2 and Zr Silicate Gate Dielectrics,”

Tech. Dig. Int. Electron Device Meet., p. 27 (2000)

[6] T.P. Ma, “Making Silicon Nitride a Viable Gate Dielectric,” IEEE Trans. Elec.

Dev., 45., p.680 (1998)

[7] Z.J. Luo, T.P. Ma, E. Cartier, M. Copel, T. Tamagawa, and B. Halpern, “Ultra-

Thin ZrO2 (or silicate) with High Thermal Stability for CMOS Gate Applications,” Symp.

70

On VLSI Tech. Dig., p.135 (2001)

[8] W. Zhu, T.P. Ma, T. Tamagawa, Y. Di, J. Kim, R. Carruthers, M. Gibson, and T.

Furakawa, “HfO2 and HfAlO for CMOS: Thermal Stability and Current Transport,

Tech. Dig. Int. Electron Device Meet., p.20.4.1 (2001)

[9] T. Ma, S.A. Campbell, R. Smith, N. Hoilien, H. Boyong, W.L. Gladfelter, C.

Hobbs, D. Buchanan, C. Taylor, M. Gribelyuk, M. Tiner, M. Coppel, and J.J.

Lee, “Group IVB metal oxides high permittivity gate insulators deposited from

anhydrous metal nitrates,” IEEE Trans. Elec. Dev., 48., p. 2348 (2001)

[10] D. Niu, W.Ashcraft, and G.N. Parsons, “Interface Properties of Yittrium Oxide

High Dielectric Constant Insulators Deposited by Oxygen Plasma Assisted Chemical

Vapor Deposition,” MRS Spring Meeting (April 2-5, 2002)

[11] J.P. Maria, D. Wicaksana, and A.I. Kingon, “High Temperature Stability in

Lanthanum and Zirconia-Based Gate Dielectrics,” J. Appl. Phys., 70, p. 3476 (2001)

[12] K.F. Schuegraf, C.C. King, and C. Hu, ”Ultra-thin Silicon Dioxide Leakage

Current and Scaling Limit,” Symp. On VLSI Tech. Dig., p. 18 (1992)

[13] S-H. Lo, D.A. Buchanan, Y. Taur and W. Wang, “Quantum-Mechanical

Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide

nMOSFET’s,” IEEE Electron Device Letters, Vol. 18, No. 5, p.209 (1997)

[14] V. Misra, G. Heuss and H. Zhong, “Advanced Metal Electrodes for High-K

Dielectrics, ” MRS Workshop, New Orleans, June1-2, p.5 (2000)

[15] H. Zhong, G. Heuss and V. Misra, “Electrical Properties of RuO2 Gate Electrodes

for Dual Metal Gate Si-CMOS,” IEEE Electron Dev. Lett., 21, p.593 (2000)

[16] Y.H. Kim, C.H. Lee, T.S. Jeon, W.P. Bai, C.H. Choi, S.J. Lee, L. Xinjian, R. Clarks,

71

D. Roberts and D.L. Kwong, “High Quality CVD TaN Gate Electrode for Sub-100 nm

MOS Devices,” Tech. Dig. Int. Electron Device Meet., p.667 (2001)

[17] G.D. Wilk, R.M. Wallace and J.M. Anthony, “High-K Gate Dielectrics: Current

Status and Materials Properties Considerations,” J. Appl. Phys., 89, p.5243 (2001)

[18] J. Hauser and K. Ahmed, “Characterization of Ultrathin Oxides Using Electrical C-

V and I-V Measurements,” AIP Conference Proceedings, p.235, Gaithersburg, MD, Mar.

23-27 (1998)

[19] J.R. Hauser, “Extraction of Experimental Mobility Data for MOS Devices,” IEEE

Trans. Elec. Dev., 43, 1981 (1996)

[20] W. Zhu, T. Tamagawa, X.W. Wang, B. Halpern and T.P. Ma, “Electrical Properties

of Ultra-Thin Hafnium Oxide Gate Dielectrics,” Semiconductor Interface Specialist

Conference Proceedings, Section 1.2 (2001)



72

0

0.5

1

1.5

2

2.5

3

-3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1

ExperimentalModel

C ( µµ µµ

F/cm

2 )

Vg (Volts)

(a)

EOT = 1.06 nm

0

0.5

1

1.5

2

2.5

-1.5 -1 -0.5 0 0.5 1 1.5

ExperimentalModel

C ( µµ µµ

F/cm

2 )

Vg(V)

EOT = 1.19 nm

(b)

Figure 4.1. High-frequency C-V characteristics of (a) NMOS capacitance and (b) PMOS capacitors.

73

10-3

10-2

10-1

100

101

102

103

-3 -2 -1 0 1 2 3

I g (A/c

m2 )

Vg (V)

W/L = 100 µµµµm/100 µµµµm EOT = 1.06 nm

Figure 4.2. NMOS Ig-Vg Characteristic of control oxide (EOT = 1.06 nm) from 100 µm x 100 µm capacitor.

74

0

50

100

150

200

6 105 8 105 1 106 1.2 106 1.4 106 1.6 106 1.8 106

dataModel

Mob

ility

(cm

2 /V-s

)

Field (V/cm)

1.06 nm OxideW/L = 10µµµµm/2.5µµµµm

Nif = 4.8 x 1010/cm2

HxL = 29.1 A2

(for W/L = 10.2 µµµµ/2.3 µµµµm)

Figure 4.3. NMOS Channel mobility of control oxide (Nif = 4.8 x1010/cm2, HxL = 29.1 Å2).

75

0

0.5

1

1.5

2

-2 -1.5 -1 -0.5 0 0.5 1 1.5V

G [V]

Cap

acita

nce

[ µµ µµF/

cm2 ] NMOS PMOS

*All Samples Pre-Deposition Cleaned by N2O

Al

AlPt

EOT = 1.85 nmEOT = 1.63 nm

EOT = 2.25 nm

Figure 4.4. C-V characteristics of JVD HfO2. Al samples received 600˚C 20min FG post-deposition anneal, while Pt samples got 600˚C, 20min N2 annealing.

76

0

0.5

1

1.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

PMOSNMOS

JVD-Al

Cap

acita

nce

[ µµ µµF/

cm2 ]

VG[V]

HF last for RTCVD sample, N2O for JVD Samples

JVD-PtRTCVD-TaN

EOT = 2.22 nm

EOT = 2.22 nmEOT = 1.86 nm

Figure 4.5. C-V curves of ZrO2 with different metal gates. RTCVD samples received, 900°C, 30sec N2 annealing while JVD samples got 550°C, 20min FG post-deposition annealing.

77

10-7

10-6

10-5

10-4

10-3

10-2

10-1

100

101

-1 -0.5 0 0.5 1

JVD-TaN

RTCVD-Poly

JVD-AlJVD-Pt

Field [V/nm]

I G [A

/cm

2 ]

NMOS PMOS

EOT = 1.85 nm

EOT = 1.63 nm

Figure 4.6. Gate leakage characteristics of HfO2 with different gate electrodes.

78

10-7

10-6

10-5

0.0001

0.001

0.01

0.1

1

10

-1 -0.5 0 0.5 1

RTCVD-TaN

JVD-TaN

JVD-Al JVD-Pt

JVD-Al

Field [V/nm]

I G [A

/cm

2 ]

NMOS PMOS

EOT = 2.22 nm

EOT =1.86 nm

EOT = 2.22 nm

Figure 4.7. Gate leakage characteristics of ZrO2 with different gate electrodes.

79

0

0.5

1

1.5

2

2.5

3

3.5

-3 -2 -1 0 1 2 3

C [ µµ µµ

F/cm

2 ]

VG [V]

NMOS PMOS

Ru/W

Poly-SiEOT = 1.2 nm

EOT = 0.9 nm

Figure 4.8. C-V characteristics of PVD HfO2 with poly-silicon (NMOS) and Ru/W (PMOS) gate electrodes.

80

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-1 -0.8 -0.6 -0.4 -0.2 0

I G (A

)

VG (V)

Cap Area 104µµµµm2

(a)PVD HfO

2 + Poly-Silicon

EOT = 1.2 nm

10-12

10-11

10-10

10-9

10-8

10-7

10-6

0 0.2 0.4 0.6 0.8 1

PVD HfO2 + Ru/W (PMOS)

I G (A

)

VG (V)

(b)

EOT = 0.9 nm

Cap Area 104µµµµm2

Figure 4.9. Gate leakage characteristics of PVD HfO2 with (a) poly-silicon gates (NMOS) and (b) Ru/W (PMOS) gates.

81

10-8

10-7

10-6

10-5

10-4

0 0.2 0.4 0.6 0.8 1 1.2

I D[A

]

VG [V]

JVD/AlW=10µµµµmL=1µµµµm

RTCVD/PolyW=3µµµµmL=0.6µµµµm

100mV/dec

(a)

EOT = 1.85 nm

10-6

10-5

-2 -1.5 -1 -0.5 0

|| ||I D|| || [

A]

VG [V]

JVD/PtW=3µµµµmL=0.6µµµµm

100mV/dec

(b)

EOT = 1.63 nm

Figure 4.10. Subthreshold characteristics of (a) NMOS JVD and RTCVD HfO2 and (b) PMOS JVD HfO2 devices.

82

10-8

10-7

10-6

10-5

10-4

0 0.2 0.4 0.6 0.8 1 1.2

I D[A]

VG [V]

JVD/AlW=10µµµµmL=0.6µµµµm

JVD/TaNW=10µµµµmL=1µµµµm

RTCVD/TaNW=10µµµµmL=1µµµµm

100mV/dec

(a)

EOT = 2.22 nm

EOT = 1.86 nm

10-8

10-7

10-6

10-5

-2 -1.5 -1 -0.5 0V

G [V]

JVD/PtW=3µµµµmL=1µµµµm

100mV/dec

|| ||I D|| || [

A]

(b)

EOT = 2.22 nm

Figure 4.11. Subthreshold characteristics of (a) NMOS JVD and RTCVD ZrO2 and (b) PMOS JVD ZrO2 devices.

83

10-8

10-7

10-6

10-5

10-4

0 0.2 0.4 0.6 0.8 1 1.2

I D [A

]

VG [V]


EOT = 1.2 nm

(a)

10-11

10-10

10-9

10-8

1 1.2 1.4 1.6 1.8

I D [A

/ µµ µµm

]

-VG [V]

W = L = 50 µµµµmEOT = 0.9 nm

(b)

Figure 4.12. Subthreshold characteristics of (a) NMOS PVD HfO2 with poly-silicon and (b) PMOS PVD HfO2 with Ru/W gate electrodes.

84

10-8

10-7

10-6

10-5

0.0001

0.001

0 0.2 0.4 0.6 0.8 1 1.2

I D[A]

VG [V]

TaNW=10µµµµmL=0.6µµµµm

100mV/dec

EOT = 3.82 nm

Figure 4.13. Subthershold characteristics of La2O3 NMOS device with TaN gate electrode.

85

0

10

20

30

40

50

60

0 0.2 0.4 0.6 0.8 1 1.2

I D [ µµ µµ

A/µ/µ /µ/µ

m]

VD

[V]

VDS

=0.8

VDS

=1.2

VDS

=1.0

VDS

=0.6


EOT = 1.85 nm

Figure 4.14. Id-Vd characteristics of JVD HfO2 with Al gated device.

86

0

50

100

150

200

250

0 0.2 0.4 0.6 0.8 1 1.2

I D [ µµ µµ

A/ µµ µµ

m]

VD [V]


VG=1.2V

VG=0.4V

VG=0.6V

VG=0.8V

VG=1.0V

Figure 4.15. Id-Vd characteristics of RTCVD HfO2 with poly-silicon gated devices.

87

0

5

10

15

20

25

30

35

40

-1.2 -1 -0.8 -0.6 -0.4 -0.2 0

VG=-2.0V

VG=-1.8V

VG=-1.6V

VG=-1.4V

VG=-1.2V

VD [V]


I D [ µµ µµ

A/µ/µ /µ/µ

m]

Figure 4.16. Id-Vd characteristics of JVD ZrO2 with TaN gated device.

88

0

0.5

1

1.5

2

2.5

3

3.5

4

0 0.2 0.4 0.6 0.8 1 1.2

VG=1.2V

VG=1.0V

VG=0.8V

VD[V]


I D [ µµ µµ

A/ µµ µµ

m] EOT = 2.22 nm

Figure 4.17. Id-Vd characteristics of JVD ZrO2 Al gated NMOS device.

89

0

20

40

60

80

100

0 0.2 0.4 0.6 0.8 1 1.2

VG=1.0V

VG=1.2V

VG=0.8V

VG=0.6V


VD [V]

I D [ µµ µµ

A/ µµ µµ

m]

EOT = 3.82 nm

Figure 4.18. Id-Vd characteristics of MBE La2O3 with TaN gated NMOS device.

90

0

5

10

15

20

25

30

35

40

-1.2 -1 -0.8 -0.6 -0.4 -0.2 0

VG=-2.0V

VG=-1.8V

VG=-1.6V

VG=-1.4V

VG=-1.2V

VD [V]

I D [ µµ µµA

/ µµ µµm

]


EOT = 1.63 nm

Figure 4.19. Id-Vd characteristics of JVD HfO2 Pt gated PMOS device.

91

0

5

10

15

20

-1.2 -1 -0.8 -0.6 -0.4 -0.2 0

VG=-2.0V

VG=-1.8V

VG=-1.6V

VG=-1.4V

VG=-1.2V

VD [V]

I D [ µµ µµ

A/µ/µ /µ/µ

m]


EOT = 2.22 nm

Figure 4.20. Id-Vd characteristics of JVD ZrO2 with Pt gated PMOS device.

92

0

50

100

150

200

250

300

5 105 7 105 9 105 1.1 106

HfO2(JVD)/Al

La2O

3/TaN

HfO2(RTCVD)/Poly

ZrO2(JVD)/Al

ZrO2(RTCVD)/TaN

ZrO2(JVD)/TaN

Field(V/cm)

Mob

ility

(cm

2 /V-s

)1.1nm Oxide Control

Sub. Doping = 1x1018/cm

Figure 4.21. Extracted NMOS mobility (JVD and RTCVD HfO2, JVD and RTCVD ZrO2, and MBE La2O3 devcies).

93

20

25

30

35

40

45

50

8 105 1 106 1.2 106 1.4 106 1.6 106

Mob

ility

[cm

2/V-

s]

Field [V/cm]


EOT = 1.2 nm

Sub. Doping = 3x1018/cm3

Figure 4.22. Extracted NMOS mobility of PVD HfO2 with poly-silicon gate.

94

26

28

30

32

34

36

38

40

5 105 6 105 7 105 8 105 9 105

HfO2(JVD)/Pt

ZrO2(JVD)/Pt

Field [V/cm]

Mob

ility

[cm

2 /V-s

]


Figure 4.23. Extracted PMOS mobility (JVD HfO2 and JVD ZrO2).

95

0

1

2

3

4

5

1.2 106 1.4 106 1.6 106 1.8 106

W=L=50µµµµmM

obili

ty [c

m2 /V

-s]

Field [V/cm]

EOT = 0.9 nm


Figure 4.24. Extracted PMOS mobility of PVD HfO2 with poly-silicon gate.

96

10-6

10-5

10-4

10-3

10-2

10-1

100

101

102

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

BeforeAfter (400C, 200 min FG)

J G [A

/cm

2 ]

Area=104µµµµm2

VG [V]

Figure 4.25. Gate leakage characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after H2 annealing.

97

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

BeforeAfter(400C, 20min FG)

VG [V]

C [ µµ µµ

F/cm

2 ]

Area=104µµµµm2

Figure 4.26. C-V characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after H2 annealing.

98

0 100

2 10-5

4 10-5

6 10-5

8 10-5

1 10-4

1.2 10-4

1.4 10-4

0 0.2 0.4 0.6 0.8 1 1.2

I D [A

]

VG [V]


Before

After(400C, 20min FG)

Figure 4.27. Id-Vg characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after H2 annealing.

99

20

30

40

50

60

70

80

90

100

1 106 1.2 106 1.4 106 1.6 106 1.8 106

AFTER(400C, 20min FG)

BEFORE

W=10µµµµmL=0.6µµµµmN

CHANNEL=3e18cm-3

Mob

ility

[cm

2 /V-s

]

Field [V/cm]

Figure 4.28. Mobility characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after H2 annealing.

100

10-7

10-5

10-3

10-1

101

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

BeforeAfter(400C, 20min D

2)

VG [V]

J G (A

/cm

2 )

Area = 104 µµµµm2

Figure 4.29. Gate leakage characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after D2 annealing.

101

0

0.5

1

1.5

2

2.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

BeforeAfter(400C, 20min D

2)

Cap

acita

nce

[ µµ µµF/

cm2 ]

VG [V]

Area = 104µµµµm2

Figure 4.30. C-V characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after D2 annealing.

102

0 100

5 10-5

1 10-4

1.5 10-4

2 10-4

0 0.2 0.4 0.6 0.8 1 1.2

BEFORE D

2 Annealing

AFTER D2 Annealing

BEFORE H

2 Annealing

AFTER H

2 Annealing

W=10µµµµmL=0.6µµµµmV

d=50mV

VG [V]

I D [A

]

Figure 4.31. Id-Vg characteristics of HfO2 (1.2 nm) with poly-silicon gates before and after D2 annealing. Id-Vg characteristics with H2 annealing are also shown to compare with D2 annealing.

103

0

50

100

150

1 106 1.2 106 1.4 106 1.6 106 1.8 106 2 106

Mob

ility

(cm

2 /V-s

)

VG [V]

BEFORE D2 Annealing

(3.48E11, 44.5)

AFTER D2

Annealing(5.2E10, 32.3)

BEFORE H2 Annealing

(1.2E11, 65.0)W=10µµµµmL=0.6µµµµm

AFTER H2 Annealing

(8E10, 39.8)

1.06nm Control Oxide(5e10, 30)

EOT for D2 Annealed Device=1.2nm

EOT for H2 Annealed Device=0.9nm

(NIF

, L*H)


Figure 4.32. MOSFET mobility characteristics of HfO2 (1.2 nm) with poly-silicon gates, before and after D2 annealing. Mobility characteristics with H2 annealing are also shown to compare with D2 annealing.

104

CHAPTER 5

Gate Leakage Current Behavior of HfO2 and Hf Silicate with Poly-silicon and Metal Gate Electrode

5.1. Introduction

In order to improve transistor performance, MOSFETs have been aggressively

scaled. As the gate dimensions are scaled, gate dielectric thickness also has to scale

down to have the right device characteristics. According to the 2001 International

Technology Roadmap for Semiconductors (ITRS), for sub-micron technology, ultra thin

SiO2 less than 1.0 nm is required [1]. It is well known that at this thickness, SiO2 has

reached the scaling limitation due to direct tunneling current for low power applications.

In addition it is expected to have reliability problems [2-3]. In order to overcome these

problems, high K dielectrics such as HfO2 and ZrO2 have been suggested to replace pure

SiO2. The hope is to use a thicker layer of high K dielectric, which exhibits less gate

leakage, while maintaining the same level of inversion under the gate.

Metal gate electrodes are highly desirable for high K gate dielectrics since they

can eliminate the limitations of poly-silicon gate, such as reaction at the interface, poly

depletion and dopant penetration. But replacing the poly-silicon gate electrode with

metal gate electrodes will impose new manufacturing and reliability challenges. Metal

gate electrodes require dual gates for NMOS and PMOS devices to have the right

threshold voltage, and they may require unconventional fabrication process such as

replacement gate or non self-aligned gate processes which are complicated and may

eventually prove to be unsuitable for commercial application. Poly-silicon gates are

105

desirable, instead of dual metal gates, because poly-silicon can be used to obtain the right

threshold voltage for both NMOS and PMOS by adjusting the ion implantation condition;

this process integration scheme is well established in the semiconductor industry. Due to

these reasons, there is a significant motivation to keep using poly-silicon gate with high

K gate dielectrics for as long as possible.

Although there are some reports on poly-silicon gates on HfO2 and ZrO2, the

stability of poly-silicon gates on high K dielectrics has still not been established [4-11].

In order to use the conventional gate first process with poly-silicon gate, the poly-

silicon/high K gate stack must withstand junction annealing temperatures, which may

range from 950 ºC to near the melting point of Si. At these high temperatures, Hf and Zr

oxides can crystallize [12-13] and their silicates may phase-separate [14].

Incompatibility of chemical vapor deposited poly-silicon gate with a ZrO2 gate dielectric

has already been reported [15-16]. In this chapter, the compatibility of poly-silicon gates

on HfO2 and Hf silicate was examined and compared with that using metal gate

electrodes.

5.2. Experimental

The gate leakage (Ig-Vg) was measured on MOS capacitors having either metal or

conventional poly-silicon gates and, the statistical variation of leakage was compared. Hf

silicate or HfO2, from any of three different sources, was deposited on p-type Si

substrates. Table 5.1 summarizes the deposition methods of HfO2 and Hf silicate in this

study [17-21]. In some experiments, designed to separate thermal from chemical

degradation of high K, high temperature anneal (600 – 1000 ºC) was performed prior to

106

gate electrode deposition. After high K deposition and optional annealing, gate

electrodes were deposited. Al gates were thermally evaporated; alternatively sputtering

was used to deposit TaSixNy gate electrodes on some wafers [22,23]. Three different

sources of poly-silicon gates were used on others. Low pressure chemical vapor

deposition (LPCVD) poly-silicon gates were deposited using SiH4 at two different

temperatures, 625 or 550 ºC. Another set of poly-silicon gates was prepared by RF

magnetron sputtering. The 625 ºC LPCVD process is conventionally used for poly-

silicon gated devices. The 550 ºC LPCVD and RF magnetron sputtering processes result

in amorphous silicon as-deposited which becomes poly-crystalline after the subsequent

annealing. The silicon gates were doped with phosphorus disks for 30 min at 900 ºC.

After the MOS capacitor fabrication, gate leakage (Ig-Vg) and capacitance voltage (C-V)

were measured for each of the gate stacks.

Table 5.1. HfO2 and Hf silicate deposition methods and their deposition condition

Dielectrics Deposition Method Deposition Condition Annealing

DC Magnetron Sputtering

(PVD) [19]

Sputtering at 20°C for

10 sec

500°C in N2 for 40

sec.

HfO2 Jet Vapor Deposition

(JVD) [20]

Mixture of Hf and O2

jet vapor at 350°C.

600°C in N2 for 1

min.

Metal Organic CVD

(MOCVD) [18]

350°C using HF (NO3)4 700°C in N2 for 1

min.

Hf silicate Remote Plasma Enhanced

CVD (RPECVD) [21]

300°C using HF tert-

butoxide

500°C in Ar for 1

min.

107

5.3. Results

5.3.1. Variability of Gate Leakage Current with Poly-silicon Gate

The gate leakage characteristics of devices having poly-silicon gates were

measured and compared with the metal gate devices. Figure 5.1 shows Ig-Vg electrical

results of PVD and MOCVD HfO2 with poly-silicon gates. For the PVD HfO2 devices,

the LPCVD poly-silicon gate was deposited at 550 ºC, while MOCVD HfO2 devices had

poly-silicon that was deposited at 625 ºC. As shown in the figures, large device-to-

device gate leakage variations were observed with poly-silicon gate capacitors, regardless

of the poly-silicon deposition condition. Gate leakage characteristics of PVD and JVD

HfO2 with metal gate electrodes are shown in figure 5.2. In contrast to the poly-silicon

gate devices, very little device-to-device gate leakage variations were observed with

metal gate electrodes. Furthermore, the gate leakages of metal gate devices scaled with

area. Figure 5.3 shows the gate leakage characteristics of Hf silicate (25% HfO2 + 75%

SiO2). As with HfO2, large gate leakage variations were observed with poly-silicon gates,

but relatively small variations were observed with Al gates. These results clearly show

that both HfO2 and Hf silicate degrade during the poly-silicon process. The statistical

variations of poly-silicon and metal gate leakage are shown in Figure 5.4. As shown in

the histograms, for both HfO2 and Hf silicate, poly-silicon gates result in large device-to-

device gate leakage variations. To examine the degradation of high K dielectrics with

poly-silicon gate process, gate leakage characteristics before and after breakdown were

measured and compared. As shown in figure 5.5, gate leakage characteristics measured

after breakdown match well with the high leakage currents measured before breakdown

in many capacitors. These results indicate that some of the devices were shorted during

108

the poly-silicon gate process.

Degradation of ZrO2 gate dielectric with a poly-silicon gate has been reported

[15-16]. In-situ XPS study showed that ZrO2 decomposition into Zr metal compound

occurred during the poly-silicon deposition [15]. Kim et al. postulated that during the

high temperature activation, an interfacial layer, most likely SiOx, was formed and this

SiOx triggered the decomposition of ZrO2 into ZrSi2 and Zr [15]. Contrary to observation

with ZrO2 and our results on HfO2, there are some reports stating that poly-silicon gate is

compatible with HfO2 [5,7]. J. Lee’s group fabricated MOSCAPs and MOSFETs with

PVD HfO2 with n+ poly-silicon gates [5-7]. The thermal stability of HfO2 was examined

by monitoring the changes in C-V and gate leakage characteristics. They reported tight

distributions of gate leakage current that were independent of RTA annealing

temperatures. They found negligible changes were observed in C-V. It is still not clear

that why this discrepancy is observed between our results and Lee’s. Even with these

encouraging results, J. Lee’s group had not shown the statistical data to back up their

results. Kaushik et al. reported that they observed “pin-hole” like defects in HfO2 films

that was caused by the presence of a reducing ambient during the poly-silicon deposition

[24]. They found that these weak spots were the mainly responsible for high leakage

currents. If these defects were distributed in the dielectrics, multiple measurements

through out the entire wafer and their statistical representation were needed to truly

represent the status of the dielectric. One thing to point out is that we also found

reasonable device characteristics similar to the reported values with JVD and PVD HfO2

devices on the few good spots where their gate leakage were small.

109

5.3.2. Compatibility of Poly-silicon Gate on Hf Silicate

The compatibility of poly-silicon gate on Hf silicate was examined and compared

with metal gate electrode. Two major effects need to be considered: 1) thermal

degradation during the high temperature poly-silicon activation cycle, and 2) chemical

reaction during the poly-silicon CVD deposition or during the doping anneal. To

examine the temperature effect, Hf silicate was deposited and annealed at four different

temperatures (600 ºC, 800ºC, 900ºC, and 1000ºC) for 1 minute prior to gate deposition.

Figure 5.6 shows the C-V characteristics of Al-gated Hf silicate capacitors for the

different pre-metal annealing temperatures. The C-V measurements were made in the

parallel mode at a frequency of 100 kHz. After the measurements, EOTs and flat band

voltages were determined by a non-linear least square fitting program using corrections

for quantum mechanical effects (Hauser program) [25,26]. As shown in the figure, no

significant deviation among the capacitors was observed except for small thickness

variations. This change in EOT for the curves in figure 5.6 could be due to either randum

thickness variation between the wafers or to phase segregation at high annealing

temperature. In order to further investigate these differences, EOTs were measured from

the center of the each wafers and compared with each other. In order to minimize the

thickness variations, EOTs were extracted from same center die (1 cm x cm) of each

wafer. Figure 5.7 shows the EOT variation with different annealing temperatures. The

EOT values given in the figure were average of 15 measurements for each temperature

with 2σ error bar. As shown in the figure, no significant EOT variation was observed

except for the capacitor with 1000 ºC annealing. Compared with the rest of the devices,

the capacitor annealed at 1000 ºC had higher EOT. Unfortunately, since we only have

110

limited samples, the statistical significance of this EOT change cannot be confirmed. But

within our experimental data sets, there is a strong suspicion that this change is legitimate.

Once the silicate system undergoes phase separation and crystallization, it is expected to

exhibit a lower permittivity (higher EOT) than the amorphous state [27].

The C-V and gate leakage characteristics of three different poly-silicon gates

(LPCVD Poly-silicon, LPCVD amorphous silicon, and sputter deposited amorphous

silicon) and two different metal gates (Al and TaSixNy) are shown in figures 5.8 and 5.9.

All devices with poly-silicon gates, regardless of their deposition methods or condition,

showed degraded C-V characteristics as shown in figure 5.8 (a); the devices with metal

gates showed reasonable characteristics (figure 5.8 (b)). As shown in figure 5.8 (b),

devices with TaSixNy gates showed lower EOT and larger negative charge than Al gated

devices. Since the TaSixNy gates were deposited by sputtering, energetic ions were

constantly bombarding the Hf silicate dielectric surface throughout the electrode

deposition, which may damage the dielectric surface and introduce some negative charge.

Figure 5.9 a-c show that poly-silicon gated capacitors had high gate leakage currents

which explains the huge roll off of C-V characteristics [28,29]. By using bulk material

data, HfO2 and Hf silicate are thermodynamically stable on Si. However, bulk

thermodynamic parameters cannot directly apply to the surface of ultra-thin films where

volatile SiO may be removed from the system thereby reducing an otherwise stable oxide.

Gilmer et al. observed a low density of very large poly-silicon grains after deposition of

poly-silicon gates on top of HfO2 [30]. According to them, a low density of Hf rich sites

on the HfO2 surface formed during the poly-silicon process, and these Hf rich sites

reacted with SiH4 to form Hf-Six. This Hf-Six can serve as a nucleation site, which

111

promotes poly-silicon nucleation and rapid grain growth. During the poly-silicon process,

these Hf rich sites are attributed to local reduction of the HfO2. A triple point is the point

where the three grain-boundaries meet. This triple point, where the bonding is least

perfect, is the most probable source of the defects, which can serve as a high leakage

current path. Even though the high thermal annealing alone did not degrade Hf silicate

dielectrics, the poly-silicon gate process (poly-silicon deposition process + high

temperature activation) possibly reduced the Hf silicate along some triple points. This Hf

silicate reduction along the weak grain-boundaries may be responsible for high gate

leakage current.

5.4 Summary and Conclusion

In order to examine the compatibility of poly-silicon gate electrodes with HfO2

and Hf silicate, Ig-Vg characteristics were statistically measured for metal and poly-

silicon gate devices. For both HfO2 and Hf silicate, large device-to-device gate leakage

variations were observed with poly-silicon gates. On the other hand, relatively small

variations were observed with metal gates where the gate leakage scaled nicely with area.

The results suggest that HfO2 and Hf silicate may react during the poly-silicon annealing

process.

To separate thermal effects during the high temperature poly-silicon activation

from chemical interaction with the poly-silicon electrode, MOS capacitors were prepared

with Hf silicates. First, Hf silicate capacitors were fabricated and annealed at different

temperatures (600 ºC – 1000 ºC) for 1 minute. The C-V data reveled that no significant

degradation was observed during the high temperature annealing. To examine the

112

reactions with the gate electrode, devices with different poly-silicon gates were prepared.

LPCVD poly-silicon gates were deposited at two different temperatures, 625 ºC and 550

ºC, and amorphous Si was deposited by RF magnetron sputtering. The results showed a

huge degradation in all poly-silicon gated devices, regardless of the poly-silicon

deposition condition. Even though the high temperature activation cycle alone had a

minor effect, the combination of high temperature annealing and the presence of silicon

gate degraded Hf-based dielectrics.

113

5.5. Reference



[2] S-H. Lo, D.A. Buchanan, Y. Taur, and W. Wang,”Quantum-mechanical Modeling of

Electron Tunneling Current form the Inversion Layer of Ultra Thin Oxide nMOSFETs”,.

IEEE Elec. Dev. Lett. 18 (209) (1997)

[3] J.H. Stathis, and D.J. DiMaria, “Reliability Projection for Ultra-thin Oxides at Low

Voltage”, Tech. Dig. Int. Electron Device Meet., p. 167 (1998)

[4] S.J. Lee, H.F. Luan, W.P. Bai, C.H. Lee, T.S. Jeon, Y. Senzaki, D. Roberts, and D.L.

Kwong, “High Quality Ultra Thin CVD HfO2 Gate Stack with Poly-Si Gate Electrode,”

Tech. Dig. Int. Electron Device Meet., p. 31 (2000)

[5] L.K. Kang, Y. Jeon, K. Onishi, B.H. Lee, W.-J. Qi, R. Nieh, S. Gopalan, and J.C. Lee,

“Single-layer Thin HfO2 Gate Dielectric with n+ Polysilicon Gate,” Symp. On VLSI Tech.

Dig., p.44 (2000)

[6] L. Kang, K. Onishi, Y. Jeon, B.H. Lee, C. Kang, W.-J. Qi, R. Nieh, S. Gopalan, R.

Choi, and J.C. Lee, “MOSFET Devices with Polysilicon on Single-Layer HfO2 High-K

Dieletrics,” Tech. Dig. Int. Electron Device Meet., p.35 (2000)

[7] S.J. Lee, C.H. Lee, Y.H. Kim, H.F. Luan, W.P. Bai, T.S. Jeon and D.L. Kwong,

“Dual-Poly CVD HfO2 Gate Stack for Sub-100 nm CMOS Technology,” Extended

Abstracts of International Workshop on Gate Insulator., p.80 (2001)

[8] W. Zhu and T.P. Ma, “HfO2 and HfAlO for CMOS: Thermal Stability and Current

Transport,” IEDM Tech. Dig., p.463 (2001)

[9] C. Hobbs, H. Tseng, K. Reid, B. Taylor, L. Dip, L. Herbert, R. Garcia, R. Hegde, J.

114

Grant, D. Gilmer, A. Franke, V. Dhandapani, M. Azrak, L. Prabhu, R. Rai, S. Bagchi, J.

Conner, S. Backer, F. Dumbuya, B. Nguyen and P. Tobin, “80 nm Poly-Si Gate CMOS

with HfO2 Gate Dielectric,” IEDM Tech. Dig., p.651 (2001)

[10] K. Onishi, C.S. Kang, R. Choi, H.-J. Cho, S. Goplan, R. Nieh, E. Dharmarajan and

J.C. Lee, “Reliability Characteristics, Including NBTI, of Polysilicon Gate HfO2

MOSFET’s,” IEDM Tech. Dig., p.659 (2001)

[11] Q. Lu, H. Takeuchi, X. Meng, T. King, C. Hu, K. Onihi, H. Cho, and J. Lee,

“Improved Performance of Ultra-thin HfO2 CMOSFETs Using Poly-SiGe Gate,” Symp.

On VLSI Tech. Dig. (2002)

[12] W.J. Zhu, T. Tamagawa, M. Gibson, T. Furukawa and T.P. Ma, “Effect of Al

Inclusion in HfO2 on the Physical and Electrical Properties of the Dielectrics”, IEEE

Electron Dev. Lett., 23 (11), (2002)

[13] J-P. Maria, D. Wickaksana, J. Parrette, and A.I. Kingon, “Crystallization in SiO2-

Metal Oxide Alloys”, J. Mater. Sci. May Issue, (2002)

[14] D. Wolfe, K. Flock, R. Therrien, R. Johnson, B. Raynor, L. Gunther, N. Brown, B.

Claflin, and G. Lucovsky, “Remote Plasma-Enhanced Metal Organic Chemical Vapor

Deposition of Zirconium Oxide/Silicon Oxide Alloy (ZrO2)x/(SiO2)1-x (x ≤ 0.5) Thin

Films for Advanced High-k Gate Dielectrics,” ULSI Gate Dielectrics, Symp. Mater. Res.

Soc., p.343 (1999)



B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R.W. Murto, A. Hou, H.R. Huff, E. Shero,

C. Pomarede, M. Givens, M. Mazanez, and C. Werkhoven, “Conventional n-channel

115

MOSFET Devices Using Single Layer HfO2 and ZrO2 as High-k Gate Dielectrics with

Polysilicon Gate Electrode” IEDM Tech. Dig., p.659 (2001)

[16] E.P. Gusev, E. Cartier, D.A. Buchanan, M. Gribelyuk, M. Copel, H. Okorn-

Schmidt, and C. D’Emic, “Ultrathin High-K Metal Oxides on Silicon: Processing,

Characterization and Integration Issues”, Microelectron. Eng. 59, p.341 (2001)










[20] Z.J. Luo, T.P. Ma, E. Cartier, M. Copel, T. Tamagawa, and B. Halpern, “Ultra-

Thin ZrO2 (or silicate) with High Thermal Stability for CMOS Gate



Abst. PV 00-1, Abst. No. 490 (2000)

[22] Y.S. Suh, G.P. Heuss, and V. Misra, “Electrical Characteristics of

TaSixNy/SiO2/Si Structures by Fowler-Nordheim Current Analysis,” Appl. Phys. Lett.

Vol 80, p. 1403 (2002)

[23] Y.S. Suh, G.P. Heuss, D.G. Park, K.Y. Lim, and V. Misra, “Thermal Stability of

116

TaSixNy Films Deposited by Reactive Sputtering on SiO2,” J. Electrochem. Soc., Vol

150, p. 79 (2003)

[24] V. Kaushik, S. De Gendt, M. Caymax, S. Van Elshocht, A. Delabie, M. Claes, E.

Rohr, R. Carter, Y. Manabe, E. Young, M. Schaekers, X. Shi, T. Conard, and M. Heyns,

“Compatibility of PolySilicon with HfO2-based Gate Dielectrics for CMOS

Applications,” ULSI Process Integration III, 203th ECS Spring Meeting (2003)(to be

Published)

[25] J. Hauser and K. Ahmed, “Characterization of Ultrathin Oxides Using Electrical C-

V and I-V Measurements,” AIP Conference Proceedings, p.235, Gaithersburg, MD,

Mar.23-27 (1998)

[26] J. Hauser, “Extraction of Experimental Mobility Data for MOS Devices,” IEEE

Trnas. Elec. Dev., 43, 1881 (1996)

[27] A.I. Kingon, J.P. Maria, D. Wicaksana, and C. Hoffman, “Compatibility of

Candidate High Permittivity Gate Oxides with Front and Backend Processing

Conditions”, 2001. IWGI 2001. Extended Abstracts of International Workshop on, p. 36

(2001)

[28] K. Ahmed, E. Ibok, C.F. Yeap, Q. Xiang, B. Ogle, J.J. Wortman, and J.R. Hauser,

“Impact of Tunnel Currents and Channel Resistance on the Characterization of Channel

Inversion Layer Charge and Polysilicon-Gate Depletion of Sub-20-Å Gate Oxide

MOSFET’s,” IEEE Trnas. Elec. Dev., 46, 1650 (1999)

[29] C.H. Choi, Y. Wu, J.S. Goo, Z. Yu, and W. Dutton, “Capacitance Reconstruction

from Measured C-V in High Leakage, Nitride/Oxide MOS,” IEEE Trnas. Elec. Dev., 47,

1843 (2000)

117

[30] D.C. Gilmer, R. Hegde, R. Cotton, R. Garcia, V. Dhandapani, D. Triyoso, D.

Roan, A. Franke, R. Rai, L. Prabhu, C. Hobbs, J.M. Grant, L. La, S. Samavedam, B.

Taylor, H. Tseng, and P. Tobin, “Compatibility of Polycrystalline Silicon Gate Depsition

with HfO2 and Al2O3/HfO2 Gate Dielectrics,” Apple. Phys. Lett. Vol 81, p. 1288 (2002)

118

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-1.5 -1 -0.5 0

I G (A

)

VG (V)

Cap Area 104µm2

(a)PVD HfO

2 + Poly-Si (LPCVD at 550 C)

EOT = 1.2 nm

Figure 5.1. (a) Gate leakage characteristics of PVD HfO2 with LPCVD poly-silicon gate electrode deposited at 550 ºC.

119

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

10-2

-1.5 -1 -0.5 0

I G (A

)

VG

(V)

Cap Area 104µm2

EOT = 2.1 nm

(b)

MOCVD HfO2 + Poly-Si (LPCVD at 650 C)

Figure 5.1. (b) Gate leakage characteristics of MOCVD HfO2 with LPCVD poly-silicon gate electrode deposited at 650 ºC.

120

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

0 0.5 1 1.5

I G (A

)

VG

(V)

105µm2

104µm2

103µm2

102µm2

10µm2

EOT = 0.9 nm

PVD HfO2 + Ru/W (PMOS)

(a)

Figure 5.2. (a) PMOS Gate leakage characteristics of PVD HfO2 with Ru/W gate electrode.

121

10-12

10-11

10-10

10-9

10-8

10-7

-1.5 -1 -0.5 0

I G (A

)

VG (V)

102µm2

103µm2

104µm2

105µm2

EOT = 1.85 nm

JVD HfO2 + Al (NMOS)

(b)

Figure 5.2. (b) NMOS Gate leakage characteristics of JVD HfO2 with Al gate electrode.

122

10-13

10-11

10-9

10-7

10-5

10-3

-1.5 -1 -0.5 0

MOCVD Hf Silicate + Poly-Si Gate

I G (A

)

VG (V)

25% HfO2 + 75% SiO

2(a)

Cap. Area =

10 µm2EOT = 5.5 nm

10-13

10-12

10-11

10-10

10-9

-1.5 -1 -0.5 0

MOCVD Hf Silicate + Al Gate

I G (A

)

VG (V)

Cap. Area = 10 µm2

EOT = 5.5 nm

(b) 25% HfO2 + 75% SiO

2

Figure 5.3. Gate leakage characteristics of MOCVD Hf silicate with (a) LPCVD poly-silicon gate electrodes deposited at 650 ºC and (b) Al metal gate electrodes.

123

Figure 5.4. Histogram representations of gate leakage variability for both poly-silicon and metal gate electrodes.

0

5

10

15

20

25

1 10-9 1 10-8 1 10-7 1 10-6 1 10-5 1 10-4

PVD HfO2 + Poly-Si Gate

Freq

uecy

(# o

f Occ

uran

ce)

IG (A) @ -1 V

Cap. Area = 104 cm2

0

2

4

6

8

10

12

14

1 10-121 10-111 10-10 1 10-9 1 10-8 1 10-7 1 10-6 1 10-5 1 10-4


Freq

uecy

(# o

f Occ

uran

ce)

IG (A) @ -1 V

Cap. Area = 104 cm2

0

2

4

6

8

10

12

14

16

1 10-121 10-111 10-10 1 10-9 1 10-8 1 10-7 1 10-6 1 10-5 1 10-4

MOCVD Hf Silicate + Poly-Si Gate

Freq

uecy

(# o

f Occ

uran

ce)

IG (A) @ -1 V

Cap. Area = 104 cm2

0

2

4

6

8

10

12

14

1 10-9 1 10-8 1 10-7 1 10-6 1 10-5 1 10-4

PVD HfO2 + Ru/W Gate

Freq

uecy

(# o

f Occ

uran

ce)

IG (A) @ -1 V

Cap. Area = 104 cm2

124

10-12

10-10

10-8

10-6

10-4

10-2

-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0

PVD HfO2 + Poly-Si Gate

I G (A

)

VG (V)

After BreakdownBefore Breakdown

Figure 5.5. PVD HfO2 gate leakage characteristics of before and after breakdown.

125

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

-2.5 -2 -1.5 -1 -0.5 0 0.5 1


6008009001000

C (µ

F/cm

2 )

VG (V)

Figure 5.6. C-V Characteristics of Hf silicate capacitors with four different temperatures (600 ºC, 800 ºC, 900 ºC, and 1000 ºC).

126

2

2.5

3

3.5

4

4.5

5MOCVD Hf Silicate + Al Gate

EOT

(nm

)

Annealing Temperature ( C)600 800 900 1000700

Figure 5.7. EOT variation with four different annealing temperatures (600 ºC, 800 ºC, 900 ºC, and 1000 ºC).

127

0

0.1

0.2

0.3

0.4

0.5

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Hf Silicate + Poly-Silicon GateLPCVD α-Si at 550 CLPCVD Poly-Si at 625 C

Sputtering Deposition α-Si

C (µ

F/cm

2 )

VG (V)

(a)

25% HfO2 + 75% SiO

2

0

0.2

0.4

0.6

0.8

1

1.2

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Hf Silicate + Metal Gate

TaSixN

yAl

C (µ

F/cm

2 )

VG (V)

V FBEOTGate Metal

-0.56 V2.83 nmTaSi x N

y

-1.20 V3.40 nmAl

25% HfO2 + 75% SiO

2

(b)

Figure 5.8. C-V characteristics of (a) three different silicon gates (LPCVD poly-silicon, LPCVD amorphous silicon, and PVD amorphous silicon) and (b) two different (Al and TaSixNy) metal gates.

128

10-9

10-7

10-5

10-3

10-1

101

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Hf Silicate + LPCVD Si at 550 CJ G

[A/c

m2 ]

VG [V]

(a)

10-9

10-7

10-5

10-3

10-1

101

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Hf Silicate + LPCVD Si at 625 C

J G [A

/cm

2 ]

VG [V]

(b)

10-9

10-7

10-5

10-3

10-1

101

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Hf Silicate + PVD Si

VG [V]

J G [A

/cm

2 ]

(c)

10-9

10-8

10-7

10-6

10-5

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

Hf Silicate With Metal Gate

AlTaSi

xN

y

J G [A

/cm

2 ]

VG [V]

(d)

Figure 5.9. Gate leakage characteristics of (a) LPCVD amorphous-silicon, (b)LPCVD poly-silicon, (c) PVD amorphous silicon, and (d) metal gate electrodes.

CHAPTER 6

Gate Leakage Characteristics of Hf Silicate Alloys and Effect

of Nitridation

6.1. Introduction

As device dimensions are scaled down to the sub micron regime, there is a strong

urge to replace the SiO2 gate dielectric with an alternative material that has a higher

dielectric constant than that of SiO2. Recently, HfO2 and ZrO2 have been extensively

studied as alternative gate dielectrics due to their thermodynamic stability in direct

contact with Si and due to their larger barrier heights [1-20]. But even with these

dielectrics, their chemical/thermal stability during the high temperature annealing is still

in question. The thermal budget associated with a conventional gate first process may

range from 950 ºC to near the melting point of Si. Under these conditions, the high K

dielectric may degrade.

HfO2 and ZrO2 are stable on Si and exhibit high K values, but they will crystallize

at a relatively low temperature. In addition, HfO2 and ZrO2 are poor diffusion barriers

for oxygen. After high temperature processing, oxygen diffuses readily through the metal

oxides, reacts with Si and forms an uncontrolled interfacial layer. Several research

groups reported the formation of an interfacial layer, as thick as 1.0 nm. [5-10]. This

interfacial layer is a significant portion of the overall oxide thickness and needs to be

minimized for further oxide thickness scaling.

Hf and Zr silicates are known to have a much improved thermal stability

129

compared to pure metal oxides [21-25]. These silicates represent a mixture of a high K

metal oxide, HfO2 or ZrO2, with a SiO2 to obtain a desirable morphology with suitable

properties. Obviously, the overall permittivity of silicate is lower than pure metal oxide,

but its crystallization temperature is much higher than metal oxide [23]. A silicate-Si

interface is chemically similar to the SiO2–Si interface. However, even in dilute silicates,

phase separation can still occur at high temperature [26-28]. Figure 6.1 illustrates the

phase segregation phenomena of Zr silicate under oxidizing conditions. During high

temperature annealing, phase separation occurs, leading to phase crystallization of the

metal. The crystallization temperature of the silicate system is a function of the SiO2

content in the film: as the fraction of SiO2 is increased, the crystallization temperature is

also increased [28]. A typical crystallization temperature of dilute silicate alloy (~30% of

metal oxide) is between 900 – 1000 ºC [28-30]. An amorphous silicate dielectric is

desirable since it has lower leakage current and higher permittivity value than crystallized

films [28]. With these issues in mind, it is still questionable whether Hf and Zr silicate

will have the necessary thermal stability to withstand conventional junction annealing

temperature.

In this chapter, the gate leakage characteristics of Hf silicate alloys are described.

In collaboration with the Lucovsky group, a series of MOS capacitors were fabricated

using Hf silicate alloys with varied Hf composition (10-100%). Recently, nitridation has

been shown to improve the thermal stability of high K dielectrics [15]. In addition,

nitrogen incorporation into gate dielectrics has been demonstrated to lower leakage,

increase dielectric constant and suppress boron penetration [31-33]. Accordingly,

nitridation of Hf silicate (25% HfO2) was also studied.

130

6.2. Experimental

MOS capacitors were fabricated using a thick field oxide isolation on p-type Si

substrates. After active area patterning and removal of sacrificial oxide, the wafers were

ready for dielectric depositions. First, bottom interfacial oxides (~0.6 nm) were grown by

remote plasma oxidation in O2 at 300 ºC for 30 seconds. This was followed by the high

K dielectric deposition. The Hf silicate films were deposited by remote plasma enhanced

chemical vapor deposition (RPECVD) using Hf tert-butoxide precursor, SiH4 and O2

sources at 300 mtorr and 300 ºC. In some selected capacitors, prior to Hf silicate

deposition interfacial/surface nitridation was perfomed in a N2 ambient at 34 mtorr for 15

seconds. In some samples, surface nitridation was performed after the silicate deposition

at 300 mtorr for 15 minutes. Following the gate dielectric deposition, post-deposition ex-

situ annealing (PDA) was performed in Ar at 600 ºC for 1 minute using an AG

Associates minipulse rapid thermal annealer (RTA). After the PDA and prior to the gate

electrode deposition, forming gas annealing was performed 400 ºC, in N2 plus 10% of

either H2 or Deuterium (D2). Following the forming gas annealing, gate electrodes, Al or

poly-silicon, were deposited. The poly-silicon gates were deposited by low pressure

chemical vapor deposition (LPCVD) using SiH4 at 625 ºC; Al electrodes were deposited

by thermal evaporation. The poly-silicon gates were doped with phosphorus disks for 30

min at 900 ºC. After the MOS capacitor fabrication, gate leakage current (Ig-Vg) and

capacitance voltage (C-V) were measured for each of the gate stacks.

131

6.3.Results

6.3.1. Gate Leakage of Hf Silicate Alloys

Figure 6.2 shows the gate leakage current at -1 V gate bias for different Hf silicate

compositions. Since different Hf silicate compositions exhibited different permittivity

values, they had different EOTs for the same physical thickness. Thus, in order to

compare gate leakages for different silicate compositions, corrections were needed. First,

for each EOT, the gate leakage of SiO2 was simulated using UTQUANT, a quantum

mechanical leakage current simulator [32]. Then experimentally measured Hf silicate

gate leakage was normalized to the calculated oxide leakage. As shown in the figure, the

measured gate leakage tunneling currents verified theoretical predictions of a minimum

in leakage at an intermediate silicate composition [35]. The intermediate Hf silicate

alloys result in less leakage than either pure HfO2 or pure SiO2. This is a significant

finding because dilute silicates have improved thermal stability.

6.3.2. Effect of Nitridation

Increase of EOT during subsequent high temperature process is one of the major

concerns with high K dielectrics. During any high temperature annealing, dielectrics

containing OH in the bulk or adsorbed wafer vapor on the surface are susceptible to the

growth of additional oxide [36-38]. It has been reported that nitridation of the bottom

interface, the bulk, or the top surface of the dielectric is an effective technique to suppress

this additional oxide growth [29-30]. In other studies, one monolayer of nitridation

(~7x1014/cm2), resulted in smooth interfaces and reduced tunneling current by reducing

sub-oxide bonding [39,40]. Figures 6.3 (a) and (b) show the C-V characteristics of poly-

132

silicon and Al gate on 25% HfO2 silicates which had different nitridation conditions.

Smooth C-V characteristics were obtained for both electrodes and all nitridation

conditions. However, as shown in the figure, nitridation played a significant role in EOT

and charge in the dielectrics. Figures 6.4 and 6.5 illustrate the effect of interface and

surface nitridation on Hf silicate with Al and poly-silicon gates, respectively. For both Al

and poly-silicon gate devices, surface nitridation resulted in 10% lower EOT than un-

nitrided films, while interface nitridation gave even lower (~2 nm) EOT. Figures 6.3 (b)

and 6.4 (b) show the effect of nitridation on flat band voltages. For both Al and poly-

silicon gate devices, surface (only) nitridation introduces positive charge (flat band

voltage shifts to more negative value). On the other hand, interface plus surface

nitridation removes positive charge. The results indicate that interface nitridation inhibits

interfacial oxidation and effectively removes positive charge.

Dr. Lee’s research group at UT Austin also studied nitridation of PVD HfO2 [31-

33]. Similar to our results, they also found that nitridation significantly reduced

interfacial layer formation [31]. On the other hand, they reported that interfacial

nitridation introduced positive charge into the dielectric and that no significant flat band

voltage shift was observed with surface nitridation [32]. This is the exactly opposite to

our result. However a different nitridation technique was used in this study. Dr. Lee’s

group used thermal nitridation (annealed in NH3 ambient at 700 ºC) while our samples

were nitrided by remote plasma as described in experimental section. In addition, the

gate dielectric here was composed of two independently formed layers: Hf silicate on top

of a bottom interfacial oxide (0.6 nm) formed by remote plasma oxidation. Interfacial

nitridation was performed right after the interfacial oxide, so that the nitridation was

133

performed on the oxide and not on the bare Si. Incorporation of nitrogen in this kind of

SiO2 layer has been shown in many other studies to be beneficial [41-47]. Interfacial

nitride is a barrier to Si, metal, and boron [41-44]. Optimized nitridation on SiO2 ends up

with N-(Si ≡) structure which cannot act as a defect precursor due to its planar structure

and pπ-dπ bonding interaction [45,46]. Nimi et al. studied the monolayer-level nitrogen

incorporation at the Si-SiO2 interface [47]. They found that the nitrogen incorporation

did not generate a fixed oxide charge but instead led to reduce suboxide bonding, which

reduced the gate oxide leakage. Since we followed exactly the same interfacial

nitridation scheme, we also found improved characteristics, lower EOT and less charge in

the dielectrics, with the interfacial nitirdation. On the other hand, the surface nitridation

process scheme is not fully optimized yet and it may introduce too much nitrogen or

damage the dielectric. Indeed, excessive positive charges were observed in the dielectric

after this process. When both surface and interfacial nitridations were performed, this

excess positive charge was not seen and the dielectric retained its original flat band

voltage.

6.4. Conclusion

In collaboration with the Lucovsky group, a series of capacitors were fabricated

using Hf silicate alloys with varied Hf composition. As the theory predicted, a minimum

in gate leakage was observed at a intermediate silicate composition (~50% HfO2).

Silicate as dilute as 25% HfO2 had gate leakage as low as pure HfO2. Nitridation of the

bottom and top surface of dielectric were seen to improve its stability. Nitridation also

134

plays a significant role against EOT increase and charge in Hf silicste. Both nitridation

processes resulted in lower EOT then un-nitrided films, but interfacial nitridation was

most effective in retarding additional oxidation. Surface (only) nitridation introduced

positive charges into the silicate, while interfacial plus surface nitridation removed

positive chareges. Thus, interfacial nitridation was shown to be an important parameter

to control the thickness and quality of silicate films.

135

6.5. Reference







[3] M. Copel, M. Gribelyuk, E. Gusev, “Structure and Stability of Ultrathin

Zirconium Oxide Layers on Si(001),” Apple. Phys. Lett. Vol 76, p. 436 (2000)




[5] L. Kang, Y. Jeon, K. Onishi, B.H. Lee, W.-J. Qi, R. Nieh, S. Gopalan, and J.C.

Lee, “Single-layer Thin HfO2 Gate Dielectric with n+ Polysilicon Gate,” Symp. On VLSI

Tech. Dig., p.44 (2000)




[7] W.-J. Qi, R. Nieh, B.H. Lee, K. Onishi, L. Kang, Y. Jeon, J.C. Lee, V. Kaushik,

B.-Y. Neuyen, L. Prabhu, K. Eisenbeiser, and J. Finder, “Performance of MOSFETs with

Ultra Thin ZrO2 and Zr Silicate Gate Dielectrics,” Symp. On VLSI Tech. Dig., p.40

(2000)

[8] T. Yamaguchi, H. Satake, N. Fukushima, and A. Toriumi, “Band Diagram and

136

Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by

Pulsed-laser-ablation Deposition,” Tech. Dig. Int. Electron Device Meet., p.19 (2000)






B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R.W. Murto, A. Hou, H.R. Huff, E. Shero,

C. Pomarede, M. Givens, M. Mazanez, and C. Werkhoven, “Conventional n-channel

MOSFET Devices Using Single Layer HfO2 and ZrO2 as High-k Gate Dielectrics with

Polysilicon Gate Electrode” Tech. Dig. Int. Electron Device Meet., p.659 (2001)

[11] Y. Ma, Y. Ono, L. Stecker, D.R. Evans, and S.T. Hus, “Zirconium Oxide Based

Gate Dielectrics with Equivalent Oxide Thickness of Less Than 1.0 nm and Performance

of Submicron MOSFET using a Nitride Gate Replacement Process,” Tech. Dig. Int.

Electron Device Meet., p. 149 (1999)

[12] S.A. Campbell, R. Smith, N. Hoilien, B. He, and W.L. Gladfelter, “Group IVB

Metal Oxides: TiO2, ZrO2, and HfO2 as High Permitivity Gate Insulators,” MRS

Workshop, New Orleans, LI, June 1-2, p.9 (2000)

[13] R.C. Smith, N. Hoilien, C.J. Taylor, T. Ma, S.A. Campbell, J.T. Roberts, M.

Copel, D.A. Buchana, M. Gribelyuk and W.L. Gladfelter, “Low Temperature Chemical

Vapor Deposition of ZrO2 on Si (100) Using Anhydrous Zirconium (IV) Nitrate,” J.

Electrochem. Soc., Vol 147, p. 3472 (2000)

[14] M. Houssa, V.V. Afanas’ev, A. Stesmans, and M.M. Heyns, “Variation in the

137

Fixed Charge Density of SiOx/ZrO2 Gate Dielectric Stacks During Postdeposition

Oxidation,” Appl. Phys. Lett. Vol 77, p. 1885 (2000)

[15] L. Manchanda, M.L. Green, R.B. van Dover, M.D. Morris, A. Kerber, Y. Hu, J.-

P. Han, P.J. Silverman, T.W. Sorsch, G. Weber, V. Donnelly, K. Pelhos, F. Klemens, N.

A. Ciampa, A. Kornblit, Y.O. Kim, J.E. Bower, D. Barr, E. Ferry, D. Jacobson, J. Eng, B.

Bush, and H. Schulte, “Si-Doped Aluminates for High Temperature Metal-Gate

CMOS:Zr-Al-Si-O, A Novel Gate Dielectric for Low Power Applications,” Tech. Dig.


[16] L. Kang, K. Onishi, Y. Jeon, B.H. Lee, C. Kang, W.-J. Qi, R. Nieh, S. Gopalan,

R. Choi, and J.C. Lee, “MOSFET Devices with Polysilicon on Single-Layer HfO2 High-

K Dieletrics,” Tech. Dig. Int. Electron Device Meet., p.35 (2000)

[17] R. Choi, k. Onishi, C. S. Kang, R. Nieh, S. Gopalan, H.-J. Cho, S. Krishnan,J.C.

Lee, “High Quality MOSFETs Fabrication with HfO2 Gate Dielectric and Tan Gate

Electrode,” Device Research Conference, 2002. 60th DRC. Conference Digest , p. 193

(2002)

[18] R. Choi, C.S. Kang, B.H. Lee, K. Onishi, R. Nieh, S. Gopalan, E. Dharmarajan,

J.C. Lee, “High-quality Ultra-thin HfO2 Gate Dielectric MOSFETs with TaN Electrode

and Nitridation Surface Preparation,” Symp. On VLSI Tech. Dig., p.15 (2001)

[19] Q. Lu, R. Lin, H. Takeuchi, T.-J. King, C. Hu, K. Onishi, R. Choi, C.-S. Kang,

J.C. Lee, “Deep-submicron CMOS Process Integration of HfO2 Gate Dielectric with Poly

Si gate,” 2001 International Semiconductor Device Research Symposium, p.377 (2001)

[20] R. Nieh, K, Onishi, R. Choi, H.-J. Cho, C.S. Kang, S. Gopalan, S. Krishna, J.C.

Lee, “Performance Effects of Two Nitrogen Incorporation Techniques on TaN/HfO2 and

138

Poly/HfO2 MOSCAP and MOSFET Devices Gate Insulator”, 2001. IWGI 2001.

Extended Abstracts of International Workshop on, p. 70 (2001)

[21] G.D. Wilk, and R.M. Wallace, “Electrical Properties of Hafnium Silicate Gate

Dielectrics Deposited Directly on Silicon,” Appl. Phys. Lett. Vol 74, p.2854 (1998)

[22] G.D. Wilk, and R.M. Wallace, “Stable Zirconium Silicate Gate Dielectrics

Deposited Directly on Silicon,” Appl. Phys. Lett. Vol 76, p. 112 (2000)

[23] W.-J. Qi, R. Nieh, E. Dharmarajan, B.H. Lee, Y. Jeon, L. Kang, K. Onishi, and

J.C. Lee, “Ultrathin Zirconium Silicate Film with Good Thermal Stability for Alternative

Gate Dielectric Application,” Appl. Phys. Lett. Vol 77, p. 1704 (2000)

[24] G. Lucovsky, G.B. Rayner, Jr., “Microscopic Model for Enhanced Dielectric

Constants in Low Concentration SiO2-rich Noncrystalline Zr and Hf Silicate Alloys,”

Appl. Phys. Lett. Vol 77, p. 2912 (2000)



Abst. PV 00-1, Abst. No. 490 (2000)

[26] D. Wolf, K. Flock, R. Therrien, R. Johnson, B. Raynor, L. Gunther, N. Brown, B.

Claflin, and G. Lucovsky, “Remote Plasma Enhanced Metal Organic Chemical Vapor

Deposition of Zirconium Oxide/Silicon Oxide Alloy (ZrO2)x(SiO2)1-x (x≤0.5) Thin Films

for Advanced High K Gate Dielectrics,” ULSI Gate Dielectrics, Symp. Mater. Res. Soc.,

p.343 (1999)

[27] J.P. Maria, D. Wickaksana, J. Parrette, and A.I. Kingon, “Crystallization in SiO2-

Metal Oxide Alloys,” J. Mat. Res., Vol 17, p.1571 (2002)

[28] A.I. Kingon, J.P. Maria, D. Wicaksana, and C. Hoffman,

139

“Compatibility of Candidate High Permittivity Gate Oxides with Front and Backend

Processing Conditions”, 2001. IWGI 2001. Extended Abstracts of International

Workshop on, p. 36 (2001)

[29] C.M. Osburn, S.K. Han, I. Kim, S. Campbell, E. Garfunkel, T. Gustafson, J.

Hauser, T.-J. King, Q. Liu, P. Ranade, A. Kingon, D.-L. Kwong, S.J. Lee, C.H. Lee, J.

Lee, K. Onishi, C.S. Kang, R. Choi, H. Cho, R. Nieh, G. Lucvosky, J.G. Hong, T.P. Ma,

W. Zhu, Z. Luo, J.P. Maria, D. Wicaksana, V. Misra, J.J. Lee, Y.S. Suh, G. Parsons, D.

Niu, and S. Stemmer, “Integration Issues with High K Gate Stacks,” Proceedings of the

Symposium on ULSI Process Integration III, The Electrochemical Society, PV2003-06, p.

375 (2003)

[30] Presentation: Spectroscopic Structures of Zr Silicate, (ZrO2)x(SiO2)(1-x) Dielectric

Films Bonding Coordination and Chemical Phase Separation by FTIR, XPS, AES and

EXAFS; B. Rayner, D. Kang, and G. Lucovsky; North Carolina State University; 29-Oct-

2002;20pp.; (Pub P004899); SRC task 616.024

[31] C.S. Kang, H.-J. Cho, K. Onishi, R. Choi, Y.H. Kim, R. Nieh, J. Han, S. Krishnan,

A. Shahriar, and J.C. Lee, “Nitrogen Concentration Effects and Performance

Improvement of MOSFETs Using Thermally Stable HfOxNy Gate Dielectrics,” Tech.


[32] H.-J. Cho, C.S. Kang, K. Onishi, S. Gopalan, R. Nieh, R. Choi, E. Dharmarajan,

and J.C. Lee, “Novel Nitrogen Profile Engineering for Improved TaN/HfO2/Si MOSFET

Performance,” Tech. Dig. Int. Electron Device Meet., p.655 (2001)

[33] K. Onishi, L. Kang, R. Choi, E. Dharmarajan, S. Gopalan, Y. Jeon, C.S. Kang,

B.H.Lee, R. Nieh, and J.C. Lee, “Dopnat Penetration Effects on Polysilicon Gate HfO2

140

MOSFETs,” Symp. On VLSI Tech. Dig., p.131 (2001)

[34] W.-K. Shih, “UTQUANT 2.0 User’s Guide,” Ausitn,TX: Univ. Texas Press

(1997)

[35] G. Lucovsky, B. Rayner, Z. Yu, and J. Whitten, “Experimental Determination of

Band Offset Energies Between Zr Silicate Alloy Dielectrics and Crystalline Si Substrates

by XAS, XPS and AES and Ab Initio theory: A New Approach to the Compositional

Dependence of Direct Tunneling Currents,” Tech. Dig. Int. Electron Device Meet., p.617

(2002)

[36] D. Niu, R.W. Ashcraft, and G. N. Parsons, “Water Adsorption and Interface

Reactivity of Yttrium Oxide Gate Dielectrics on Silicon,” Appl. Phys. Lett. Vol 80, p.

3575 (2002)

[37] T. Gougousi, M.J. Kelly, and G.N. Parson, “The Role of the OH Species in High

K/Poly-Si Gate Electrode Interface Reactions,” Appl. Phys. Lett. Vol 80, p. 4419 (2002)

[38] T. Gougousi, M.J. Kelly, W.S. Burnside, J.M. Bennett, T.L. Schmit, and G.N.

Parson, “Preparation and OH Absorption in La Silicate Formed by Oxidation of PVD La

on Si,” MRS Spring Meeting (April 2-5, 2002)

[39] H. Yang, G. Lucovsky, “Integration of Ultrathin (1.6~2.0 nm) RPECVD

Oxynitride Gate Dielectrics into Dual Poly-Si Gate Submicron CMOSFETs,” Tech. Dig.


[40] H. Nimi, “Monolayer-Level Controlled Incorporation of Nitrogen in Ultra-Thin

Gate Dielectrics Using Remote Plasma Processing.” Ph.D. Dissertation Thesis, North

Carolina State University, 1998

[41] S.K. Ghandi, VLSI Fabrication Principles (Wiely, New York, 1994)

141

[42] P.D. Krisch and J.G. Ekerdt, “Interfacial Chemistry of the Ba/SiOxNy/Si(100)

Nanostructure,“ J. Vac. Sci. Technol. A. Vol 19, p. 207 (2001)

[43] P.D. Krisch and J.G. Ekerdt, “Interfacial Chemistry of the Sr/SiOxNy/Si(100)

Nanostructure, “ J. Vac. Sci. Technol. A. Vol 19, p. 2222 (2001)

[44] M.L. Green, D. Brasen, K.W. Evens-Lutterodt, L.C. Feldman, K. Krisch, W.

Lennard, H.-T. Tang, L. Manchanda, and M.-T.Tang, “Rapid Thermal Oxidation of

Silicon in N2O Between 800 and 1200 °C: Incorporated Nitrogen and Interfacial

Roughness,” Appl. Phys. Lett. Vol 65, p. 848 (1994)

[45] G. Lucovsky, Z. Jing, and D.R. Lee, “Defect Properties of Si-, O-, N- and H-

Atoms at Si-SiO2 Interface,” J. Vac. Sci. Technol. B. Vol 14, p. 2832 (1996)

[46] F.A. Cotton and G. Wilkinson, Advanced Inorganic Chemistry (Interscience, New

York, 1972)

[47] H. Nimi, and G. Lucovsky, “Monolayer-Leve Controlled Incorporation of

Nitrogen in Ultrathin Gate Dielectrics Using Remote Plasma Processing: Formation of

Stacked “N-O-N” Gate Dielectrics,” J. Vac. Sci. Technol. B. Vol 17, p. 2610 (1999)

142

Si

SiO2

SiO2 rich Crystalline ZrO2

Si

ZrO2•SiO2 (amorphous) Figure 6.1. Schematic illustration of (ZrO2)•(SiO2) phase separation after high temperature annealing under oxidizing conditions.

143

10-9

10-7

10-5

10-3

10-1

101

0 20 40 60 80 1Leak

age

Cur

rent

@-1

V fo

r EO

T=1n

m[A

/cm

2 ]

(HfO2)x (SiO

2)1-x [%]

SiO2

00

Range of data reported for HfO

2

* Data corrected for thickness (Assuming SiO

2 thickness dependence)

NMOSCAP Gate Injection

Figure 6.2. Gate leakage current (corrected for 1 nm EOT) at -1 V gate bias for different silicate composition.

144

0.1

0.2

0.3

0.4

0.5

0.6

-3 -2 -1 0 1 2

25%HfO2 + 75% SiO

2 /Poly Gate

Interface + Surface NitridationSurface NitridationNo Nitridation

C (µ

F/cm

2 )

VG (V)

Cap. Area = 104µm2

(a)

Figure 6.3. (a) C-V characteristics of Hf silicate/poly-silicon gate stack with different nitridation conditions.

145

0.1

0.2

0.3

0.4

0.5

0.6

-3 -2 -1 0 1 2

25%HfO2 + 75% SiO

2 /Al Gate

Interfacial + Surface NitridationSurface NitridationNo Nitridation

C (µ

F/cm

2 )

VG (V)

(b)

Figure 6.3. (b) C-V characteristics of Hf silicate/Al gate stack with different nitridation conditions.

146

5

5.5

6

6.5

7

7.5

825% HfO

2 + 75% SiO2

2 / Al Gate

EOT

( nm

)

Nitridation Condition

No Nitridation

Surface Nitridation

Interfacae& SurfaceNitridation

(a)

Figure 6.4. (a) Interfacial and surface nitridation effect on EOT (Hf silicate with Al gate).

147

25% HfO2 + 75% SiO2

2 / Al Gate

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

- V FB

(V)

Nitridation Condition0

3

6

9

10

13

15

NF,equiv (10

11/cm2)

No Nitridation

Surface Nitridation

Interface& SurfaceNitridation

(b)

Figure 6.4. (b) Interfacial and surface nitridation effect on flat band volgates (Hf silicate with Al gate).

148

25% HfO2 + 75% SiO

2 / Poly Gate

5

5.5

6

6.5

7

7.5


EOT

(nm

)


No Nitridation Surface Nitridation

Figure 6.5. (a) Interfacial and surface nitridation effect on EOT (Hf silicate with poly-silicon gate).

149

25% HfO2 + 75% SiO

2 / Poly Gate

-1.4

-1.35

-1.3

-1.25

-1.2

-1.15

-1.1

-1.05

-1


V FB (V

)

No Nitridation Surface Nitridation


Figure 6.5. (b) Interfacial and surface nitridation effect on flat band volgates (Hf silicate with poly-silicon gate).

150

CHAPTER 7 Summary and Conclusions

In order to study high K dielectrics and gate electrode materials, NMOS and

PMOS devices having alternative gate stacks were fabricated and evaluated. The

integration focus was on devices that meet the 70 and 50 nm node ITRS performance

objectives and on processes that were thermally and chemically compatible with new

dielectrics and new gate electrode materials. Since many of these new materials are

unable to withstand the thermal and chemical processing conditions that are present today,

a different device integration strategy was required to form the gate dielectric/gate

electrode stack after junction annealing and contact formation. For this task, a non-self-

aligned scheme was developed in order to assess candidate materials. After device

fabrication, electrical properties of the materials were evaluated.

7.1. Non-self Aligned Gate Process and ERC 6 Mask Set

Due to the limited thermal and chemical stability of many high K dielectric and

metal gate electrode candidates, the thermal budget after the gate stack formation needs

to be minimized. The replacement gate scheme accomplishes this objective using a

technology that provides high performance devices; however, it is a complex process that

requires many additional steps, thereby increasing fabrication time. In this study, a non-

self aligned process and a new mask set, ERC 6, have been developed to more rapidly

fabricate devices having alternative gate stacks (31 steps in the non self-aligned process

vs. 66 steps in a replacement gate process). This process forms source/drain junctions

151

before the gate stack depositions and, thus allows the use of dielectrics and electrodes

that are not able to withstand junction activation temperatures.

7.2. Etching of High K Gate Dielectrics and Gate Metal Electrodes

The etching behaviors of high K dielectrics and meal gate electrodes were studied

and new etching recipes for each candidate material were developed. Wet etching of Pt

and TaN were performed in diluted aqua-regia and TaN etchant, respectively. During

wet etching of these materials, adhesion between the photoresist and metal was lost. To

prevent adhesion loss, the photoresist was re-baked periodically. RIE processes were

developed for RuO2, Ru, Ru/W and Ta/W gate electrodes. Etching of RuO2 has been

demonstrated using a mixture of O2 and CHF3 (2.5%) plasma where a fairly high etching

rate (~40 nm/min) was achieved. However, even with the addition of a few percent of

Cl2 to O2 to enhance the etch rate of Ru, only a very small etching rate (up to 6.7 nm/min)

was observed, and this etch rate was slower than that of photoresist. In order to

circumvent this problem, without using a hard mask, a laminated gate composed of a thin

layer of Ru (3 nm) with a thick layer of W (100 nm) was used.

The etching characteristics of various high K dielectric candidates depended not

only on the materials, but also on the deposition methods. Most ZrO2 films etched in

BOE, while RTCVD films required dry etching. Similarly, JVD HfO2 etched in BOE,

but other HfO2 films needed dry etching. La2O3 received ion milling, while Y2O3 etched

in BOE.

152

7.3. Device Characterization of Alternative Gate Stacks Using the Non-self Aligned

Gate process

After the devices were fabricated by the non self-aligned gate process, their

electrical characteristics were measured and compared. The gate leakage and channel

mobility of the control oxide devices (EOT ~1 nm) showed good agreement with

previously published values. Working devices were obtained for most of the

experimental splits. But, due to the lack of an optimized etching scheme, large die-to-die

variability was observed with TaN gated devices. Extracted EOT values for the JVD

HfO2 ranged from 1.28 to 2.25 nm, while RTCVD and JVD ZrO2 had EOTs ranging from

1.86 to 2.62 nm. JVD HfO2 and RTCVD ZrO2 had slightly higher leakages than

published values. On the other hand, gate leakage characteristics of RTCVD HfO2 and

JVD ZrO2 were about the same as previously reported. Nevertheless, most of the devices

with HfO2 and ZrO2 met the low operating power gate leakage specifications (0.81 A/cm2

at 1.0 V) for 100 nm and 70 nm technology nodes. However, most of the dielectrics were

thicker than the target value (~1 nm), except for the PVD HfO2. PVD HfO2 dielectrics

with poly-silicon and Ru/W gates were made with EOT as low as 1.2 and 0.9 nm,

respectively. Devices with HfO2 dielectric showed comparable mobility to oxide controls,

but ZrO2 was inferior to SiO2 control devices. The effect of H2 (10% H2 in 90% N2) and

D2 (10% D2 in 90% N2) forming gas annealing on PVD HfO2 with poly-silicon gates was

studied. The annealing was performed at 400 C for 20 minutes. For both H2 and D2

annealing, significant enhancements in drive current and channel mobility were observed,

while negligible change in gate leakage and C-V characteristics were observed. Similar

to the forming gas annealing mechanism of SiO2, this mobility enhancement was

153

attributed to a reduction in interface charges by H2 or D2. Compared to H2, D2 annealing

gave a greater increase in device current and mobility.

7.4. Gate Leakage Current Behavior of HfO2 and Hf Silicate with Poly-silicon and

Metal Gate Electrode

In order to examine the compatibility of poly-silicon gate electrodes with HfO2

and Hf silicate, Ig-Vg characteristics were statistically measured for metal and poly-

silicon gate devices. For both HfO2 and Hf silicate, large device-to-device gate leakage

variations were observed with poly-silicon gates. On the other hand, relatively small

variations were observed with metal gates where the gate leakage scaled nicely with area.

The results suggest that HfO2 and Hf silicate may react during the poly-silicon annealing

process. To separate thermal effects during the high temperature poly-silicon activation

prepared with Hf silicates. These capacitors were annealed at different temperatures (600

ºC – 1000 ºC) for 1 minute. The C-V data revealed that no significant degradation

occurred as a result of high temperature annealing. To examine reactions with the poly-

silicon gate electrode, devices with different poly-silicon gates were prepared. LPCVD

poly-silicon gates were deposited at two different temperatures, 625 ºC and 550 ºC, and

amorphous Si was deposited by RF magnetron sputtering. Considerable degradation was

observed with all poly-silicon gated devices, regardless of the poly-silicon deposition

condition and activation cycle. Even though the high temperature activation cycle alone

had a minor effect, the combination of high temperature annealing and the presence of

silicon gates degraded Hf-based dielectrics.

154

7.5. Gate Leakage Characteristics of Hf Silicate and Effect of Nitridation

A series of capacitors were fabricated using Hf silicate alloys with varied Hf

composition. The measured gate tunneling currents verified theoretical predictions of a

minimum in leakage at an intermediate silicate composition. The intermediate Hf silicate

alloys result in less leakage than pure HfO2 (or SiO2). To have better EOT stability,

nitridation was performed on the bottom and/or the top surface of Hf silicate. The results

show that nitridation plays a significant role in EOT and charge in Hf silicate. Both

surface and interfacial nitridation effectively reduce the increase in EOT: surface

nitridation resulted in 10 % lower EOT than un-nitride films, while interfacial nitridation

gave even lower (~2 nm) EOT. Surface (only) nitridation introduced positive charges in

the dielectric. On the other hand, interface and surface nitridation reduced the amount of

positive changes.

7.6. Future Work

While this dissertation has addressed some of the issues related to the integration

of high K dielectrics and metal gate electrodes, there are still number of topics need to be

examined.

• Although, initial assessments were given in this dissertation, the degradation of

high K dielectrics during the poly-silicon process had not been fully explained.

Aside from electrical data, physical observations (TEM, AFM, and SEM) and

compositional analysis (AES and XPS) may be needed to identify the degradation

mechanism of high K dielectric.

155

156

• The thermal stability of high K gate dielectrics needs to be improved before they

are accepted in volume VLSI manufacturing. Further optimization of surface and

interfacial nitridation is needed and other techniques, such as alloying with Al2O3

have to be studied.

• Even with H2 or D2 forming gas annealing, a significant number of interface states

are still observed with HfO2, compared with pure SiO2. New dielectric deposition

methods and new annealing techniques, such as atomic layer deposition and high

temperature forming gas annealing, may also be needed to reduce the interface

state charges.

• In order to fully explore the dielectrics properties, MOSFETs are needed along

with the capacitors. Fabrication of Hf silicate transistors having various gate

electrodes is needed to examine the device current and mobility.

Appendix A.

Detailed Process Flow for Non Self-Aligned Gate Process Uniformly Doped Wafers

Initial Substrate PMOS: n-type (P doped) (100) wafers: 25, 0.05-1.00 ohms-cm NMOS: p-type (B doped) (100) wafers: 25, 0.5-2.0 ohms-cm 1. Label Wafers

• On backside using diamond tip scribe

2. RCA Clean • 5 min in SC1 (NaOH:H2O2: H2O=1100:1100:5000 ml) at 75 °C followed by a

5 min rinse in DI • 5 min in SC2 ( HCl: H2O2: H2O=1100:1100:5000 ml) at 75 °C followed by a

5 min rinse in DI

3. Grow Pad Oxide – 6.5 nm

• Furnace: D3 (dry oxidation_ • Temperature/Time: 850°C/12 min. • Ambient: O2 + 4.5% HCl • Thickness measurement: 6.6 nm (measured with NANOMETRICS)

4. Substrate Implant

• NMOS: B, 3.4e13 cm-2, 25 KeV, tilt = 7 º • PMOS: P, 1.3e13 cm-2, 28 KeV, tilt = 7 º • The wafers were sent to Ion Implant Service to be implanted

5. RCA Clean (no BHF)

• 5 min in SC1 (NaOH:H2O2: H2O=1100:1100:5000 ml) at 75 °C followed by a 5 min rinse in DI

• 5 min in SC2 ( HCl: H2O2: H2O=1100:1100:5000 ml) at 75 °C followed by a 5 min rinse in DI

6. 30 sec BHF (10:1)

• 30 sec in BHF(10:1) at room temperature followed by a 5 min rinse in DI and dry

157

7. Grow Isolation Oxide-100 nm • Furnace: D1 (wet oxidation) • Temperature/Time: 1000 ºC/6.7min • Ambient: O2 + 2% HCl • Thickness measurement: 1010 nm (measured with NANOMETRICS)

8. Drive in Anneal

• Furnace: D4 • Temperature/Time: 950°C/60min. • Ambient: N2

9. Photolithography for Level 1 (Junction)-Resist coat

• Resist ID: Shiply 510 (positive resist) • Spin speed/time: 4500 rpm/45 sec. • Comments: This level is dark field

10. Photolithography for Level 1 (Junction)-Pre-exposure bake

• Temperature/Time: 90°C/1 min 11. Photolithography for Level 1 (Junction)-Align and expose

• Use GCA800 DSW I-line lithography stepper • Mask set: ERC6 • Level: level 1 (Diffusion) • Expose Time: 1 sec

12. Photolithography for Level 1 (Junction)-Post-exposure bake

• Temperature/Time: 115°C/1 min

13. Photolithography for Level 1 (Junction)-Develop • Time: 60 sec.

14. Photolithography for Level 1 (Junction)-Post-develop bake


158

15. Resist descum • System: March Instruments PM600 asher • Time: 3 min. • Condition: 80 sccm O2 plasma, 600 mtorr, 300 W

16. Wet etch oxide

• 100 sec. in BOE (10% Hf) at room temperature 17. Strip resist and inspect

• Solution: Nanostrip • Time: 10 min. in first Nanostrip bath + 10 min. in second Nanostrip bath

18. Junction Implant

• NMOS: As, 1.5e15cm-2, 15 KeV, tilt = 7 º • PMOS: BF2, 1.0e15 cm-2, 19 KeV, tilt = 7 º • The wafers were sent to Ion Implant Service to be implanted

19. RCA Clean (no BHF)

• 5 min in SC1 (NaOH:H2O2: H2O=1100:1100:5000 ml) at 75 °C followed by a 5 min rinse in DI

• 5 min in SC2 ( HCl: H2O2: H2O=1100:1100:5000 ml) at 75 °C followed by a 5 min rinse in DI

20. Activation anneal (RTA)

• Temperate/Time: 950°C/10 sec. • Ambient: N2

21. LPCVD SiO2-100 nm

• Temperature/Time: 410 ºC/ 16 min. • Ambient: 210 sccm of O2 and 87 sccm of LTO • Pressure: 750 mtorr

22. Photolithography for Level 2 (active and contact)-Resist coat

• Resist ID: Shiply 510 (positive resist) • Spin speed/time: 4500 rpm/45 sec. • Comments: This level is dark field

159

23. Photolithography for Level 2 (active and contact)-Pre-exposure bake • Temperature/Time: 90°C/1 min

24. Photolithography for Level 2 (active and contact)-Align and expose

• Use GCA800 DSW I-line lithography stepper • Mask set: ERC6 • Level: leve 2 (active and contact) • Expose Time: 1 sec

25. Photolithography for Level 2 (active and contact)-Post-exposure bake


26. Photolithography for Level 2 (active and contact)-Develop • Time: 60 sec.

27. Photolithography for Level 2 (active and contact)-Post-develop bake

• Temperature/Time: 115°C/5 min 28. Resist descum

• System: March Instruments PM600 asher • Time: 3 min. • Condition: 80 sccm O2 plasma, 600 mtorr, 300 W

29. Wet etch oxide

• 100 sec. in BOE (10% Hf) at room temperature 30. Strip resist and inspect


160

31. RCA Clean (no BHF) • 5 min in SC1 (NaOH:H2O2: H2O=1100:1100:5000 ml) at 75 °C followed by a

5 min rinse in DI • 5 min in SC2 ( HCl: H2O2: H2O=1100:1100:5000 ml) at 75 °C followed by a

5 min rinse in DI 32. Dilute HF (1% HF) dip prior to gate oxide deposition

• 20 sec. in 1 % HF at room temerature 33. Deposit gate dielectrics and metal gate electrodes

• Wafers were shipped out to receive advanced gate stacks 34. Photolithography for Level 3 (gate metal)-Resist coat

• Resist ID: Shiply 510 (positive resist) • Spin speed/time: 4500 rpm/45 sec. • Comments: This level is light field

35. Photolithography for Level 3 (gate metal)-Pre-exposure bake • Temperature/Time: 90°C/1 min

36. Photolithography for Level 3 (gate metal)-Align and expose

• Use GCA800 DSW I-line lithography stepper • Mask set: ERC6 • Level: level 3 (Gate electrode) • Expose Time: 1 sec

37. Photolithography for Level 3 (gate metal)-Post-exposure bake


38. Photolithography for Level 3 (gate metal)-Develop • Time: 60 sec.

39. Photolithography for Level 3 (gate metal)-Post-develop bake

• Temperature/Time: 115°C/5 min 161


41. Etch gate electrode metal and gate dielectric

• Appropriate etchings were performed for each gate stacks 42. Strip resist and inspect


43. Lift-off photolithography for Level 4 (contact metal)-Resist coat

• Resist ID: Shipley 1813 + 3% imidazole (negative resist) • Spin speed/time: 4500 rpm/45 sec • This level is light field. Image reversal need to be done for Lift off

44. Lift-off photolithography for Level 4 (contact metal)-Pre-exposure bake


45. Lift-off photolithography for Level 4 (contact metal)-Align and expose

• Use GCA800 DSW I-line lithography stepper • Mask set: ERC6 • Level: level 4 (Contact Metal) • Time: 4 sec

46. Lift-off photolithography for Level 4 (contact metal)-exposure bake • Temperature/Time: 90°C/1 min

47. Lift-off photolithography for Level 4 (contact metal)- Flood exposure

• Time: 60 sec. On King Karl

48. Lift-off photolithography for Level 4 (contact metal)-develop

• Time: 60 sec.

162

163


50. Back door etch

• Solution: Dilute BOE (1% Hf) • Time: 30 sec

51. Evaporate contact metals- Ti/Al (100/400 nm)

• System: thermal evaporation 52. Lift off contact metals

• Solution: Accustrip 53. Front side Resist coat

• Resist ID: Shipley 1813 • Spin speed/time: 4500 rpm/45 sec.

54. Front side Resist bake

• Temperature/Time: 115°C/ 5 min 55. Etch backside in BHF until clear 56. Evaporate Al backside- Al (0.1-0.5 µm)

• System: thermal evaporation 57. Strip front side resist and inspect

• Solution: Accustrip • Time: 10 min

58. Forming gas anneal

• Temperature/Time: 400°C/ 30 min

Appendix B.

ERC 6 MASK SET GROUNDRULES (developed with Deepak Johri)

1. PROCESS GROUNDRULES Minimum feature size on mask Alignment Bias (AB, DAB) = 0.00 ± 0.35 Lithography Bias for mask#1 (LB1, DLB1) = -0.10 ± 0.20 Lithography Bias for mask#2 (LB2, DLB2) = -0.10 ± 0.20 Lithography Bias for mask#3 (LB3, DLB3) = -0.10 ± 0.20 Lithography Bias for mask#4 (LB4, DLB4) = -0.10 ± 0.20 Oxide1 Etch Bias (OE1, DOE1) = -0.20 ± 0.20 Oxide2 Etch Bias (OE2, DVE2) = -0.20 ± 0.20 Gate Metal Etch Bias (GME, DGME) = -0.50 ± 0.50 Contact Metal Lift-off Bias (CME, DCME) = 0.00 ± 0.20 Lateral Diffusion of Junction$ (LD, DLD) = 0.04 ± 0.02 Minimum Grid Spacing = 0.10 * Metal Probe Pads are 100µm × 100µm, ** Minimum distance between Probe Pads is 100 µm, *** Minimum size of the Contact Hole is 0.8µm × 0.8µm, $ Assuming that the Junction Depth is 50 nm 2. ALIGNMENT SCHEME Level 2 to Level 1 Level 3 to Level 1 Level 4 to Level 2 Level 1: Junction (dark field mask) Level 2: Contact Holes and Gate (dark field mask) Level 3: Gate Dielectric and Metal (light filed mask) Level 4: Contact Metal (light filed mask)

164

3. CALCULATIONS FOR EXPECTED FEATURE SIZE ON WAFER (a) Channel Length: (Level 1) Figure 1a. Bias of L = LB1 + OE1 + 2LD = − 0.1 − 0.2 − 0.08 = − 0.38 Tolerance = (DLB1)2 + (DOE1)2 + (2 DLD)2 = (0.2)2 + (0.2)2 + (2×0.02)2 = ±0.29

If the Channel Length on Mask is L then the Expected Channel Length on Wafer would be given as: L − 0.38 ± 0.29

(b) Channel Width: (Level 2) Figure 1b. Bias of W = −LB2 − OE2 = − (− 0.1 − 0.2) = 0.30 Tolerance = (LB2)2 + (OE2/)21/2 = (0.2)2 + (0.2)2 1/2 = ±0.29

If the Channel Width on Mask is W then the Expected Channel Width on Wafer would be given as: W + 0.30 ± 0.29

(c) Gate Electrode: (Level 3) Figure 1c. Bias of X = LB3 + GME = −0.1 − 0.5 = − 0.6 Tolerance = (DLB3)2 + (DGME)21/2 = (0.2)2 + (0.5)2 1/2 = ±0.54

If the Gate Electrode has the Length of X on Mask then the Expected Gate Electrode Length on Wafer would be given as: X − 0.6 ± 0.54

165

(d) Contact Metal: (Level 4) Figure 1d. Bias of Y = − LB4 + CME = 0.1 + 0.00 = 0.10 Tolerance = (DLB4)2 + (DCME)21/2 = (0.2)2 + (0.2)2 1/2 = ±0.28

If the Contact Metal has the dimension Y on Mask then the Expected Contact Metal on Wafer would be given as: Y + 0.10 ± 0.28

4. CALCULATIONS FOR OVERLAYS BETWEEN VARIOUS FEATURES (a) Gate Opening to Diffusion (along Channel Length): (Figure 2a) Bias in “a” = AB + 1/2 ( − LB2 − OE2 − LB1 − OE1 − 2LD ) = 0.00 +0.5 (0.1 + 0.200 + 0.10 + 0.20 + 0.08) = 0.34 Tolerance = m*(DAB)2 + (DLB1/2)2 + (DLB2/2)2 + (DOE1/2)2 + (DOE2/2)2 + (DLD)21/2 = 1*(0.35)2 + (0.2/2)2 + (0.2/2)2 + (0.2/2)2 + (0.2/2)2 + (0.02)21/2 = ± 0.41 Worst Case Change = 0.34 − 0.41 = − 0.07 Minimum Overlap on Mask = 0.1

Overlap finally taken because of the minimum layout grid spacing is 0.1 the overlap considered = 0.1 µm.

(b) Gate Opening to Diffusion (along Channel Width): (Figure 2b) Bias in “b” = AB + 1/2 (LB1 + OE1 + 2LD − LB2 − OE2 ) = 0.00 + 0.5(0.1 + 0.2 + 0.08 + 0.1 + 0.2) = 0.04 Tolerance = m*(DAB)2 + (DLB1/2)2 + (DLB2/2)2 + (DOE1/2)2 + (DOE2/2)2 + (DLD)21/2 = 1*(0.35)2 + (0.2/2)2 + (0.2/2)2 + (0.2/2)2 + (0.2/2)2 + (0.02)21/2 = ± 0.41 Worst Case Change = 0.04 − 0.41 = − 0.37

166

Minimum Overlap on Mask = + 0.4

Overlap finally taken because of the minimum layout grid spacing is 0.1 the overlap considered = + 0.4 µm.

(c) Gate Electrode over Gate Opening: (Figure 2c) Bias in “c” = AB + 1/2 (LB3 + LB2 + OE2 + GME) = 0.00 + 0.5( − 0.1 − 0.1 − 0.2 − 0.5) = −0.45 Tolerance = m*(DAB)2 + (DLB3/2)2 + (DLB2/2)2 + (DOE2/2)2 + (DGME/2)21/2 = 2*(0.35)2 + (0.2/2)2 + (0.2/2)2 + (0.2/2)2 + (0.5/2)21/2 = ± 0.58 Worst Case Change = −0.45 − 0.58 = − 1.03 Minimum Overlap on Mask = 1.1 Overlap finally taken because of the minimum layout grid spacing is 0.1 the

overlap considered = 1.1 µm. (d) Diffusion to Contact Hole: (Figure 2d) Bias = AB + 1/2 (− LB1 − OE1 + LB2 + OE2 + 2LD) = 0.00 + 0.5(+ 0.1 + 0.2 − 0.1 − 0.2 + 0.08) = + 0.04 Tolerance = m*(DAB)2 + (DLD)2 + (DOE1/2)2 + (DLB1/2)2 + (DOE2/2)2+(DLB2/2)21/2 = 1*(0.35)2 + (0.02)2 + (0.2/2)2 + (0.2/2)2 + (0.2/2)2 + (0.2/2)21/2 = ± 0.4 Worst Case Change = 0.04 − 0.4 = − 0.36 Minimum Overlap on Mask = 0.4

Overlap finally taken because of the minimum layout grid spacing is 0.1 the overlap considered = 0.4 µm.

(e) Metal overlap of Contact: (Figure 2e) Bias = AB + 1/2 (− LB4 + LB2 + OE2 − CME) = 0.00 + 0.5(+ 0.1 − 0.1 − 0.2 + 0.00) = − 0.10

167

Tolerance = m*(DAB)2 + (DLB4/2)2 + (DLB2/2)2 + (DOE2/2)2 + (DCME/2)21/2

= 1*(0.35)2 + (0.2/2)2 + (0.2/2)2 + (0.2/2)2 (0.2/2)21/2 = ±0.403 Minimum Overlap = − 0.10 − 0.403 = − 0.503 Overlap finally taken because of the minimum layout grid spacing is 0.1 the

overlap considered = 0.6 µm.

168

Diffusion Area Level 1

LB2OE2

Level 2 W

L

Figure 1a.

Diffusion Area Level 1

DE 1

LD

LB 1

L

Figure 1b.

169

LB3

GME

Level 3

Level 2

LX

Level 1

Figure 1c. Y

Level 4

Level 2

CME

LB4OE2 Level 1

Figure 1d.

170

Gate opening

Junction LB1

LD

OE1

OE2

LB2

a

Figure 2a.

LDOE2LB2

LB1OE1

b

Gate opening

Junction

Figure 2b.

LB2OE2

Gate electrode

c

LB3GME

Gate opening

Junction

Figure 2c.

171

Junction

Contact hole

d

DELB2

LB1 OE1L

Figure 2d.

Contact metal Junction

Contact hole

e

DE2LB2CMELB4

Figure 2e.

172

Appendix C.

ERC 6 Mask Set The ERC 6 mask set was designed to facilitate more rapid evaluation of high-K dielectrics and new gate electrode materials. A layout of the new mask set is shown in Fig. 1. The ERC-6 mask set consists of four levels: level 10, a dark field junction level; 20, a dark field contact holes level; 30, a light field gate and gate dielectric level; and 40, a dark field contact metal level. Table 1 summarizes the key structures in the ERC 6 mask set.

A

3 4 51 2

B

C

D

E

F

G

H

I

J

Figure 1. ERC-6 chip die.

173

Table 1. Summary of test structures in ERC 6 mask set

Structures Description Cells Resolution targets A1, J1, F3,

A5, F5 24 devices: W=50µm, L=50µm I2, DE4(F),

B4, F5 21 devices: W =10 µm, L=0.6, 0.7, 0.8, 0.9, 1,

1.5, 2, 2.5, 3, 3.5, 4, 5, 6, 7, 10, 15, 25, 30, 50, 70, 100 µm

D1, FG2(B), A4,

Directly probe-able MOSFET

21 devices: W = 3 µm, L=0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 6, 7, 10, 15, 25, 30, 50, 70, 100 µm

CD2(F), E2, I3, I5

24 devices: W = 1 µm, L = 2, 3, 4, 5, 7, 10, 15, 20, 50 µm W = 5 µm, L = 2, 3, 4, 5, 7, 10, 15, 20, 50 µm W = 10 µm, L = 2, 3, 4, 5, 7, 10, 15, 20, 50 µm

FG2(F), D3, H4

21 devices: W =50 µm, L=0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 6, 7, 10, 15, 25, 30, 50, 70, 100 µm

G3, C5

6 devices: W=100µm, L=100µm A3, E5 Indirectly probe-able

MOSFET 16 devices: W = 10 µm, L = 0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 7, 10, 15, 20 µm

E1

16 devices: W = 3 µm, L = 0.6, 0.7, 0.8, 0.9, 1, 1.5, 2, 2.5, 3, 3.5, 4, 5, 7, 10, 15, 20 µm

CD2(B), B3, G5

Think oxide MOSFET 6 devices: L = 30, 40, 50, 60, 70, 80 µm B2, H5 Thin oxide capacitors 100 µm x 100 µm and 200 µm x 200 µm

capacitors. Comb capacitors (H3, D5) and smaller capacitors (F1, C4) are included.

H3, D5, F1, C4, J3(B)

Thick oxide capacitors 100 µm x 100 µm and 200 µm x 200 µm capacitors. Smaller capacitors (A2, F4) are included.

A2, F4 J3(F)

Sheet resistance Measurement

Van der Pauw and 4-point probe structure for sheet resistance measurements.

I1, E3, B5

structures 4-point probe structure for sheet resistance measurements.

J2, G4

Contact resistance measurement

structures

TLTR-EE and TLTR-CE structure for contact resistance measurements.

BC1, GH1

174

Resolution Targets Cell A1

Figure 2. Resolution target

Directly probe-able MOSFETs Cell I2

Figure 3. 50µm x 50µm (gate width x gate length) directly probe-able MOSFETs.

175

Cell I3

Figure 4. Directly probe-able MOSFETs (fixed gate width at 3 µm, various gate lengths (in µm) were indicated in the figure) Cell E1

176

Figure 5. Directly probe-able MOSFETs (fixed gate width at 10 µm, various gate lengths (in µm) were indicated in the figure)

Cell D3

Figure 6. Directly probe-able MOSFETs (three different gate widths 1,5,10 µm with various gate lengths (in µm) were indicated in the figure) Cell G3

Figure 7. Directly probe-able MOSFETs (fixed gate width at 50 µm, various gate lengths (in µm) were indicated in the figure)

177

Indirectly probe-able MOSFETS Cell A3

Figure 8. Indirectly probe-able MOSFETS (gate width/gate length = 100 µm/100 µm) Cell E1

Figure 9. Indirectly probe-able MOSFETs (fixed gate width at 10 µm, various gate lengths (in µm) were indicated in the figure)

178

Cell B3

Figure 10. Indirectly probe-able MOSFETs (fixed gate width at 3 µm, various gate lengths (in µm) were indicated in the figure)

Thick oxide MOSFETs

Cell B2

Figure 11. Thick oxide MOSFETS (size indicated in µm)

179

Capacitors Cell H3

Figure 12. Thin oxide square capacitors and comb capacitor Cell F1

Figure 13. Square capacitors

180

Sheet resistance measurement structures

Cell I1

Figure 14. Van der Pauw and 4-point sheet resistance structures Cell J2

Figure 15. 4-point probe sheet resistance measurement structures ( line width dimension and distance between the terminals indicated in µm

181

Contact resistance measurement structures

Cell BC1

Figure 16. TLTR-EE and TLTR-CE contact resistance measurement structures

182

FABRICATION AND DEVICE CHARACTERIZATION OF …

Documents

Transcript of FABRICATION AND DEVICE CHARACTERIZATION OF …