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Transactions of The Japan Institute of Electronics Packaging Vol. 5, No. 1, 2012

1. IntroductionThree-dimensional packaging using an embedded sub-

strate is being developed to achieve miniaturization of the

area for the capacitors in the electrical substrate. This

embedded capacitor is manufactured for a three-dimen-

sional structure rather than surface packaging technology.

Embedded substrate technology is already used to some

extent in the packaging process, but it mostly involves tip

products rather than elements. Thin film capacitors, pack-

aged into the electrical substrate, will become a new and

useful technology in the near future. Generally, the prepa-

ration of a high-dielectric-constant film requires the use of

heat treatment over 600°C. However, this high-tempera-

ture process causes serious damage to the electrical sub-

strate that is popular for electrical products. Nano-transfer,

therefore, could be a promising method for creating thin

film capacitors because it involves preparation on a heat-

resistive substrate followed by a transfer process onto the

polymer substrate.[1] The concept of the method is shown

in Fig. 1. This method consists of release and transfer pro-

cesses. First, a capacitor is fabricated on an outer substrate

that has high heat resistance, and it is then peeled from

that substrate and transferred to the application substrate.

The principle examination procedures for the nano-

transfer method have been confirmed for use with a Pt

electrode, but a suitable quantitative structure design has

not yet been found.

Among the various kinds of capacitor materials in use,

lead zirconate titanate (PZT) systems are familiar, but

materials containing lead will be replaced by other mate-

rial systems. Barium titanate (BaTiO3) is one lead-free fer-

roelectric material and is used in this study.

In our previous studies, we fabricated PZT (Pb(Zrx,Ti1–x)

O3) thin film capacitors to establish the process for the

[Technical Paper]

Fabrication and Characterization of Ferroelectric PZT and BaTiO3

Thin Films on Releasable Electrode StructuresErika Komine*, Motoyuki Ozaki*, Tadatomo Suga*, Masaaki Ichiki**,***, and Toshihiro Itoh**

*Department of Precision Engineering, the University of Tokyo, 7-3-1 Hongo, Bunkyo, Tokyo 113-8656, Japan

**Research Center of Ubiquitous MEMS and Micro Engineering, National Institute of Industrial Science and Technology (AIST), 1-2-1 Namiki,

Tsukuba, Ibaraki 305-8564, Japan

***JST-Presto, Japan Science and Technology Agency, 4-1-8, Honcho, Kawaguchi-shi, Saitama 332-0012 Japan

(Received June 29, 2012; accepted October 11, 2012)

Abstract

The physical and structural properties of the ferroelectric capacitors on a releasable substrate were shown for the clari-

fication of effective process parameters in the fabrication of high-density capacitors. A Ti-bonding layer located at the

corner is found to be effective for the prevention of the destruction during the crystallization process. The tensile stress

of the capacitor films is caused by the deflection of the film surface. The crystallized capacitors have a perovskite struc-

ture and the same characterization as that on the non-releasable substrate. This paper describes the preparation process

and also the estimation of the capacitors for the nano-transfer method. In this study, the releasing property of the thin

film was evaluated as an important factor in this process. To evaluate the releasing property of the thin film, a tape test

was performed and the conditions of the deposition and substrate were considered for PZT.

Keywords: Thin Films, PZT, BTO, Embedded Substrate, Nano-transfer, Capacitor

Fig. 1 Process flow of nanotransfer method.

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Komine et al.: Ferroelectric Thin Films on Releasable Electrode Structure (2/7)

nano-transfer method. However there were some prob-

lems, such as thin films being destroyed during the film

deposition process and not peeling off under some condi-

tions. It is, therefore, necessary to clarify the main process

parameters in the film preparation procedure for PZT.

On the other hand, BaTiO3 film has higher internal

stress than that of PZT because of the lower density of the

raw solution materials. As a result, it is necessary to pre-

pare another type of releasable substrate for the BaTiO3

films. The weak adhesion force between the Pt and SiO2

layer poses a difficulty for the transfer of prepared capaci-

tors onto the polymer substrate. This is a common prob-

lem for ferroelectric films prepared on a releasable sub-

strate using the metal organic decomposition (MOD)

method. The internal stress of the films during the heating

process causes the destruction of the structure. In a previ-

ous study, a Ti layer was introduced as the bonding layer

between the Pt and SiO2 in the prepared structure. How-

ever, the bonding of the Ti layer is too high to release the

thin film capacitors in the release process. Therefore, it is

necessary to optimize the thickness and design of the Ti

layer to improve the film’s characteristics and the nano-

transfer method.

The purposes of this study are as follows: 1) Study the

effect of heating on the deflection of the substrate and esti-

mate the electrical properties of prepared films. 2) Con-

firm the effect of the double layer structure of the elec-

trode and optimization of the shape of the electrode. 3)

Clarify the relationships between PZT films and Pt in the

releasing process.

2. Experimental Procedure for PZT (EXP-1)2.1 Thin film fabrication process

Figure 2 shows the process of forming the PZT capaci-

tor. A 4-inch Si wafer was used as the substrate. A 300 nm

thick SiO2 film was formed in an oxidation furnace. After

that, the Si wafer was diced into 20 mm squares. Then, the

Pt layer for the bottom electrode was deposited by sputter-

ing. Pt was sputtered variously from thicknesses of 40 nm

to 2,500 nm to investigate the relationship between the Pt

thickness and the release property of the interface.

PZT thin films were fabricated on the bottom electrode

using metal organic decomposition (MOD). The MOD

method is a chemical solution deposition (CSD) method

that is similar to the sol-gel method. Unlike other thin film

deposition methods, MOD does not need a vacuum, thus a

thin film can be produced easily and at low cost. The PZT

was deposited using a spin coater at 2,500 rpm and fol-

lowed by rapid thermal annealing (RTA). The maximum

temperature was 700°C. These MOD processes consisting

of deposition and annealing were repeated 10 times to

build up a thickness of 2,000 nm to 2,500 nm which would

provide an adequate PZT thickness to prevent leakage cur-

rent.

After the PZT thin films were formed, the Pt layer for

the upper electrode was deposited.

Figure 3 shows a schematic of the PZT capacitor.

2.2 Evaluation methodThe structural, electrical and releasing properties of this

capacitor were then measured.

The structural properties were measured using x-ray

diffraction (XRD). The electrical properties were mea-

sured with an LCR (inductance, capacitance and resis-

tance) meter.

The releasing properties were investigated using a tape

peel test, a qualitative test method in which a tape affixed

to the sample surface is peeled off. The Pt film stress was

also measured to clarify its effect on the release property.

3. Experimental Procedure for BaTiO3 (EXP-2)3.1 Double-layered electrode structure

In a previous study, a double-layered electrode struc-

ture, consisting of two kinds of areas with and without the

Ti layer, was prepared.[2] In this study, the Ti layer of the

electrode structure is used to protect the release during Fig. 2 Process flow of the PZT capacitor.

Fig. 3 Schematic of PZT thin film capacitor.

(a) Si Oxidation. (b) Pt sputtering for bottom electrode.

(d) Pt sputtering for upper electrode.

(e) PZT etching.

(c) PZTdeposition by using MOD method.

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the heat treatment. The central area, without the Ti, is

used for the releasable capacitor. The structure of the sub-

strate is shown in Fig. 4 and is almost the same as that in

Fig. 2.

However, only one kind of electrode design has been

prepared up to now. It is shown in Fig. 5. It will be neces-

sary to clarify a suitable structural design for the nano-

transfer method that enables wider application. The target

will be the development of another electrode structure that

has more area for the Pt layer and high protection against

destruction during the heating process. The establishment

of a method to prepare BaTiO3 capacitors at the chip scale

will be another problem. Dicing after preparation at wafer

scale was not successful because of the destruction of the

structure. Development of a dicing process from wafer to

chip is expected to be useful for improving production.

3.2 Preparation of the double-layered electrode structure for BaTiO3 (EXP-2-1)

Several variations of capacitor chips composed of a dou-

ble-layered electrode structure were prepared and heat

treatment was applied to clarify their suitability in an

expected process flow. Figure 6 shows the design of the

prepared samples. Three designs were prepared: circular,

square with rounded corners, and square. Three sizes

were prepared: 12 mm, 14 mm and 16 mm.

Capacitor chips with a uniform lower electrode were

also prepared using the same process for comparison with

the above samples. Three kinds of Pt lower electrodes

were prepared: 1) formed at room temperature, 2) formed

at 200°C, and 3) formed as Pt on Ti at room temperature.

Figure 7 shows the process flow for preparing the lower

electrode with the double-layered structure. This prepara-

tion was performed on wafer and diced into chips 20 mm ×

20 mm. The capacitor film was prepared onto the above

chip substrate.

BaTiO3 films of 15 layers were prepared using MOD.

The condition of the spin coater was 2,500 rpm for 20 sec-

onds and the crystallization condition was 700°C for 3 min-

utes. The structure and electrical properties of the sam-

ples formed without destruction of the structure were

evaluated. X-ray diffraction (XRD) analysis was conducted

and the dielectric constant and film thickness were investi-

gated.

3.3 Evaluation of the release depending of the design of the lower electrode (EXP-2-2)

Based on an assumption from the results of Exp-2-1, an

additional experiment was performed to confirm that

using Ti in the corner area protected the structure from

destruction. We prepared four kinds of samples to clarify

this. The designs are shown in Fig. 8. These are the

designs of the lower electrode of the Pt and Ti layer. After

the four kinds of electrodes were formed, BaTiO3 films

Fig. 4 Structures of releasable and non-releasable substrates for ferroelectrics.

Fig. 5 Double-layered structure of thin film capacitor for BaTiO3.

Fig. 6 Structures of the lower electrode of the samples.

Fig. 7 Process flow of preparing the double-layered struc-ture of the capacitor.

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Komine et al.: Ferroelectric Thin Films on Releasable Electrode Structure (4/7)

were prepared onto the lower electrode, as shown in Fig.

7. The preparation process of the films was the same as

used for Exp-2-1.

4. Experimental Results and Considerations4.1 PZT (EXP-1)

4.1.1 Fabrication stability of capacitorTo investigate the stability of the thin film fabrication,

the deposition temperature and film thickness conditions

of the bottom Pt electrode layer were changed and PZT

thin films were prepared on it.

On the sample with a Pt thickness of 1 µm and a deposi-

tion temperature of 200°C, 10 PZT layers could be fabri-

cated. On the other hand, on the sample with a Pt thick-

ness of 1 µm and deposition at room temperature (RT),

stable PZT layers could not be fabricated because the sam-

ple was destroyed after the second layer was added.

Figure 9 shows the displacement distribution of the Pt

layer measured before deposition of the PZT thin film. The

Pt layer had tensile stress caused by the 200°C deposition

and compressive stress caused by the RT deposition.

Therefore, at different deposition temperatures, the stress

was found to have reversed tension and compression.

Thus the stress of the Pt layer was inversed, and stable

fabrication became possible.

A PZT thin film generally exhibits tensile stress and the

Pt layer fabricated under a heated condition has the same

tensile stress. We think that matching the stress direction

causes the stress relaxation of the capacitor.

Figure 10 shows the temperature dependence of the Pt

layer stress on a releasable substrate. As the temperature

changed, the direction of the Pt film stress changed gradu-

ally. By changing the deposition temperature, compressive

stress changed to tensile stress. Therefore in order to

obtain a tensile stress, heating to more than 200°C is

required. Therefore stable fabrication of PZT film requires

at least 200°C.

4.1.2 Thin film structureFigure 11 shows the XRD patterns of the fabricated PZT

thin films.

The XRD analysis revealed the intense peak of (110) ori-

entation that was the PZT perovskite structure. After the

10th PZT layer was fabricated, the (110) peak intensity

became higher.

Fig. 8 Design of the lower electrode including Pt and Ti in 4 locations.

Fig. 9 Displacement distribution before and after the deposi-tion of Pt thin film.

Fig. 10 Temperature dependence of Pt internal stress on releasable substrate.

Fig. 11 XRD patterns of PZT thin films.

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4.1.3 Electrical propertiesFigure 12 shows an example of the hysteresis loop. This

loop shape was common to all the samples. Dielectric con-

stants were about 1,300 in all capacitors, and dependency

on the deposition condition (Pt layer thickness and deposi-

tion temperature) was not observed. It was found that the

electrical characteristics do not depend on the deposition

condition of Pt layer.

The electrical characteristics of capacitors fabricated on

a releasable substrate were compared with those of con-

ventional ones. Table 1 shows a comparison of the capaci-

tors. Permittivity was not inferior to conventional capaci-

tors. Remanent polarization was about the same as for

conventional capacitors. The coercive field was larger than

that of conventional capacitors, because the crystal struc-

ture is different from that of conventional capacitors. We

confirmed that the capacitor on the releasable substrate

had 110 orientation. However it is well known that a con-

ventional capacitor has 100 orientation. Generally, a capaci-

tor which has 100 orientation shows high electrical proper-

ties. So it is possible to equal  this by improvement of the

film quality.

That is, it is expected that the electrical characteristics

can be improved by changing the crystal orientation.

4.1.4 Releasing propertiesThe releasing properties of the SiO2-Pt interface were

investigated using the tape peeling test.

From the tape test results, as shown in Fig. 13, we found

that the release properties could be divided into three

types: the capacitor could be peeled off completely, the

capacitor could be peeled off partially, and the capacitor

could not be peeled off.[3]

The Pt thickness and PZT thickness are used as param-

eters in Fig. 13. The gray area is the region where peeling

is expected to occur. In the sample with the non-peeling

area, the PZT was firmly adhered at the SiO2-Pt interface,

and also did not peel off by any means other than by tape.

As seen in Fig. 13, the thicker the Pt layer, the more eas-

ily the film releases. The possible reason for this result

may be that the adhesion between the SiO2-Pt was weak-

ened by the thickness of the Pt layer which had greater

stress, thus the capacitor became easier to peel.

On the other hand, the capacitor cannot be peeled off

when the PZT is thicker. We think that the reason for this

is diffusion at SiO2-Pt interface. Increasing the number of

thermal processes caused diffusion and made it impossi-

ble to release.

4.2 BaTiO3 (EXP-2)4.2.1 Results and discussion of Exp-2-1All 9 variations of the BaTiO3 samples shown in Fig. 6

were prepared without destruction in the formation pro-

cess. The appearance of the prepared samples is shown in

Fig. 6. A patterned Ti layer is useful for protecting the

crystallization from destruction during the heat treatment.

The film thickness of the prepared samples ranged from

1.0 to 1.2 mm. The dielectric constant of the BaTiO3 films

ranged from 300 to 600, which is almost the same as that

which has previously been reported. The results are sum-

Fig. 12 Hysteresis loop of PZT.

Fig. 13 Releasing property.

Table 1 Electrical property of PZT capacitors.

Pt deposition temperature

Pt thickness (nm)

Permittivity Pr (mC/cm2) Ec (kV/cm)

Conventional capacitor[4] RT 150 1154 14.9 33.5

Capacitor on releasable snbstrate

200°C 1000 1375 10.2 59.7RT 1000 — — —

200°C 150 1348 13.4 43.4RT 150 1252 15.2 75.5

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Komine et al.: Ferroelectric Thin Films on Releasable Electrode Structure (6/7)

marized in Table 2. A perovskite structure was confirmed

in the crystal structure by an XRD analysis, as shown in

Fig. 14. Figure 14 shows that the orientation is the (110)

preferred in this experiment.

Figure 15 shows that the coated film on the Pt lower

electrode could not be crystallized and that the structure

was destroyed. On the other hand, the film coated on the

Pt/Ti lower electrode was crystallized without destruc-

tion.

A tape test was performed to evaluate the release of the

prepared capacitors from the substrate. No capacitor was

released from the substrate of the lower electrode with the

Ti layer. The capacitors were easily released from the Pt/

Ti electrode. These results show that the Ti layer has a

strong bonding force between the substrate and the capac-

itors. In the previous study, almost the same process was

carried out as expected and into the destruction and/or

release during the process. These results show that there

is an optimum design of the Ti layer of the lower electrode

for successful use of the nano-transfer method. A pat-

terned Ti layer is effective for this proposed process.

4.2.2 Results and discussion of Exp-2-2The No. ① sample shown in Fig. 16 was crystallized

successfully in the preparation process without destruc-

tion. The No. ② and ③ samples were partially crystallized;

the area of the Pt/Ti electrode was successful but the part

with only Pt was partially destroyed. This destruction was

partial and was different from the total destruction shown

in Fig. 16. Local destruction on the Pt layer only was

observed. Uniform crystallization was achieved for the No.

④ sample without destruction.

Although the areas of the No. ② and ③ samples are the

same as that of the No. ① sample and some of the samples

in EXP-2-1, the structure was destroyed during crystalliza-

tion. This shows the effectiveness of the Ti layer at the

corner area for protecting against destruction during the

crystallization process.

On the other hand, this was not the case for the No. ④

sample in spite of the location of the Ti. The No. ④ sample

was not destroyed during crystallization. This might have

occurred for the following reasons: 1) the large area of the

Ti layer or 2) damage caused by heat treatment repeated

over ten times. The design of the electrode also has differ-

ent symmetry from the samples in EXP-2-1. Protection

from destruction could have been caused by the large Ti

layer having a strong bonding force between the wafer and

lower electrode even in a low-symmetry design. Repeated

heat treatments would lead to the diffusion of the Ti in the

larger volume of the film structure.

Table 2 Summary of experimental results of BaTiO3.

Pattern SizeFilm fabri-cation

Film thick-ness

εr

Circle

16 mm ○ 1.1 µm —

14 mm ○ 1.2 µm 360

12 mm ○ 1 µm 480

Square with rounded corner

16 mm ○ 1.2 µm —

14 mm ○ 1.2 µm 590

12 mm ○ 1.3 µm 490

Square

16 mm ○ 1.2 µm 570

14 mm ○ 1.4 µm 650

12 mm ○ 1.4 µm 540

Without pattern (Pt, 200°C) × — —

Without pattern (Pt, RT) × — —

Without pattern (Ti/Pt) ○ 1.2 µm 650

Fig. 14 X-ray diffraction analysis of the formed BaTiO3 films.

Fig. 15 15-layer BaTiO3 films on Pt/Ti lower electrode. Appearance of sample destruction at crystallization.

Fig. 16 Surfaces of the prepared samples after crystalliza-tion of 15 layers of BaTiO3.

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5. ConclusionsWe investigated the correlation between the releasing

properties and fabrication conditions in the nano-transfer

method. We found that by changing the deposition condi-

tions and thickness of the Pt layer to control and change

the stress, stable fabrication of a PZT capacitor is possible.

Therefore, substrate heating during Pt sputtering is effec-

tive to fabricate the PZT films for this study. We evaluated

the characteristics of the capacitors, and confirmed that

the performance meets the basic requirements. Also, we

investigated the correlation of the thickness and releasing

characteristics and obtained basic knowledge for future

application.

Lead-free ferroelectric thin films were prepared on a

releasable substrate as an investigation of chip production.

The process flow of the film preparation was established as

expected. This will lead to development of a packaging

technique for polymer substrates.

The formed films have the random orientation of a

perovskite structure and a dielectric constant of about 650.

This indicates that these thin films have adequate charac-

teristics and crystal structures to provide improved perfor-

mance. The main focus of this study is the film preparation

using lead-free dielectric BaTiO3. It will be possible for this

process technology to be applied to other ferroelectrics,

including Pb.

AcknowledgementWe would like to show our appreciation for Mr. I. Terada

and Mr. M. Obata for their assistance in the preparation of

the samples and Ms. T. Tanaka for the preparation of the

manuscript of this article.

References[1] S. Makino, “The Nano-Transfer Technology of the

PZT Capacitor for the Application of Embedded Sub-

strate,” ICEP Proceedings, pp. 255–259, 2009.

[2] T. Hosono, “Electrode Structure for Ferroelectric

Thin Films and Application to the Nanotransfer

Method,” ICEP Proceedings, TC2-3, pp. 296–299,

2010.

[3] K. Iimura, “EA Release Property of High-Permittivity

Thin Film Manufactured with Nano-Transfer Method,”

ICEP 2010 Proceedings, pp. 292–295, 2010.

[4] K. Sueshige, “EHomogenizing Piezoelectric Film and

application to Wafer Level Film Preparation,” ICEP

2012 proceedings, pp. 218–221, 2012.

Erika KomineShe is a student of Department of Precision Engineering, Graduate School of Engineer-ing, The University of Tokyo. She received BS from Department of Mechanical and Aerospace Engineering, Faculty of Engi-neering, Tohoku University in 2011. Her research is the preparation of ferroelectric

materials and its application to MEMS.

Motoyuki OzakiHe is a MS course student of Department of Precision Engineering, School of Engineer-ing, The University of Tokyo. He received BS from Dept. of Precision Engineering, Faculty of Engineering, The University of Tokyo in 2012.

Tadatomo SugaProfessor of School of Engineering, The Uni-versity of Tokyo. He received the M.S. degree in precision engineering from the University of Tokyo in 1979. He joined the Max-Planck Institut für Metallforschung, Stuttgart, in 1979, and received the Ph.D. degree from University of Stuttgart in 1983.

In 1984 he became a member of the Faculty of Engineering, the University of Tokyo, and since 1993, he has been a professor of precision engineering. He is conducting also a research group in National Institute of Materials Science (NIMS) in Tsukuba as a director, and also he is a member of the Science Council of Japan. His researches focus on micro-systems integration and packag-ing, and development of interconnect technology, especially the room temperature bonding technique for various applications.

Masaaki IchikiTeam Leader of Researcher Center for Ubiq-uitous MEMS and Micro Engineering, National Institute of Advanced Industrial Sci-ence and Technology (AIST), and researcher of JST Presto of “Nano Systems and Emer-gent Functions.” He received BS, MS and PhD degree from Waseda Univ. He has been

Researcher at AIST from 1997 to 2008, and from 2012 to present. He was Associate Professor of the University of Tokyo from 2008-2012. His major research field is the preparation of ferroelectric materials and its application to MEMS and packaging technology.

Toshihiro ItohDepty Director of Reseach Researcher Cen-ter for Ubiquitos MEMS and Micro Engi-neering National Institute of Advanced Industrial Science and Technology (AIST). He received PhD from the Department of Precision Engineering, the University of Tokyo at 1994. He was Research Associate,

Lecturer and Associate Professor of the University of Tokyo. He joined the AIST from 2007 and became the present position from 2012. He research is the development of the wireless sensor sys-tem and the large-area MEMS device.