Fa Structure Modelling
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Transcript of Fa Structure Modelling
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VHDL Code for Full Adder using Structural Modellinglibrary IEEE;
use IEEE.std_logic_1164.all;
entity bejoy_fa is
port(In1,In2,c_in : in std_logic;
sum, c_out : out std_logic);
end bejoy_fa;
architecture arc of bejoy_fa is
component half_adder
port(a,b : in std_logic;
sum, carry : out std_logic);
end component;
component or_2
port(a,b : in std_logic;
c : out std_logic);
end component;
signal s1, s2, s3 : std_logic;
begin
![Page 2: Fa Structure Modelling](https://reader035.fdocuments.net/reader035/viewer/2022071920/55cf991a550346d0339b95d0/html5/thumbnails/2.jpg)
H1: half_adder port map(a=>In1, b=>In2, sum=>s1, carry=>s3);
H2: half_adder port map(a=>s1, b=>c_in, sum=>sum, carry=>s2);
O1: or_2 port map(a=> s2, b=>s3, c=>c_out);
end arc;
entity half_adder is
port (a,b : in bit ;
sum,carry : out bit);
end half_adder;
architecture arc of half_adder is
begin
sum<= a xor b;
carry <= a and b;
end arc;
entity or_2 is
![Page 3: Fa Structure Modelling](https://reader035.fdocuments.net/reader035/viewer/2022071920/55cf991a550346d0339b95d0/html5/thumbnails/3.jpg)
port (a,b : in bit ;
c : out bit);
end or_2;
architecture arc of or_2 is
begin
c<= a or b;
end arc;