1Formal Verification Based Automated Approaches To SOC

DFT Logic Verification

Subir K. RoyRubin A. Parekhji

Texas Instruments Bangalore, India

(Presenter : Sarveswara Tammali)

DAC User Track 2009 Poster Session

2MotivationAutomate integration verifications of DFT Logic and IPs towards

Cycle time reduction in verification by minimizing usage of simulation based SOC level verification requirements. (Minimum 2X)

Si quality improvement by elimination of all connectivity logic related bugs.

Deployment through common infrastructure

3Simulation vis--vis FV

Limitations of Simulation - Limited input test vectors/ Manual test bench creation / Only end-to-end bugs found Larger debug time/ Larger regression runtimes

Advantages of formal verification - No test bench generation/ Comprehensive verification and coverage/ Faster verification/ Properties are generic/ Pin-points source of bug

Issues in FV Intrinsic capacity limitations (1000 flops) => Rules out use of embedded memory/memory models/IPs => Needs partitioning and abstraction.

4SOC DFT Logic Structure &Different types of Integration

SOC DFT Logic Structure & Behavior

Canonical & Regular Largely Independent of SOC

Reasonably generic nature of its interconnection to rest of logic in SOC

Different Types of Integration

Static integration

Example : Pure connectivity

Dynamic integration

Temporal (Example : Pipeline registers in DPs)

Functional (Example : Switching between functional and test modes)

5Case Study in Pure Connectivity Verification

Bug Classes Total/%

Specification 18/10%

Pure Connectivity

150/83.33%

Non-IP SOC logic

12/6.66%

SOC design complexity

Total IPs in the design = 42

Total Instances at top level = 117

Total integration bugs found by simulation = 180

Total effort = 6 months/8 persons (1136 man days)

Total PSL assertions for CBA sub-system = 6480

Total FV runtime = 180 minutes (3-4 secs/property)

Results

FV performance boost on the CBASub-system - 33XFV performance boost on the wholeSOC (extrapolated) - 38X

6Advantages of using FV for SoC Level Connectivity checks

Modeling and property generation are simple

Allows concurrent efforts on RTL flow and Connectivity verification flow

Can be used very early in the design cycle to extract maximum benefit, as it does not require RTL to be complete or functionally mature.

Can be carried out selectively on sub-systems with high bug risks due to variability in choosing IP configurations (Eg. Auto-generated parameterized/configurable IPs)

7FV of Memory Data Path (Dynamic Integration - Temporal)

8Flow of Data between PBIST ControllerAnd Embedded Memories

Command Line Arg

Generated Properties &

FV env

Input_Info.xlsscript

Automated Flow

9Icepick Cntr

Icepick Top DFT

Jtag Reg Mod

Decode logic

FSM

CVL TM

TDI

TCKTMS

RST

TM Reg

nRESET

FV of Testmode Entry Sequence (Dynamic Integration - Functional)

SOC Top Level Verification Approach Through Partitioning

10

SOC MDP + Test Mode Entry Sequence ResultsIPs/

SubsystemsProperties Pass Fail

1 148 144 4

2 68 67 1

3 1344 1312 32

4 158 155 3

5 1363 1324 37

6 48 46 2

7 670 660 10

8 172 168 4

9 38 5 33

10 (Hard IP)* 29 21 8

11 (Hard IP)* 29 4 25

12 (Hard IP)** NA NA NA

13 (Hard IP)** NA NA NA

14 (Hard IP)** NA NA NA

Total 4067 3906 161

* - Only Pure Connectivity Checks** - Connectivity information unavailable during first iteration of DFT FV

Block Level /

Connectivity

Verification

Proper-ties

Average

Flip-Flops

CPU Time

[mins.]

ICEPick IP 61 170 38

JTAG Regs 10 90 20

Connectivity 14 2 3

In one SoC MDP, due to awrongly placed inverter, write-enable pin of a memory was notbeing de-asserted properly caught by de-assertion property

twenMux Reg

RGS

Should be here

CSR

WZ0

1 1

Mux RegWrongly Placed

Inverter

11

Automated DFT FV Regression Flows

IFVIFV IFVIFV IFVIFV IFVIFV

IndividualIndividualRunRun

ReportsReports

ConsolidatedConsolidatedRegressionRegression

ReportReport

FVFVRegressionRegression

RunsRuns

Types of DFT checks to be performedTypes of DFT checks to be performed(Connectivity/MDP/Safe Val/TME/TAM etc.)(Connectivity/MDP/Safe Val/TME/TAM etc.)

DFT logics to be verifiedDFT logics to be verified

12

Summary For standardized SOC connectivity and DFT

logic architecture formal verification can be easily automated and extremely efficient Enormous Reduction in Verification Cycle Time + High Quality Verification.

Person month reduction to complete DFT FV after deployment of automation :

For Large Sized SOCs --- Factor of 4

Only 1 resource needed.

[Acknowledgement : Thanks to Bijitendra Mittra, Amit Roy, SupriyaBhattacharjee, Deepanjan Roy and Lopamudra Sen from Interra IndiaPrivate Limited, Bangalore]