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  • External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

    Updated for Intel® Quartus® Prime Design Suite: 19.3

    IP Version: 19.1.0

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    UG-20116 | 2019.09.30 Latest document on the web: PDF | HTML

    https://www.intel.com/content/www/us/en/programmable/bin/rssdoc?name=mls1506089797502 mailto:FPGAtechdocfeedback@intel.com?subject=Feedback%20on%20External%20Memory%20Interfaces%20Intel%20Cyclone%2010%20GX%20FPGA%20IP%20User%20Guide%20(UG-20116%202019.09.30)&body=We%20appreciate%20your%20feedback.%20In%20your%20comments,%20also%20specify%20the%20page%20number%20or%20paragraph.%20Thank%20you. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20116.pdf https://www.intel.com/content/www/us/en/programmable/documentation/mls1506089797502.html

  • Contents

    1. Release Information....................................................................................................... 7

    2. External Memory Interfaces Intel Cyclone® 10 GX FPGA IP Introduction........................8 2.1. Intel Cyclone 10 GX EMIF IP Design Flow.................................................................. 8 2.2. Intel Cyclone 10 GX EMIF IP Design Checklist.......................................................... 10

    3. Intel Cyclone 10 GX EMIF IP Product Architecture........................................................11 3.1. EMIF Architecture: Introduction............................................................................ 11

    3.1.1. I/O Subsystem........................................................................................ 12 3.1.2. I/O Column.............................................................................................12 3.1.3. I/O AUX..................................................................................................13 3.1.4. I/O Bank.................................................................................................13 3.1.5. I/O Lane.................................................................................................16 3.1.6. Input DQS Clock Tree............................................................................... 19 3.1.7. PHY Clock Tree........................................................................................ 20 3.1.8. PLL Reference Clock Networks................................................................... 20 3.1.9. Clock Phase Alignment..............................................................................21

    3.2. Intel Cyclone 10 GX EMIF Sequencer...................................................................... 22 3.2.1. DQS Tracking.......................................................................................... 23

    3.3. Intel Cyclone 10 GX EMIF Calibration......................................................................23 3.3.1. Calibration Stages ...................................................................................24 3.3.2. Calibration Stages Descriptions..................................................................24 3.3.3. Calibration Algorithms.............................................................................. 25 3.3.4. Calibration Flowchart................................................................................26

    3.4. Intel Cyclone 10 GX EMIF Controller....................................................................... 27 3.4.1. Hard Memory Controller............................................................................27 3.4.2. Hard Memory Controller Rate Conversion Feature.........................................31

    3.5. Hardware Resource Sharing Among Multiple EMIFs...................................................32 3.5.1. I/O Aux Sharing.......................................................................................32 3.5.2. I/O Bank Sharing.....................................................................................32 3.5.3. PLL Reference Clock Sharing......................................................................33 3.5.4. Core Clock Network Sharing...................................................................... 34

    3.6. Intel Cyclone 10 GX EMIF Ping Pong PHY.................................................................35 3.6.1. Ping Pong PHY Feature Description............................................................. 35 3.6.2. Ping Pong PHY Architecture....................................................................... 36 3.6.3. Ping Pong PHY Limitations......................................................................... 38 3.6.4. Ping Pong PHY Calibration......................................................................... 39 3.6.5. Using the Ping Pong PHY........................................................................... 40 3.6.6. Ping Pong PHY Simulation Example Design.................................................. 40

    4. Intel Cyclone 10 GX EMIF IP End-User Signals..............................................................41 4.1. Interface and Signal Descriptions........................................................................... 41

    4.1.1. Intel Cyclone 10 GX EMIF IP Interfaces for DDR3......................................... 41 4.1.2. Intel Cyclone 10 GX EMIF IP Interfaces for LPDDR3...................................... 52

    4.2. AFI Signals......................................................................................................... 60 4.2.1. AFI Clock and Reset Signals...................................................................... 60 4.2.2. AFI Address and Command Signals............................................................ 61 4.2.3. AFI Write Data Signals..............................................................................62

    Contents

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  • 4.2.4. AFI Read Data Signals.............................................................................. 62 4.2.5. AFI Calibration Status Signals....................................................................63 4.2.6. AFI Shadow Register Management Signals...................................................63

    4.3. AFI 4.0 Timing Diagrams...................................................................................... 64 4.3.1. AFI Address and Command Timing Diagrams............................................... 65 4.3.2. AFI Write Sequence Timing Diagrams......................................................... 67 4.3.3. AFI Read Sequence Timing Diagrams..........................................................73 4.3.4. AFI Calibration Status Timing Diagram........................................................75

    4.4. Intel Cyclone 10 GX Memory Mapped Register (MMR) Tables.....................................76 4.4.1. ctrlcfg0...................................................................................................77 4.4.2. ctrlcfg1...................................................................................................77 4.4.3. dramtiming0........................................................................................... 79 4.4.4. sbcfg1....................................................................................................79 4.4.5. caltiming0...............................................................................................79 4.4.6. caltiming1...............................................................................................79 4.4.7. caltiming2...............................................................................................80 4.4.8. caltiming3...............................................................................................80 4.4.9. caltiming4...............................................................................................81 4.4.10. caltiming9.............................................................................................81 4.4.11. dramaddrw............................................................................................81 4.4.12. sideband0............................................................................................. 81 4.4.13. sideband1............................................................................................. 82 4.4.14. sideband2............................................................................................. 82 4.4.15. sideband3............................................................................................. 82 4.4.16. sideband4............................................................................................. 82 4.4.17. sideband5............................................................................................. 83 4.4.18. sideband6............................................................................................. 83 4.4.19. sideband7............................................................................................. 83 4.4.20. sideband8............................................................................................. 84 4.4.21. sideband9............................................................................................. 84 4.4.22. sideband10........................................................................................... 84 4.4.23. sideband11........................................................................................... 84 4.4.24. side