External Memory Interface (EMIF) - Florida Institute of …my.fit.edu/~vkepuska/ece3552/TI...

External Memory Interface (EMIF)

Introduction Provides an introduction to the EMIF, the memory types it supports, and programming its configuration registers.

Learning Objectives Outline

Memory MapsMemory TypesProgramming the EMIFAdditional Memory Topics

Technical TrainingOrganization

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C6000 Integration Workshop - External Memory Interface (EMIF) 13 - 1

Memory Maps

Chapter Topics External Memory Interface (EMIF).......................................................................................................13-1

Memory Maps ........................................................................................................................................13-3 Sidebar: Memory Addressing on C6x ..............................................................................................13-4

Memory Types........................................................................................................................................13-5 Overview ...........................................................................................................................................13-5 Using SDRAM ..................................................................................................................................13-6 Using Asychronous Memory...........................................................................................................13-10

Sidebar: Optional Async Timing .................................................................................................13-14 Programming the EMIF.......................................................................................................................13-16

Using the EMIF with CSL...............................................................................................................13-16 Programming the EMIF with Assembly..........................................................................................13-17 Programming the EMIF with GEL..................................................................................................13-18

Additional Memory Topics...................................................................................................................13-19 EMIF – CPU’s Access Performance ...............................................................................................13-19 Fanout..............................................................................................................................................13-21 Shared Memory ...............................................................................................................................13-22 SBSRAM.........................................................................................................................................13-24 SDRAM Optimization.....................................................................................................................13-25 EMIF ‘C6x Family Comparison......................................................................................................13-25 Sidebar: C6x01 Memory Map .........................................................................................................13-26

13 - 2 C6000 Integration Workshop - External Memory Interface (EMIF)

Memory Maps

Memory Maps

Memory Map Review

8000_0000

128MB CE3

9000_0000

B000_0000

128MB CE2

128MB CE1

128MB CE0

A000_0000

128 MB8000_0000CE0

A000_0000CE2

C6000CPU

L2 SRAM

EMIF

64KB L2 SRAM

B000_0000CE3

9000_0000CE1

128 MB

128 MB 128 MB

0000_0000

A Memory Map is atable representationof memory…


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FFFF_FFFF

0000_0000

256KB InternalProgram / Data

Peripheral Regs0180_0000

128MB External

128MB External

8000_0000

9000_0000

A000_0000

B000_0000

128MB External

128MB External

TMS320C6713

Available viaDaughter Card

Connector

‘C6713 DSK16MB SDRAM

256K byte FLASH

CPLD

C6713 DSK Memory Map

CPLD:LED’sDIP SwitchesDSK statusDSK rev#Daughter Card

9008_0000


Memory Maps

Sidebar: Memory Addressing on C6x

CE Pins Select Memory Space

FFFF_FFFF

0000_0000

C6000CPU

L2InternalMemory

EMIF

64KB Internal(Program or Data)

On-chip Periph

128MB External

128MB External

128MB External

128MB External

CE0

CE1

CE2

CE3


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‘C6x Addressing

CPU

DMA orEDMA

EMIF

32

32

20A2:A21

With only 20 address pins, only SDRAM can access full 128M Bytes per CE spaceNot all CPU/DMA address lines are used in C6x01 example above

EA2-21

A0:A1

BE0BE1BE2BE3

A24:A25CE0CE1CE2CE3


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Memory Types

Memory Types

Overview

SDRAM - Synchronous (clocked) DRAMSDRAM provides lowest cost / bit cheapOperates up to 100 MHz fastBuilt-in SDRAM controller makes interfacing simple easyOnly SDRAM can reach full address space big

Memory Types Overview16M ByteSDRAMCPU

EDMA

EMIF

ASYNC - Traditional (unclocked) memoriesWide array of memories (Flash, SRAM, Regs, FPGA/ASIC)Can use buffer/drivers, address decoding, etc. flexibleAllows multiprocessor access share

Flash (ASYNC)

I/O Port (ASYNC)

Note: SBSRAM is covered later in the chapter - it's not implemented on the DSK

Selecting Memory Type

Global Control

SDRAM Refresh PrdSDRAM Control

180_001C180_0018

180_0000

180_0020

MTYPE7 4CEx Control Register

RW, +0010

0000b = 8-bit-wide Async0001b = 16-bit-wide Async0010b = 32-bit-wide Async0011b = 32-bit-wide SDRAM0100b = 32-bit-wide SBSRAM1000b = 8-bit-wide SDRAM1001b = 16-bit-wide SDRAM1010b = 8-bit-wide SBSRAM1011b = 16-bit-wide SBSRAM

SDRAM Extension

CE1 Control

CE3 Control

CE0 Control

CE2 Control180_0004

180_0014

180_0008

180_0010


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Memory Types

Using SDRAM

1. Select SDRAM and verify it meets system performance timing

DM642 SDRAM RecommendationsDue to datasheet requirements, the following is recommended:

1 bank (max of 2 chips) of SDRAM connected to EMIFUp to 1 bank of buffers connected to EMIF for async memoriesTrace lengths between 1 and 3 inches183MHz SDRAM for 133MHz EMIF operation143MHz SDRAM for 100MHz EMIF operation

Therefore:To run the EMIF at 133MHz and meet the above requirements, the largest memory size available today is 16M Bytes using two 2Mx32 SDRAMs.

Alternatively:The largest memory size achievable using x32 devices is 32MBytesusing 4Mx32 SDRAMs. However, these devices are only available at 166Mhz.Another option is to use x16 devices, but you have to use four of these since the EMIF is 64 bits wide. Also, the fastest speed grade is 167MHz.

* These guidelines are for DM642 in June 2003. Other C6000 devices require similar consideration.Technical TrainingOrganization

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SDRAM Design ConsiderationsUse Daisy chaining or minimum stub length routing on EMIF signalsKeep trace lengths as close as possible to the same length‘Swizzle’ signals such that they are flow through to avoid signal criss-crossing as much as possible. For example, on resistor packs or SDRAM data pins on a ‘byte’ boundarySerial termination resistors should be inserted into all EMIF output signal lines to maintain signal integrityUse controlled impedance of 50-60 ohms on layout/pwb fabricationGround layer is a must, and can be duplicated to help with controlled impedance any time there is an odd number of layersPerform timing analysis to verify A/C timings are met using I/O Buffer Information Specification (IBIS)

In fact, using IBIS modeling you may find you can improve upon the suggestions provided on the previous slideRefer to application note: Using IBIS Models for Timing Analysis

http://www-s.ti.com/sc/psheets/spra839a/spra839a.pdf


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Memory Types

What is IBIS?

General IBIS Information:http://www.eigroup.org/ibis/ibis.htm

http://www.eigroup.org/ibis/ibis.htmTechnical TrainingOrganization

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What are these models based on?


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Model Characteristics


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Memory Types

2. Specify SDRAM Parameters

SDRAM Control Register

Calculate the number of cycles for each of the three timing parameters using the SDRAM datasheet. The following formula may help:

TR__ = (tRCD / tECLKOUT) – 1

There’s only one SDRAM Control Register, therefore all SDRAM spaces must have the same configuration

TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC15 12 0

reserved

rsv


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TRCD = 30ns / 10ns - 1 = 2

TRP = 30ns / 10ns - 1 = 2

TRC = 90ns / 10ns - 1 = 8

From SDRAM

Datasheet

EMIF Clockspeed

TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC15 12 0

reserved

rsv


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Memory Types


Oh, here’s a couple other small details:

TRPTRCD31 30 29 28 27 26 25 24 23 20 19 16

TRC15 12 0

SDRSZ INIT

reserved

RFENSDCSZSDBSZ

‘C6x does Refresh(REFEN)0 = No1 = Yes

‘C6x does Refresh(REFEN)0 = No1 = Yes

rsv

SDRAM Column Size(SDCSZ)

00 = 9 pins (512)01 = 8 pins (256)

10 = 10 pins (1024)11 = reserved

SDRAM Column Size(SDCSZ)

00 = 9 pins (512)01 = 8 pins (256)

10 = 10 pins (1024)11 = reserved

SDRAM Row Size(SDRSZ)

00 = 11 pins (2048)01 = 12 pins (4096)10 = 13 pins (8192)

11 = reserved

SDRAM Row Size(SDRSZ)

00 = 11 pins (2048)01 = 12 pins (4096)10 = 13 pins (8192)

11 = reserved

SDRAMBank Size(SDBSZ)

0 = 1 pin (2)1 = 2 pins (4)

SDRAMBank Size(SDBSZ)

0 = 1 pin (2)1 = 2 pins (4)

Initialization(INIT)

0 = No effect1 = Initialize

Initialization(INIT)

0 = No effect1 = Initialize

3. Calculate Refresh Timing

SDRAM Refresh Timing Register

= 1562 (0x61A)

From the SDRAM data sheet: Refresh Rate = “4K Auto Refresh each 64ms”

= 64 ms / 4096

PeriodCounterreserved31 26 25 24 23 12 11 0

R, +0 RW, +00 R, +010111011100 RW, +010111011100

XRFR

Assuming 100MHz EMIF Clockspeed

= (64ms/4096) / 10ns

Period = tRefresh Rate / tECLK


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Memory Types

Using Asychronous Memory • Generic Read Timing • Async Example - Flash • Flash Read Timing • Flash Write Procedure

MemoryA

D

ADADAD

Access 1

Access 2

Access 3

Asynchronous Memory - What is it?Traditional Memory Interface

Doesn’t require clockNon Pipelined AccessesEx: SRAM, EPROM, Regs, Ext. Periph

External buffers can be used for:Shared memoryIncreased fanoutIsolation


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Memory Types

Async Read Timing

Setup = 1 Strobe = 2 Hold = 1

Async Read Timing

ECLKOUT

AOE

ARE

C6x11 range: 1 - 15 1 - 63 0 - 7

Read HoldMTYPERead StrobeRead Setup

CEx Register

ED

EA, CE, BE

19 16 13 8 7 4 2 0


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Memory Types

Async Flash Memory

Flash Read Timing

9008 0000h


Connector

C6711 DSK16MB SDRAM

128KB FLASH

4 byte I/O PortLED’sSwitchesDSK statusDSK rev#

9000 0000h

DSK has 128K FlashProvides re-programmable,non-volatile memoryPre-program with code, init values and boot-strap programStores non-volatile, run-time data

Looking more closely at the timing …Technical Training

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Timing & Table


Connector

C6711 DSK16MB SDRAM

128KB FLASH

4 byte I/O Port

CE1


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Memory Types

Flash Read Timing

Setup = ______Strobe = ______Hold = ______

Let's figure out the timing for the DSK's async Flash memory …

150ns

100ns 150ns

0ns

50ns

Use EMIF’sARE pin


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Writing to Flash

Writing to DSK's FlashFlash is a non-volatile memory, i.e. it can't normally be written to

To change it's content, you must "unlock" it with a special procedure:

PC based tools available for Flash programming

BSL functions allow runtime writing to Flash

1. Write 0xAA to 0x55552. Write 0x55 to 0x2AAA3. Write 0xA0 to 0x55554. Write new data to 128 byte sector

(data must be written in 128 byte chunks)

Flash requires 20ms to complete internal write cycle. Data I/O7 can be polled to determine when write cycle is complete.


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Sidebar: Optional Async Timing

Sidebar: Optional Async Timing Async Read - Maximum Speed

Setup = 1 Strobe=1 Hold = 0

ECLKOUT

EA, CE, BE

AOE

ARE

ED


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Async Write Timing

Setup Strobe Hold

ECLKOUT

AWE

EA, CE, BE

ED

1 - 15 1 - 63 0 - 3

31 28 27 22 21 20

Write HoldWrite StrobeWrite Setup


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Sidebar: Optional Async Timing

Minimum Turn-Around Time

First R/W in a series requires an extra “setup” cycle

Read Read Bus Turn-Around Write

CE

EA, BE

AOE

ARE

AWE

ED

CE on last access is held active for a minimum of 7 cyclesBus turn-around time (R→W or W→R) is approx 9 cycles(please refer to data sheet for specifics for each individual processor)


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Async Memory - Summary

CyclesSetup = 1* - 15 Read Hold = 0 - 7Strobe = 1* - 63 Write Hold = 0 - 3

CyclesSetup = 1* - 15 Read Hold = 0 - 7Strobe = 1* - 63 Write Hold = 0 - 3

* 0 1 and 1 1

Read SetupWriteHoldWrite StrobeWrite Setup

31 28 27 22 21 19 16

RW, +1111 RW, +111111 RW, +11 RW, +1111

ReadHoldrsvMTYPETA Read Strobe

15 14 13 8 7 4 3 2 0

RW, + 111111 RW, +0010 RW, +011

0000b = 8-bit-wide Async0001b = 16-bit-wide Async0010b = 32-bit-wide Async0011b = 32-bit-wide SDRAM0100b = 32-bit-wide SBSRAM

1000b = 8-bit-wide SDRAM1001b = 16-bit-wide SDRAM1010b = 8-bit-wide SBSRAM1011b = 16-bit-wide SBSRAM


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Programming the EMIF


Using the EMIF with CSL

Program EMIF with CSLfar const EMIFA_Config C6416DskEmifConfigA = {EMIF_GBLCTL_RMK( // 0x00012070

EMIF_GBLCTL_EK2RATE_FULLCLK, // bits 18-19 = 00EMIF_GBLCTL_EK2HZ_CLK, // bit 17 = 0EMIF_GBLCTL_EK2EN_ENABLE, // bit 16 = 1EMIF_GBLCTL_BRMODE_MRSTATUS, // bit 13 = 1EMIF_GBLCTL_BUSREQ_LOW, // bit 11 = 0...EMIF_GBLCTL_CLK6EN_DISABLE, // bit 3 = 0

);0x00000000, /* cectl0 **/...0x00000000 /* cesec3 */

};

void emifInit(){EMIFA_config(&C6416DskEmifConfigA);

}

Program EMIF similar to other peripherals.Since EMIF is not a multi-channel periperhal, no _open function is required.


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Programming the EMIF with Assembly

Program EMIF with Assembly (1)EMIF .equ 0x01800000GBLCTL .equ 0x________CE0CTL .equ 0x________CE1CTL .equ 0x________CE2CTL .equ 0x________CE3CTL .equ 0x________SDCTL .equ 0x________SDTIM .equ 0x________SDOPT .equ 0x________

cEMIF: mvkl EMIF, A0mvkh EMIF, A0mvkl GBLCTL, A1mvkh GBLCTL, A1stw A1, *+A0[0]mvkl CE0CTL, A1mvkh CE0CTL, A1stw A1, *+A0[2]

…mvkh SDOPT, A1stw A1, *+A0[8]

Global Control

SDRAM Ref PrdSDRAM Control

180_001C180_0018

180_0000

180_0020 SDRAM Extension

CE1 Control

CE3 Control

CE0 Control

CE2 Control180_0004

180_0014

180_0008

180_0010

Add the desired register values to the blank spaces and code will program EMIFAssembly code will work for all devices, if you …

Better yet, …Technical Training

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Program EMIF with Assembly (2)/* Include Header File #include “csl_emif.h”

/* Config Structures */far const EMIF_Config myEM

0x00003078, /* Global Control Reg. (GBLCTL) */0x00000020, /* CE0 Space Control Reg. (CE0CTL)*/0xFFFF3F23, /* CE1 Space Control Reg. (CE1CTL)*/0x00000030, /* CE2 Space Control Reg. (CE2CTL)*/0xFFFF3F23, /* CE3 Space Control Reg. (CE3CTL)*/0x0388F000, /* SDRAM Control Reg.(SDCTL) */0x00000040 /* SDRAM Timing Reg.(SDTIM) */0x00F02AE0 /* SDR

};

.global _myEMIF

EMIF .equ 0x01800000

cEMIF: mvkl EMIF, A0mvkh EMIF, A0mvkl _myEMIF, A1mvkh _myEMIF, A1ldw *A1, A2stw A2, *A0ldw *++A1[1], A2stw A2, *+A0[2]...ldw *++A1[1], A2stw A2, *+A0[8]

Create EMIF_Config structure and use assembly to write configuration values to peripheralNote: must use “far const” declaration for this method to work


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Programming the EMIF with GEL

init_emif(){ // First we define the EMIF addresses#define EMIF_GCTL 0x01800000#define EMIF_CE1 0x01800004#define EMIF_CE0 0x01800008#define EMIF_CE2 0x01800010#define EMIF_CE3 0x01800014#define EMIF_SDRAMCTL 0x01800018#define EMIF_SDRAMTIMING 0x0180001C#define EMIF_SDRAMEXT 0x01800020

// Now we set the values*(int *)EMIF_GCTL = 0x00003300; // EMIF global*(int *)EMIF_CE0 = 0x00000030; // CE0-SDRAM*(int *)EMIF_CE2 = 0xFFFFFF23; // CE2-32bit async on daughtercard*(int *)EMIF_CE3 = 0xFFFFFF23; // CE3-32bit async on daughtercard*(int *)EMIF_SDRAMCTL = 0x07227000; // SDRAM control register(100 MHz)*(int *)EMIF_SDRAMTIMING = 0x0000061A; // SDRAM Timing register*(int *)EMIF_SDRAMEXT = 0x00054529; // SDRAM Extension register}

init_emif(){ // First we define the EMIF addresses#define EMIF_GCTL 0x01800000#define EMIF_CE1 0x01800004#define EMIF_CE0 0x01800008#define EMIF_CE2 0x01800010#define EMIF_CE3 0x01800014#define EMIF_SDRAMCTL 0x01800018#define EMIF_SDRAMTIMING 0x0180001C#define EMIF_SDRAMEXT 0x01800020

// Now we set the values*(int *)EMIF_GCTL = 0x00003300; // EMIF global*(int *)EMIF_CE0 = 0x00000030; // CE0-SDRAM*(int *)EMIF_CE2 = 0xFFFFFF23; // CE2-32bit async on daughtercard*(int *)EMIF_CE3 = 0xFFFFFF23; // CE3-32bit async on daughtercard*(int *)EMIF_SDRAMCTL = 0x07227000; // SDRAM control register(100 MHz)*(int *)EMIF_SDRAMTIMING = 0x0000061A; // SDRAM Timing register*(int *)EMIF_SDRAMEXT = 0x00054529; // SDRAM Extension register}

Program EMIF with GEL

When does this GEL script get executed?

/** The StartUp() function is called every time you start Code Composer.* You can customize this function to perform desired initialization.* This function may be commented out if no initialization is needed.*/

StartUp() {setup_memory_map(); GEL_Reset(); init_emif();

}

/** The StartUp() function is called every time you start Code Composer.* You can customize this function to perform desired initialization.* This function may be commented out if no initialization is needed.*/

StartUp() {setup_memory_map(); GEL_Reset(); init_emif();

}

OpenDSK6211_6711.gel

GEL Startup


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Additional Memory Topics

Additional Memory Topics Additional Memory Topics

Performance ConsiderationsFanout / SystemShared Memory (HOLD, HOLDA)Overview of SBSRAMSDRAM OptimizationC6000 Family EMIF Comparison


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EMIF – CPU’s Access Performance

DMC

1

2

mem

‘C6201

PC

3

4regs

CPU Load from Internal Memory

Even though an internal memory access requires a four cycle access time, as with most modern RISC processors, the C6000’s pipelined architecture provides means to overcome this delay



CPU Load from External MemoryDMC‘C6201

PC 1

1617

18mem

EMIF

2

SBSRAM

8

15 9

4

13

5

12

6

11

7

10

3

14

Even providing a zero wait-state off-chip memory, the CPU’s access time for external memory will be upwards of 18 cycles.

Total affect is a 14 cycle delay. (18 cycles less four afforded by C6000’s hardware pipelining.)

C6201 details are shown here. Similar issues affect all C6000 devices (in fact, all high perf μP), but they are manifested differently. For example, the cache in more recent devices mitigate the affect of these delays by keeping often used code and data in faster on-chip memory.

Even providing a zero wait-state off-chip memory, the CPU’s access time for external memory will be upwards of 18 cycles.

Total affect is a 14 cycle delay. (18 cycles less four afforded by C6000’s hardware pipelining.)

C6201 details are shown here. Similar issues affect all C6000 devices (in fact, all high perf μP), but they are manifested differently. For example, the cache in more recent devices mitigate the affect of these delays by keeping often used code and data in faster on-chip memory.

Besides cache, what is a better way to increase EMIF throughput?Technical Training

Organization

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Load from External MemoryDMC‘C6x

PC 1

1617

18mem

EMIF

2

SBSRAM

8

15 9

4

13

5

12

6

11

7

10

3

14

Unlike the CPU, the EDMA (and DMA) can pipeline-up access through the EMIF delays to achieve single-cycle throughput from zero wait-state external memories.

While the first access may take 14 cycles, subsequent accesses can get down to a single cycle.

Unlike the CPU, the EDMA (and DMA) can pipeline-up access through the EMIF delays to achieve single-cycle throughput from zero wait-state external memories.

While the first access may take 14 cycles, subsequent accesses can get down to a single cycle.

EDMA


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Fanout

‘C6201 Bus Fanout

H/W MaxType Top Speed* Wait Size/Fan Glueless

ASYNC 100 MHz Yes 16 M/∞ Yes/No

SBSRAM 200 MHz No 3 MB Yes

SDRAM 100 MHz No 48 MB Yes

Bus pin drivers rated for 30pf loadingDevices are designed for 45pf loads, but testing equipment cannot guarantee it

Most memory devices present 5pf loadsTotal fanout is six memory devicesWhile this slide is slightly old, the issue remains. Again, IBIS modeling is an excellent way to deal with this issue.


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System with All Memory Types

‘C6201 SBSRAM

SDRAM

Flash

SRAM

FPGA

CBT’s and WidebusTransceivers work great

CE0

CE2

CE3


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Shared Memory

Shared Memory

SharedMemory

‘C6201OtherμP

How can 2 μPShare the samememory?

Using 3-state buffers.

One of the μP or another device arbitrates.

Arbiter

What is the drawback of using a buffer here?

Costs you extra:

Speed, Power, Reliability, Money, etc.



Shared Memory

SharedMemory

‘C6201OtherμP

ArbiterHOLD

When ‘C6x drives HOLDA active:

• EMIF signals tri-stated• CPU continues to

execute as long as no off-chip access is needed

HOLDA


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HOLD Status Bits (GBLCTL)

HOLD and HOLDA statusDisable HOLD feature (NOHOLD = 1)

HOLD HOLDA NOHOLD rsv CLK1EN CLK2EN rsvR, +x R, +x RW, +x R, +11 RW, +1 RW, +1 R, +000

9 8 7 6 5 4 3 2 0

BUSREQ ARDYR, +0 RW, +0 RW, +1 RW, +1 R, +0 R, +x

31 15 14 13 12 11 10

rsv rsv± rsv±rsv±

C6711 EMIF GBLCTL


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SBSRAM

Access 1

Access 2

Access 3

A1A2A3/D1A4/D2A5/D3A6/D4

D5D6

Access 4

Asynchronous SynchronousA1D1A2D2A3D3A4D4

Synchronous Burst SRAM (SBSRAM)SBSRAM's pipelines memory accessesWith Burst mode a processor only needs to generate an address every four sequential accesses

Not required by C6000 DSP's as they're fast enough'0x devices don't use (have) this feature'1x devices include the burst feature for power savings (only one address pin needs toggling for four sequential accesses)

A1-- /D1- /D2A5/D3- /D4

D5D6

Burst


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SBSRAM Timing

SSADS

CE

Data is available 2 cycles after address appearsData can be accessed at the rate of 1 per cycle

1 2 3 4 5 6 7 8 9

SSOE

EA/BE EA1/BEx EA2 EA3

ED D1 D2 D3


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SDRAM Optimization

SDRAM Extension Register

TCLRD2RD

09 4 3 1

TRASTWR

6 5

THZP

8 7

RD2DEAC

11 10

RD2WR

14 12

DQM

15

TRRD

R2W

1617

TRRDWR2DEAC

19 1820WR2RDRESERVED

31 21

Most SDRAMs will work without programming this register. This is the case for the C6711 DSK.

Program the SDRAM Extension (SDOPT) register to optimize SDRAM performance.

Please refer to the SDRAM applications note (at the TI website) for further details on programming this register.


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EMIF ‘C6x Family Comparison

EMIF Variations '1x'1x'0xScheme

Sync & Async

Std Sync FIFOFWFT FIFO

ZBT SRAMFlow thru SBSRAM

Pipelined SBSRAM

Sync MemAllowed

in System

CE1 Types

Sync Clocking

Size (MB)Bus Width

Devices

AllBoth

SDRAM and SBSRAM

Either SDRAM or SBSRAM

Both SDRAM & SBSRAM

Sync & AsyncAsync Only

Independent ECLKIN¼ CPU clk1/6 CPU clk

Independent ECLKIN(≤ 100MHz)½ CPU clk

CPU clk½ CPU clk

25610242565125252166416323232

'64x (B)'64x (A)'6712'x11'x02/3/4/5'x01



Sidebar: C6x01 Memory Map

C6201/C6701 Memory Ranges

4M x 8ASYNC or SBSRAM2K x 256 Int’l ProgOn-chip Peripherals

64K x 8 Int’l Data

0000_0000

0100_0000

0140_0000

0200_0000

CE0

CE1

CE2

CE3

0300_0000

(access as 32-bit only)

4M x 8ASYNC or SBSRAM





16M x 8SDRAM

16M x 8SDRAM

16M x 8SDRAM

(read access as 8/16/32-bit, write access as 32-bit only)


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‘C6x01 - MAP 0 vs. MAP 1

CE0 (16M)

CE1 (4M)

P

D

100_0000

000_0000

0

Memory

CE2

CE3

D

040_0000

000_0000

1

Memory

CE2

CE3

140_0000

200_0000

140_0000

200_0000

CE0 (16M)

CE1 (4M)

P


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External Memory Interface (EMIF) - Florida Institute of …my.fit.edu/~vkepuska/ece3552/TI...

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