EE552 Extra Credit Project 1

Extended Burst Mode Design

Orignally Submitted by :Amish Patelamishjpa@usc.edu

Revised by :Sumit Bhargavasumitbha@usc.edu

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Introduction

Illustrate example on Extended Burst Mode Design

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Topics of Discussion Extended Burst Mode Specification Hazard-free Next State Logic

Synthesis 3D Automatic Synthesis Algorithm

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Extended Burst Mode

Specification All input transitions in input burst

should change in assigned time d Circuit settle with in time e Output burst generated

Arrivals of input transitions in input burst may be arbitrary order.

Restrictions:

Maximal Set property

Unique Entry Condition

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Restrictions

Maximal set property --- to prevent non-deterministic state transitions

0

3 1

a-/

2

c-/x-

b+c-/y+

a+c+/x+

If c goes lower first in state 1 arbitrary decision to wait for b+ (go to state 2) or go to state 3

?

?

0

3 1

a-/

2

a+c-/x-

c+/x+

b+c-/y+

Correct Implementation

a, b and c are input variables, x and y are output variables+ represents rising transition- represents falling transition

Illegal implementation Legal implementation

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Restrictions (Contd.) Unique entry condition

1

2 3

a+c+/y- a-/x+y+

0b+c*/x+

c-/x-

abc/xy = 000/01

{ 010/11,011/11 }

{01011}

Not Unique

Correct 1

2 3

a+c+/y- a-c*/x+y+

0b+c*/x+

c-/x-

abcxy=00001

{ 01x11 }

{11000}

Unique

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3D Machine Operation

Mode I : input burst output and sstate bursts simultaneously

Mode II: input burst output burst sstate burst

We will be using this mode in rest of presentation

Mode III : input burst sstate burst output burst

Three protocols / modes of operation

differ in timing of burst of variable change

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* = Directed Don’t Care ?

This symbol is used to model concurrent input /output transitions

Variable is allowed to change before it is required. The input variable is allowed to

change with output and state variable

Eg.

1 2 3a+ b* / x- b+ / x+

Here we allow input variable b to change while going from state 1 to state 2 but state 2 does not care about value of b, but it is in state 3 that we require b to be high. Input variable b is changing all across going from state 1 to state 3 concurrently with output and state variable.

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0 1 2 3abc/xy=000/00

a+b*/x+y+ b+c+/x- c-/x+y- a-b-/x-

ExampleMode II: input burst output burst sstate burstMode III : input burst sstate burst output burst

abc/xy=1*0/11abc/xy = 111/01

abc/xy=110/10

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11 11

11 01 11

11 01 01 11

11 11

Conflict during Table Construction

00 00

bc bc

xy xya = 0 a = 1

000

01

11

10

00

01

11

10

00 01 11 10 00 01 11 10

2

11

10Conflict

Mode II Machine

0 1 2 3abc/xy=000/00

a+b*/x+y+ b+c+/x- c-/x+y- a-b-/x-

abc/xy=1*0/11abc/xy = 111/01 abc/xy=110/10

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11 11

11 01 11

11 01 01 11

11 11

Next-state Table (before layer encoding)

Layer A

10

01 10

01 10

10 10

00 00

00

00 00

1 1

0

bcxy

a = 000 01 11 10

bcxy

a = 100 01 11 10

00

01

11

10

00

01

11

10

00

01

11

10

00

01

11

10

bcxy

a = 000 01 11 10

bcxy

a = 100 01 11 10

2

3

Layer B

Mode III Machine

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Next-state Table (after layer encoding)

011 011

011 101 011

011 101 101 011

011 011

110

101 110

101 110

110 110

000 000

000

000 000

1 1

0

bcxy

a = 000 01 11 10

bcxy

a = 100 01 11 10

00

01

11

10

00

01

11

10

00

01

11

10

00

01

11

10

bcxy

a = 000 01 11 10

bcxy

a = 100 01 11 10

2

3

q = 0

q = 1

Mode II Machine

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00 00 11 11

11 01 11

11 01 01 11

11 11

000 011001 010 110 111 101 100

00

01

11

10

xy

abc

0

2

1

10

Conflict

Conflict during Table Construction

1

Mode III Machine

0 1 2 3abc/xy=000/00

a+b*/x+y+ b+c+/x- c-/x+y- a-b-/x-

abc/xy=1*0/11abc/xy = 111/01

abc/xy=110/10

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11 11

11 11

11 01 01 11

11 11

Layer A

10

01 10

01 10

10 10

00 00

00

00 00

1 1

0

bc a = 000 01 11 10

bcxy

a = 100 01 11 10

00

01

11

10

00

01

11

10

00

01

11

10

00

01

11

10

bc a = 000 01 11 10

bcxy

a = 100 01 11 10

2

3

Layer B

Next-state Table (before layer encoding)

Mode III Machine

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011 011

011 101 011

011 101 101 011

011 011

110

101 110

101 110

110 110

000 000

000

000 000

1 1

0

bcxy

a = 000 01 11 10

bcxy

a = 100 01 11 10

00

01

11

10

00

01

11

10

00

01

11

10

00

01

11

10

bcxy

a = 000 01 11 10

bcxy

a = 100 01 11 10

2

3

q = 0

q = 1

Next-state Table (after layer encoding)

Mode III Machine

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Automatic SynthesisProcedure Next State Assignment Layer Minimization Layer Encoding Combinational logic synthesis

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Another Example

2 0 1<d->c+/y+ <d+>c+/x+

c-/x-c-/y-

If d sampled at rising edge of clock c is 1, x follows the clock and rises to 1,y=0;Otherwise, y follows clock and x=0

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Example Specification

00 01

00

00

00

00

00

00

11 10

01

11

10

00 01

0

0

0

0

0

00

11 10

01

11

10

0

0 0 0

1 1

1

c

a

K-map for xNext State Table

01 10

01 01 00

10 10

dcdcxy xy

2 0 1<d->c+/y+ <d+>c+/x+

c-/x-c-/y-

2

1

0 0

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State Graphd=1d=0

c+

c+

x+

d-d+

c-c-

1

2

3

After x+ and d = 1, machine waits in 1, d may fall freely, leading to 2. If next input is d+ c-, machine may change from 213, giving output as 1-0-1-0 which is a dynamic hazard

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Modified State GraphAfter Adding a New Layer

d=1d=0

c+

c+

p+

d-d+

c-c-

x+Solution:Add new layer and to move to it viaa state burst before enabling i/p tochange if next i/p is unconditional and enables o/p to fall

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Partial Next-State Table

00 01

00

00

00

00

00

11 10

01

11

10

00 00

dcxy 00 01

00

00

00

00

00

11 10

01

11

10

10 10

10 10

dcxy

p=0 p=1

00

1

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Partial K-map

00 01

0

0

0

0

00

11 10

01

11

10

0 0

dc00 01

0

0

0

0

00

11 10

01

11

10

1 1

dc

11

xy xy

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Partial K-map fornext p

00 01

0

0

0

0

00

11 10

01

11

10

0 1

dc00 01

0

0

0

0

00

11 10

01

11

10

1 1

dc

11

xy xy

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References

Synthesis of Asynchronous Controllers for Heterogeneous Systems, Kenneth Yun, Ph.D Dissertation 1994

Automatic Synthesis of Extended Burst Mode Circuits:Part I-II, Kenneth Yun,David Dill

EE552- Fall 2001 Lectures and Discussions

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Policy

"I alone revised this project. I received no help from anyone else. This material is not copied or paraphrased from any other source except where specifically indicated. I grant my permission for this project to be placed on the course homepage during future semesters. I understand that I could receive an F for the course retroactively, even after graduation, if this work is later found to be plagiarized.“

Submitted by Sumit Bhargava