Exploring Sub-20nm FinFET Design withPredictive Technology Models

Saurabh Sinha, Greg Yeric, Vikas Chandra, Brian Cline, Yu Cao*ARM Inc., *Arizona State University, Tempe, AZ

saurabh.sinha@arm.com

ABSTRACTPredictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research. Inthis work, Predictive Technology Model files for sub-20nmmulti-gate transistors have been developed (PTM-MG). Basedon MOSFET scaling theory, the 2011 ITRS roadmap andearly stage silicon data from published results, PTM forFinFET devices are generated for 5 technology nodes corre-sponding to the years 2012-2020 on the ITRS roadmap.

Categories and Subject DescriptorsB.7.1 [Hardware]: Integrated Circuits—Types and DesignStyles, Advanced Technologies; B.8.2 [Hardware]: Perfor-mance and Reliability—Performance Analysis and DesignAids

General TermsTheory

KeywordsFinFET, multi-gate, scaling theory, predictive models, SPICE

1. INTRODUCTIONCMOS scaling has continued up to the 20nm node through

innovative techniques such as incorporating high-k dielectricsin the gate stack, strain engineering, pocket implants andoptimization in materials and device structures. However,further scaling of planar devices is proving to be extremelychallenging due to degrading short channel effects, processvariations and reliability degradation [1].

Multi-gate transistor structures such as FinFETs will bethe technology of choice for extending CMOS scaling beyondthe 20nm node. Improved short channel control through afully depleted fin, reduced random dopant fluctuation, im-proved mobility, lower parasitic junction capacitance andimproved area efficiency are some of the primary advantages

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of FinFETs [2]. However, FinFETs will be markedly differ-ent than planar FETs due to added fringing capacitance,higher access resistance, width-quantization, 3D-factor, andlow-field mobility. Hence, it is crucial to develop accuraterepresentative FinFET compact models to be used as toolsfor design-technology co-optimization, identify key designneeds and explore design solutions upfront.

In the area of predictive modeling, the Berkeley Predic-tive Technology Model (BPTM) [3] and the Arizona StateUniversity (ASU) PTM [4] were developed for planar CMOStechnology nodes up to 20nm based on the BSIM4 model [5].BPTM was developed by empirically extracting model pa-rameters from early stage silicon data while ASU PTM fur-ther improved the methodology by taking into account sig-nificant physical correlations among model parameters. Pre-dictive technology models for bulk planar transistors [4] haveenabled a wide variety of exploratory circuit design researchby the design community [6–8].

In this work, a new generation of Predictive Technol-ogy Model for multi-gate transistors (PTM-MG), specificallyFinFETs for sub-20nm technology nodes, is developed. InSection 2, we discuss the development of these model param-eters using BSIM-CMG (short for Berkeley Short-channelIGFET Common Multi-Gate) model [9], scaling theory ofmulti-gate devices, physical models and ITRS projections.In Section 3 we develop separate models aligning to the evenyears 2012-2020 of the 2011 ITRS roadmap. These yearsapproximately align to technology node names of 20nm,16nm, 14nm, 10nm and 7nm, respectively. Additionally,ring-oscillator delay metrics and comparison with bulk de-vices is presented. The new PTMs for sub-20nm multi-gatetransistors have been developed in two application-specificversions, high performance (HP) and low-standby power(LSTP).

2. PTM FOR MULTI-GATE TRANSISTORS

2.1 BSIM-CMG: Multi-gate transistor modelMulti-gate transistors have been studied previously using

TCAD device simulators, but the speed of TCAD tools lim-its their use in circuit design exploration. BSIM-CMG is asurface-potential-based compact model that can model dif-ferent multi-gate structures (double-gate, tri-gate and gate-all-around FETs) [9] [10]. In addition to incorporating theeffect of the 3D structure and quantum mechanical effects(QME) on device characteristics and short channel effects,the model retains the standard framework of BSIM4 andBSIM-SOI models for real-device effects such as mobility

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Figure 1: Top view and cross-sectional schematic ofa FinFET device.

degradation, velocity saturation, series resistance, parasiticcapacitance, etc., allowing ease in efficient extraction of modelparameters. The model has been verified against TCAD andexperimental data [9] and is a standard feature in commer-cial circuit simulators.

Figure 1 shows the top and cross-sectional view of a Fin-FET. The dimensions are labeled using the correspondingBSIM-CMG model parameters. The parameters used inPTM-MG development are listed in Table 1. The behav-ior of a FinFET device is most sensitive to the primaryparameters, technology specifications and physical param-eters. The secondary parameters are useful to fine-tune a fitto the complete current-voltage characteristics or capturesecondary effects.

2.2 Predicting Model ParametersSince FinFET data for advanced technology nodes (sub-

20nm) is not available from foundries, our BSIM-CMG model

Table 1: PTM-MG ParametersPrimary Parameters

L Gate lengthTFIN Fin thicknessHFIN Fin height

FPITCH Fin pitch

Technology SpecificationsEOT Equivalent oxide thicknessVDD Supply voltageRDS S/D resistance

Secondary ParametersPHIG Gate work function

NBODY Channel dopingCDSC SD-channel couplingEta0 DIBL coefficient

Physical Parametersµ0 Low-field mobility

Vsat Saturation velocity

Figure 2: Flowchart describing PTM-MG modelgeneration for FinFETs.

development begins by fitting to previously published tran-sistor data with gate length 25nm or higher. The completefit of I-V characteristics is discussed in Section 3. This initialstep forms the nominal model and parameters for advancedtechnologies are derived by scaling the PTM-MG parame-ters based on multi-gate MOSFET physics, guidance fromthe ITRS road-map and published data. Figure 2 showsa flowchart describing PTM-MG model development. Thedetails of each step will be described in this subsection.

The primary process parameters are determined by multi-gate MOSFET physics. Traditional bulk devices have reliedon reducing gate oxide thickness and increased channel/halodoping to reduce Short-Channel Effects (SCE) with scaling.However, for fully depleted devices such as FinFETs, theratio of channel length to fin thickness affects SCE adversely.The Voltage Doping Transformation (VDT) model [11] is asimple tool that translates the effects of device geometryscaling into electrical parameters. It is important to studyhow L, TFIN and HFIN influence short channel effects suchas Drain-Induced Barrier Lowering (DIBL) and we use themodified VDT model to get its first-order expression as

DIBL = 0.80εsiεox

EI × VDS (1)

EI stands for Electrostatic Integrity and it represents theway the electric field from the drain influences the channelregion [11]. It is given by

EI =1

2

[1 +

tsi2/4

Lel2

]toxLel

tsi/2

Lel(2)

Modifying Eq.1 to incorporate the scale length (λ) [9] andplotting for different tsi (tsi is equivalent to TFIN in MGdevices), we see that the fin thickness needs to scale withgate length scaling in order to keep short-channel effectsunder control (Figure 3). For double-gate transistors it hasbeen demonstrated that the Lg/TFIN of ∼1.5 is sufficient

284

Figure 3: DIBL vs. FinFET gate length for differentfin thickness (TFIN). Inset graph shows the scalelength (λ) vs. fin thickness (TFIN).

Figure 4: (a) VDD and (b) EOT scaling with tech-nology node. The parameters are scaled accordingto 2011 ITRS predictions.

to achieve subthreshold slope less than 90mV/dec [12]. Thisforms the basis of deriving the transistor dimensions of eachtechnology node as listed in Table 2.

VDD and EOT are scaled according to 2011 ITRS predic-tions as shown in Figure 4, with the various ITRS device-specific parameters included for reference as the various dash-ed lines. The ITRS roadmap predicts the introduction ofmulti-gate transistors in the year 2015 preceded by UTB SOIand planar transistors, but because the leading foundrieshave announced FinFETs beyond 20nm, we have concen-trated our efforts on developing FinFET PTM models. Forthe sake of simplicity we have used the BSIM-CMG mod-els to fit an average of the planar and UTB SOI values inthe years 2012 and 2014. In this way we attempt to bestmatch the likely ITRS device targets as the devices changeto improve electrostatics. The outcome for Figure 4 is a re-laxed overall trend on EOT as compared to any one ITRSdevice type. As shown in later figures, this same philosophyhas been applied to several of the other device-dependentparameters discussed later.

Parasitic series resistance (RDS) is a major source of per-formance degradation in nanoscale transistors. It is en-hanced in multi-gate structures due to increased spread-ing resistance in the narrow fins and difficulty in contactingthe source-drain regions [13]. RDS is highly dependent onthe contact resistivity in addition to fin geometry, length ofspacer and doping gradient from S/D region to the chan-nel [14]. These parameters can be instantiated in BSIM-CMG by invoking the geometry based parasitic series resis-tance model (RGEOMOD=1). Based on ITRS predictionsof silicide contact resistivity from the Front End Process

Figure 5: Parasitic Source-Drain Resistance for eachtechnology node.

Figure 6: Low field mobility and saturation velocitytrend. ITRS trends are for HP FETs.

(FEP) tables and published data [15], Figure 5 shows thetrend of extracted RDS (normalized to Weff ) in these PTM-MG models.

Apart from the gate metal work-function (PHIG), the restof the secondary process parameters do not have a major in-fluence on the device characteristics. A fixed off-current of100nA/µm is used for HP devices, which matches the ITRSHP trends. For LSTP devices, we have targeted a 0.1nA/µmoff-current that is higher than the 0.01nA/µm of the ITRSLSTP devices. The ITRS VTH set point is indicative of ahigher VTH device that would be used in power critical orperformance non-critical applications or paths. Both devicesare important for circuit prediction, with the higher leakagedevice more properly tracking performance trends and thelower leakage device more properly tracking the static powerof non-critical paths/applications. VTH adjustment in Fin-FETs can be a complicated combination of doping, workfunction, and fin dimension that can affect other device per-formance aspects such as mobility, DIBL and subthresholdslope. For the sake of simplicity, we have modeled our differ-ent off-current targets using the gate work-function (PHIG)parameter only. The remainder of this paper will use ourhigher off-current device targets, but a list of ‘DVTSHIFT’values targeting the ITRS off-currents for each technologynode is available on the PTM website [4].

The transistor channel is assumed to be very lowly doped(NBODY= 1017 cm−3) for the 20nm node and is gradu-ally reduced to near intrinsic (NBODY=1016 cm−3) at 7nm.Since FinFETs are fully-depleted and the fin thickness de-termines the short channel effects, channel to S/D coupling(CDSC) and DIBL parameter (Eta0) can be used to modelimperfections in real devices such as tapered fins or irreg-

285

Table 2: PTM-MG SummaryYear 2012 2014 2016 2018 2020

Node (nm) 20 16 14 10 7M1 Pitch (nm) 64 48 38 30 24

Lg (nm) 24 21 18 14 11VDD (V) 0.9 0.85 0.8 0.75 0.7

TFIN (nm) 15 12 10 9 6.5HFIN (nm) 28 26 22 21 18WEFF (nm) 71 64 54 51 42.5

FPITCH (nm) 60 42 32 28 223D factor 1.183 1.52 1.68 1.82 1.93

ular fin thickness along fin height [16] [17]. With theseNBODY assumptions, the gate metal work function is tunedto achieve the off-current target. This results in arbitrarygate work functions that may not be practical to achievein manufacturing. Thus it is possible that some additionalchannel doping may be needed in practical FinFET imple-mentations.

Very low channel doping and volume inversion in narrowfins reduce carrier scattering and lead to improved low fieldcarrier mobility (µ0) and saturation velocity (Vsat) [18]. Ad-ditionally, strain engineering and ballistic transport in sub-20nm channel lengths can further improve carrier mobil-ity [19]. Figure 6 shows this trend, which is crucial to gettingconsistent improvement in drive current through subsequenttechnology nodes.

A summary of the primary process parameters of the PTM-MG models for each technology node are listed in Table2. Metal 1 pitches are also provided as well as the ap-proximate corresponding technology node values. Since theeffective channel width (Weff ) of a FinFET is equal to2×HFIN+TFIN, the total transistor width is quantized. Thefin pitch (FPITCH) determines area efficiency compared to aplanar device. Weff/ FPITCH is referred to as the “3D fac-tor” in Table 2, demonstrating the additional device widthfrom a FinFET as compared to a planar FET due to fin con-struction. The ITRS roadmap does not provide guidanceon the prediction of these device geometries so our valuesare tied to the existing published literature for the earliernodes and then scaled to meet electrostatic requirementsand ION/IOFF values according to ITRS scaling.

Table 3: PTM-MG VerificationData source [16] [20] [19] [21]

Foundry Intel TSMC TSMC IBM

Lg (nm) 40 25 24 25

VDD (V) 1.1 1 1 1

EOT (nm) 1.2 1.1 1.2 1.15

TFIN (nm) 25 15 15 10

HFIN (nm) 29 30 30 30

RDS (Ω − µm) 194 220 244 262

Ion (µA/µm) 1395 1300 1200 1300

PTM-MG Ion 1385 1330 1214 1264

Ioff (nA/µm) 139 41 100 100

PTM-MG Ioff 139 43 100 100

Worst Case Error 0.7% 4.87% 1.16% 2.77%

(a)

(b)

Figure 7: PTM-MG fit with measurement data from[20].

3. PTM-MG EVALUATIONIn order to verify accuracy, the models are fitted with mea-

surement data from industrial publications and parameterssuch as subthreshold slope, DIBL, etc., are plotted with thePTM-MG trends [13,16,19–26].

Based on the limited available information and devicecharacteristics, assumptions regarding the geometry are madeallowing us to generate I-V curves using the PTM-MG pa-rameters to match with published data. Table 3 summarizesthe verification of PTM-MG predictions with published mea-surement results. Tuning the primary parameters, the ION

and IOFF of FinFET devices with various device geometrieshave been matched to published results with high accuracy.Figure 7 shows an example fit of the complete I-V char-acteristics of a FinFET device with Lg=25nm obtained byfine-tuning both primary and secondary parameters.

3.1 PTM-MG Model TrendsThe PTM-MG model cards are developed using ITRS as

a reference for Lg, VDD, EOT, IDSAT and intrinsic delaytrends. Figure 8 shows saturation drive current of PTM-MGmodels normalized per effective width (Weff ) for a constantoff-current (Ioff=0.1nA/µm for LSTP and 100nA/µm forHP). The PTM-MG LSTP devices follow the ITRS LSTPtrend but are shifted to be slightly stronger as discussed inSection 2.

Figure 9(a) and 9(b) show subthreshold slope and DIBLof PTM-MG models across technology generations. Selectedpublication data are plotted for comparison. Short chan-nel effects are determined by the scale length (λ) which

286

Figure 8: Prediction of IDSAT for PTM-MG HP andLSTP devices. Trends from ITRS and selected pub-lications are annotated for comparison.

(a) (b)

Figure 9: Prediction of subthreshold slope andDIBL across technology generations. Selected pub-lication results are included for comparison.

has a strong dependence on fin-width (TFIN). The ratioof L/TFIN is kept greater than 1.5 across technology nodes.However, secondary model parameters CDSC and Eta0 areslightly modified to capture real-device effects such has non-uniform fin thickness, trapezoid or notched fins [16].

3.2 Design BenchmarkingFinFETs possess superior electrostatics compared to bulk

planar transistors. However, the final power/performancemetrics below 20nm will be highly dependent on the totalgate capacitance and not just the intrinsic device electro-statics. The prediction of gate capacitance along with ITRStrends are presented in Figure 10. The parameter-basedintrinsic capacitance is in agreement with the ITRS predic-tions, but the total gate capacitance in the PTM FinFETs ismuch higher due additional fringing capacitance associatedwith the 3D nature of the device. This fringe capacitance issensitive to structural dimensions [27] and the BSIM-CMGmodel has a provision (CGEOMOD=2) to estimate para-sitic fringe capacitance based on device geometry. The totalcapacitance in PTM-MG is estimated using this mode.

Figure 11 shows the scaling of intrinsic delay (τ) calcu-lated from total gate capacitance, supply voltage and satu-ration current. FO4 inverter delay is plotted in Figure 12.Both metrics match the general ITRS trends showing thatFinFETs possess the capability to support the roadmap tar-gets to the 10nm node or below. The ITRS roadmap pro-vides FO4 delay predictions only for HP devices and not forLSTP devices. As was the case for EOT in Figure 4(b), the

Figure 10: Intrinsic and total gate capacitance ofPTM-MG LSTP and HP FinFETs. ITRS predictiontrends are plotted for comparison.

2012 and 2014 PTM-MG devices are made to approximatethe averaged bulk and UTB-SOI trends.

In Figure 13 we compare the FO4 delay as VDD is scaledfor two different technologies: 22nm PTM HP bulk model [4]and 20nm PTM-MG HP model. For fair comparison, thenormalized delay with supply voltage scaling is plotted. Itis seen that the delay of the 22nm PTM planar transistor in-creases by about 9 times while scaling VDD from 1V to 0.5V.However, the FinFET transistor shows much better perfor-mance with VDD scaling owing to superior electrostatics.This trend matches the results demonstrated in [21].

Figure 11: Intrinsic delay (CV/I) of PTM FinFETmodels and ITRS trend across technology nodes.

Figure 12: Fan out of 4 (FO4) delay prediction byPTM-MG HP and LSTP models.

287

Figure 13: Normalized FO4 delay with VDD scalingcomparing 22nm HP planar PTM model to 20nmHP FinFET PTM model.

4. CONCLUSIONS AND FUTURE WORKA new generation of Predictive Technology Model for Multi-

gate (PTM-MG) devices has been developed for early-stagedesign-technology exploration. Model parameter files for 5technology nodes corresponding to the years 2012-2020 onthe 2011 ITRS roadmap have been developed using BSIM-CMG models. The predictive models have been verified withpublished results and show excellent scalability across pro-cess and design conditions. The PTM-MG models allow themovement beyond time constants to actual circuit simula-tion in order to explore the impact of technology scalingusing multi-gate transistors. For more detailed predictionsof circuit design using FinFETs, accurate modeling of pro-cess variations, temperature and wire effects are importantareas of future work.

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