EXPERIMENT NO. 3

Aim: To implement D-Flipflop using static and dynamic latches and calculate setup time, hold time, clock -to-Q delay and data –to-Q delay.

1. Transmission Gate based Static Master-Slave D-Flipflop2. Dynamic Transmission Gate Edge Triggered D-Flipflop3. 𝐶2𝑀𝑂𝑆 D-Flipflop4. True Single Phase Clocked (TSPC) D-Fliplfop

Theory:

Timing Metrics for D-Flipflop

There are three important timing parameters associated with a register as illustrated in above figure. The set-up time (𝒕𝒔𝒖) is the time that the data inputs (D input) must be valid before the clock transition (this is, the 0 to 1 transition for a positive edge-triggered register). The hold time (𝒕𝒉𝒐𝒍𝒅) is the time the data input must remain valid after the clock edge. Assuming that the set-up and hold-times are met, the data at the D input is copied to the Q output after a worst-case propagation delay (with reference to the clock edge) denoted by �𝒕𝒄−𝒒�

1. Transmission Gate based Static Master-Slave D-Flipflop

Above figure shows reduced clock load static master-slave D-FF. The transmission gate (𝑇1) and its source driver must overpower the feedback inverter (𝐼2) to switch the state of the cross-coupled inverter. The sizing requirements for the transmission gates can be derived using a similar analysis as performed for the SR flip-flop. The input to the inverter 𝐼1 must be brought below its switching threshold in order to make a transition. If minimum-sized devices are to be used in the transmission gates, it is essential that the transistors of inverter I2 should be made even weaker. This can be accomplished by making their channel-lengths larger than minimum. Using minimum or close-to minimum size devices in the transmission gates is desirable to reduce the power dissipation in the latches and the clock distribution network. Problem with this scheme is the reverse conduction — this is, the second stage can affect the state of the first latch. When the slave stage is on, it is possible for the combination of 𝑇2 and 𝐼4 to influence the data stored in 𝐼1 − 𝐼2 latch. As long as 𝐼4 is a weak device, this is fortunately not a major problem. Another problem is the clock skew which may cause failure.

Schematic Diagram:

gndVDD

VDD

M11

M5

M10

M4

gnd

Q

gnd

VDD

VDD

CLK gnd

VDD

M7

M1

CLKBAR

gnd

gnd

VDD

M9

M8

M2

M3

VDD

CLK

gnd

M6

M0

VDD

CLKBAR

Data

M13

VDD

gnd

M12

CLK CLKBAR

gnd

CLK

val0=1.8val1=0

CLK

Data

val0=1.8val1=0

Data

gnd

Simulation Results:

V

SEL>>

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.1

CLK

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

15n 18n 21n 24n 27n 30n 33n 36n 39n12n 40n

Q

time, sA1:(15.50000ns, 900.00000mV); A2:(14.85940ns, 900.00000mV); dif:(640.60000ps, -2.55351fV)

V

SEL>>

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.1

CLK

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

15n 18n 21n 24n 27n 30n 33n 36n 39n12n 40n

Q

time, sA1:(15.50000ns, 900.00000mV); A2:(14.85930ns, 900.00000mV); dif:(640.70000ps, -1.22125fV)

The D-input edge is skewed relative to the clock signal until the output Q stops following D-input.

For a skew of 640.6 ps, the incorrect value of input D is sampled and an incorrect value propagates

to the output Q .

For a skew of 640.7 ps, output Q follows D-input. ∴ 𝒕𝒔𝒆𝒕𝒖𝒑 = 𝟔40. 𝟕 𝒑𝒔

V

SEL>>

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.1

CLK

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

15n 18n 21n 24n 27n 30n 33n 36n 39n12n 40n

Q

time, sA1:(15.96080ns, 900.00000mV); A2:(15.50000ns, 900.00000mV); dif:(460.80000ps, 3.88578fV)

V

SEL>>

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.1CLK

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

15n 18n 21n 24n 27n 30n 33n 36n 39n12n 40n

Q

time, sA1:(15.96090ns, 900.00000mV); A2:(15.50000ns, 900.00000mV); dif:(460.90000ps, 0.00000V)

After the D-input is set for correct setup time, the transaction edge on D-input is skewed relative to the clock signal until the circuit gives incorrect output. For a skew of 460.8 ps, the incorrect value of input D is sampled and an incorrect value propagates to the output Q.

For a skew of 460.9 ps, output Q follows D-input.

∴ 𝒕𝒉𝒐𝒍𝒅 = 𝟒𝟔𝟎.𝟗 𝒑𝒔

V

SEL>>

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.1CLK

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

14n 16n 18n 20n 22n 24n 26n12n 28n

Qtime, s

A1:(15.77636ns, 900.00000mV); A2:(15.50000ns, 900.00000mV); dif:(276.36484ps, 0.00000V)

Date/Time Run: 4/3/2016 8:31:09 AM

SymSpice

V

SEL>>

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

-0.1CLK

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

Data

V

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

14n 16n 18n 20n 22n 24n 26n12n 28n

Qtime, s

A1:(15.77636ns, 900.00000mV); A2:(14.85930ns, 900.00000mV); dif:(917.06484ps, 0.00000V)

Date/Time Run: 4/3/2016 8:31:09 AM

SymSpice

∴ Clock-to-Q delay 𝒕𝒄−𝒒 = 𝟐𝟕𝟔.𝟑𝟔𝟒𝟖𝟒 𝒑𝒔

∴ Data-to-Q delay 𝒕𝒅−𝒒 = 𝟗𝟏𝟕.𝟎𝟔𝟒𝟖𝟒 𝒑𝒔