EE 280-001 Ashley Exam 2 Name_________________

Spring 2010

1/5

You have 50 minutes to complete this exam. It is closed book, closed notes.

Put away your cell phones, programmable watches, and calculators. Show

all of your work and circle your final answer (additional paper will be

provided if necessary) and make sure it is organized and readable. Review

the exam before you begin.

1) (10 points – 1 point each) NUMBER CONVERSION. Convert the following

numbers to the number system given (and enter in the space provided). The numbers to

convert are decimal(base 10) unless otherwise noted.

a) +11 as a 5-bit sign and magnitude _____________________________

b) +11 as a 5-bit 1’s complement _____________________________

c) -7 as a 5-bit 1’s complement _____________________________

d) -7 as 5-bit 2’s complement _____________________________

e) +10 as 5-bit 2’s complement _____________________________

f) -10 as 5-bit 2’s complement _____________________________

g) 5-bit 2’s complement 10100 as decimal _______________________

h) 5-bit 2’s complement 11011 as decimal _______________________

i) (67)8 as 6-bit unsigned binary_____________________________

j) (CF)16 as 8-bit unsigned binary_____________________________

EE 280-001 Ashley Exam 2 Name_________________

Spring 2010

2/5

2) (10 points) ADDITION/SUBTRACTION Perform addition (part d – subtraction)

of the following 5-bit 2’s complement numbers. Check and note whether an overflow

has occurred (put a YES besides “Overflow=” if an overflow occurred, otherwise put a

NO). Additionally write down the result in decimal (i.e. base 10) for values that

didn’t overflow.

a) 11110 b) 10100

+00010 Overflow = +01111 Overflow =

c) 00101 d) 00101

+01100 Overflow = - 11001 Overflow =

Note : part e) is an 8-bit 2’s complement number e) 00001111

+11110000 Overflow =

3) (10 points) RIPPLE CARRY ADDER – First derive and draw the circuit diagram

for a 1-bit adder (using any gates you like). Then draw a 4-bit 2’s complement adder

(subtraction not required) labeling all of your inputs and outputs accordingly. Make

sure to include overflow detection. You can use a block diagram approach for drawing

the adder circuit.

Cin X Y | S | Cout

----------------------

0 0 0 | 0 | 0

0 0 1 | 1 | 0

0 1 0 | 1 | 0

0 1 1 | 0 | 1

1 0 0 | 1 | 0

1 0 1 | 0 | 1

1 1 0 | 0 | 1

1 1 1 | 1 | 1

EE 280-001 Ashley Exam 2 Name_________________

Spring 2010

3/5

4) (10 points) MULTIPLICATION. Perform the following binary multiplications of

unsigned numbers. Show and check your work. Determine the answer for each in

binary and in decimal.

a) 1010 b) 10110

* 0110 * 0100

5) VERILOG (5 points) a)Given inputs (v,w,x,y,z) and output (f) write a Verilog

module Vprob that implements the following function. AND = & , OR = | , NOT = ~

wy) zw(v zx v z)y,x,w,f(v,

module Vprob(v,w,x,y,z,f);

endmodule

b) (5 points) What functional component presented in Chapter 6 does the following

Verilog code represent? Be specific.

module WhatIsIt (W, Y, En);

input [1:0] W;

input En;

output reg [0:3] Y;

always @(W, En)

case ({En, W})

3'b100: Y = 4'b1000;

3'b101: Y = 4'b0100;

3'b110: Y = 4'b0010;

3'b111: Y = 4'b0001;

default: Y = 4'b0000;

endcase

endmodule

EE 280-001 Ashley Exam 2 Name_________________

Spring 2010

4/5

6) (10 points) SHANNON’S EXPANSION THEOREM. Consider f defined

below. Apply Shannon’s expansion theorem (also given below) with respect to input

z as if you were implementing this function using a 2:1 MUX. You need not draw the

circuit but make sure to place a box around your final equation.

Shannon’s Expansion Theorem

)w,,wf(1, * w )w,,wf(0, * w )w,,w,f(wn21n21n21

The function to be expanded

zxwxzzxwzyzyxwf ),,,(

7) (10 points) ANALYSIS. Consider the following circuit. What are the values of

the outputs (f,g,h,i) of this circuit given the following input valuations.

8) (10 points) FLOATING POINT. Express +(14.25)10 as a 32 bit IEEE 754

floating point number . The unidentified 11 bits of the mantissa (there are 12 underlines

you must fill in) will be filled with zeros so do not worry about these bits in your

answer. Value = +/- 1.M x 2E-127

ANSWER = __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ ……

S E M

Sign

32 bits

23 bits of mantissa excess-127 exponent

8-bit

S M E

+ 0 denotes – 1 denotes

w0

w1

EN

y1

y0

y2

y3

1

1

1

0

1

f

g

h

i

f= __ g= ___ h=___ i=___

EE 280-001 Ashley Exam 2 Name_________________

Spring 2010

5/5

9) (5 points) CARRY LOOKAHEAD ADDER. What is the primary advantage of

the Carry Lookahead adder over the Ripple Carry Adder?

10) (5 points) DECODERS AND ENCODERS. What does one-hot encoding mean

within the context of the devices covered in Chapter 6 of the textbook?

11) (5 points) SHANNONS USING A GRAPHICAL APPROACH. Implement the

following function given inputs X,Y,Z and output f using a 4:1 MUX and any other

non-MUX gates you may need.

X Y Z | f

----------------------

0 0 0 | 0

0 0 1 | 0

0 1 0 | 0

0 1 1 | 1

1 0 0 | 1

1 0 1 | 0

1 1 0 | 1

1 1 1 | 1

12) (5 points) BUILD A MUX. Derive a minimum cost 2:1 Multiplexer circuit using

only NOR gates given the following truth truth table.

s w0 w1 | f

----------------------

0 0 0 | 0

0 0 1 | 0

0 1 0 | 1

0 1 1 | 1

1 0 0 | 0

1 0 1 | 1

1 1 0 | 0

1 1 1 | 1