Ex. 1009: Invalidity of the ’247 Patent [Ex. 1001] over Go [Ex ......Ex. 1009: Invalidity of the...

Ex. 1009: Invalidity of the ’247 Patent [Ex. 1001] over Go [Ex. 1004] in view of Beers [Ex. 1005]

1

Limitation Prior Art Teachings

Claim: 1

1[preamble]. A data transfer system for a multi-level signal for providing a display data to a matrix display panel, comprising:

(Ex. 1004 [Go] at Figure 7 (For clarity, the material components of Figure 7 are highlighted as follows: Bus compressor 34 (blue); FPC cable 36 (yellow); Bus decompressor 46 (pink); Liquid crystal panel 42 (green))

Petitioner Valens Semiconductor 1009


2


“In order to achieve these and other objects of the invention, a bus compressing apparatus according to one aspect of the present invention includes at least two bit lines for receiving a bit data stream each; at least two voltage control means, each provided in the at least two bit lines, for changing voltage levels on each line into a ratio different each other; and adder means for adding the voltage levels changed by the at least voltage control means to generate and transfer an analog signal. A bus decompressing apparatus according to another aspect of the present invention includes means for receiving a single of analog signal in which at least two parallel bit data are compressed; quantizing means for quantizing the analog signal from the receiving means; and coding means for coding the quantized analog signal to reconstruct the at least two bit parallel data. A data interfacing apparatus according to still another aspect of the present invention includes bus compressing means for compressing at least two bit parallel data into a single of analog signal; and bus decompressing means, being installed in a data terminal, for decompressing for decompressing the analog signal from the data compressing means into the at least two bit parallel data. A liquid crystal display according to still another aspect of the present invention includes driver integrated circuits for divisionally driving a liquid crystal panel with at least two bit video data; signal input means for inputting a single analog signal, in which the at least two video data are compressed, from the exterior; and bus decompressing means for decompressing the analog signal from the signal input means into the at least two bit video data and for supplying the decompressed video data to the driver integrated circuits.”

(Ex. 1004 [Go] at 2:26-59; see also id. at Abstract)


3


“Referring to FIG. 7, there is shown a computer system to which an interfacing device adopting the correlation modulation scheme according to a preferred embodiment of the present invention. As shown in FIG. 7, the computer system includes a computer body 30 having a video card 32 and a bus compressor 34, and an LCD 40 connected to the video card 32 and the bus compressor over an FPC cable 36. The video card 32 is responsible for converting text and image informationinto video data in such a manner that the information is displayed as a picture by means of the LCD 40. The video data generated by the video card 32 include red(R), green(G), and blue(B) data for each pixel. Each one of the R, G, and B data has a 6-bit length, and hence the video data has a 18-bit length for each pixel. The video data VD comprising 18 bit lines are supplied, via a first bus line 31, to the bus compressor 34. Further, the video card 32 applies control signals including a data clock representing a period of the video data VD as well as various timing signals, via the first control bus 33, to a first connector 36A of the FPC cable 36. The bus compressor 34 compresses the 18-bit video data VD from the first data bus 31 to 9-analog signals. Specifically, the bus compressor 34 modulates 2 bit data from two bit lines of the first data bus 31 to a single analog signal having a different amplitude signal AMS in accordance with logical values of the 2 bit data. To this end, the bus compressor 34 includes 9-bus compression cells connected to two separate bit lines among the 18 bit lines of the first data bus 31. The 9-analog signals AMS generated by the bus compressor 34 in this manner are transferred to the LCD 40 over the FPC cable 36. As described above, the 18 bit video data are compressed into the 9-analog signals to reduce the number of lines in the FPC cable 36. The LCD 40 includes a number of D-ICs 44 for divisionally and selectively driving the pixels in the liquid crystal panel 42, a bus decompressor 46 for receiving the 9-analog signals AMS


4


from a second connector 36B of the FPC cable 36, and a controller 48 for receiving 10-control signals from the second connector 36B of the FPC cable 36. The bus decompressor 46 quantizes and codes the 9-analog signals AMS from the second connector 36B of the FPC cable 36 to substantially reconstruct 18-bit video data VD.”

(Ex. 1004 [Go] at 3:29 – 4:4)

[1a] a multi-level timing controller for receiving a digital data input and converting it into a multi-level signal display data output;

“DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 7, there is shown a computer system to which an interfacing device adopting the correlation modulation scheme according to a preferred embodiment of the present invention. As shown in FIG. 7, the computer system includes a computer body 30 having a video card 32 and a bus compressor 34, and an LCD 40 connected to the video card 32 and the bus compressor over an FPC cable 36. The video card 32 is responsible for converting text and image information into video data in such a manner that the information is displayed as a picture by means of the LCD 40. The video data generated by the video card 32 include red(R), green(G), and blue(B) data for each pixel. Each one of the R, G, and B data has a 6-bit length, and hence the video data has a 18-bit length for each pixel. The video data VD comprising 18 bit lines are supplied, via a first bus line 31, to the bus compressor 34. Further, the video card 32 applies control signals including a data clock representing a period of the video data VD as well as various timing signals, via the first control bus 33, to a first connector 36A of the FPC cable 36. The bus compressor 34 compresses the 18-bit video data VD from the first data bus 31 to 9-analog signals. Specifically, the bus compressor 34 modulates 2 bit data from two bit lines of the first data bus 31 to a single analog signal having a different amplitude signal AMS in accordance with logical values of the


5


2 bit data. To this end, the bus compressor 34 includes 9-bus compression cells connected to two separate bit lines among the 18 bit lines of the first data bus 31. The 9-analog signals AMS generated by the bus compressor 34 in this manner are transferred to the LCD 40 over the FPC cable 36. As described above, the 18 bit video data are compressed into the 9-analog signals to reduce the number of lines in the FPC cable 36.”

(Ex. 1004 [Go] at 3:26-62)

“The respective 2-bit data are compressed into a single analog signal by the bus compression cells. As a result, the line number of FPC cable transmitting the video data is reduced to 1/2 and power consumed for the transmission of the video data is reduced. As a result, the EMI outputted from the FPC cable is reduced. Further, if the bus decompressor 46 are located within each D-ICs 44 and an analog signal is applied from the second connector 36B of the FPC cable 36 to the D-ICs 44, then the EMI generated in the video data transferred from the video card 32 to the D-ICs 44 can be minimized and the wiring structure between the second connector 36B of the FPC cable 36 and the D-ICs 44 can be simplified.”

(Ex. 1004 [Go] at 4:22-34)

“Moreover, if that the bus compression cells of the bus compressor 34 compress 3 or more bits of data rather than 2 bits of data into a single of analog data, then the line number of FPC cable can be further reduced and the wiring structure between the second connector 36B and the D-ICs 44 can be further simplified.”

(Ex. 1004 [Go] at 4:35-41)


6



“FIG. 8 is a circuit diagram of the bus compression cell included in the bus compressor 34 shown in FIG. 7. The bus compression cell includes a first resistor R1 connected


7


between, for example, an odd-numbered bit line 31A of the first data bus 31 and an output line 51, and a second resistor R2 connected between, for example, an even-numbered bit line 31B of the second data bus 31 and the output line 51. The first resistor R1 drops a voltage level of the odd-numbered bit data Dn from the odd-numbered bit line 31A by ⅓ and delivers the reduced voltage signal to the output line 51. The second resistor R2 drops a voltage level of the even-numbered bit data Dn+1 from the even-numbered bit line 31B by ⅔ and delivers the reduced voltage signal to the output line 51.

Accordingly, the output line 51 outputs an analog signal AMS (Amplitude Modulated Signal) having a sum voltage of voltage signals dropped by the first and second resistors R1 and R2 at the bit transmission line 36A. The analog signal emerging at the output line 51 are applied to the second connector 36A of the FPC cable 36 in FIG. 7.”

(Ex. 1004 [Go] at 4:42-61)

(Ex. 1004 [Go] at Figure 8)

“As shown in FIG. 9, the analog signal AMS has an amplitude varying in accordance with a logical value of the 2 bit data Dn and Dn+l from the odd-numbered and even-numbered bit lines 31A and 31B.”


8


(Ex. 1004 [Go] at 4:62-65; see also id. at 4:66 – 5:5)


“Similarly, if the bus compression cell of the bus compressor 34 is used for compressing 3-bits of data, then there are three resistors Rl, R2 and R3 outputs of which are connected together. In such case, the values of Rl, R2 and R3 are set to have a ratio of 4 to 2 to 1, respectively.”

(Ex. 1004 [Go] at 5:6-10)

“The present invention relates generally to the conversion of signals between digital and analog formats to optimize data transmission over a frequency limited bus. More particularly, the invention is directed to grouping and converting digital signals into multilevel analog signals for current source based transmission over a bus, and related reconversion to digital format at the receiving end of the bus.”

(Ex. 1005 [Beers] at 1:18-25)

“The use of a relatively low frequency capability bus to


9


transmit data between relatively high frequency operation devices is accomplished through the use of an architecture comprising a means for providing digital signals at a first cycle rate, means for latching the digital format signals for multiple successive cycles, means for converting latched digital format signals into multilevel analog format signals, means for sending the analog format signals from a transmitting end of a bus to a receiving end of the bus, the bus characterized in having a maximum operating frequency materially less than the first cycle rate, means for converting analog format signals received from the bus into received digital format signals distributed over multiple successive cycles, and reference current transmitted over a reference line connecting the means for converting latched digital format signals to the means for converting analog format signals. In other forms, the invention relates to the method practiced by the preceding apparatus and to a particularized bus architecture for connecting a processor to a peripheral having the characterized clock frequency relationships.”

(Ex. 1005 [Beers] at 1:66 – 2:18)

“The present invention addresses and overcomes this problem by operating the bus in a multilevel analog mode to simultaneously transmit groups of digital signals from successive clock cycles, whereby the simultaneous multilevel analog transmission of grouped digital signals offsets the lower clock rate capability of the bus.”

(Ex. 1005 [Beers] at 3:18–24)

(Ex. 1005 [Beers] at Figure 1)


10


“FIG. 2 schematically illustrates by functional blocks an embodiment of the present invention in the context of one directional transmission over I/O bus 3. As embodied in FIG. 2, processor 1 is on a common integrated circuit chip, generally 4, with interface latches 6, current source drivers 7, and reference generator 8. Operations performed on integrated circuit chip 4 are generally digital in format.”

(Ex. 1005 [Beers] at 3:33–40)


11



“The interface latches in block 6 of FIG. 2 are shown in the embodiment of FIG. 8. The function, performed individually by bus line, is to receive data from the processor over multiple successive clock cycles, to latch the data, and to provide the


12


combination as an input to current source driver 7 for simultaneous digital to analog conversion, a serial to parallel type conversion. As embodied in FIG. 8, line 1 from the processor bus is provided as an input to latch 44, whose output is thereupon provided to latch 46 in processor clocked succession. In conjunction, latches 47 and 48 are synchronized to the I/O clock, which in this embodiment operates at half the processor clock, to receive the outputs from corresponding latches 44 and 46, and in I/O clocked succession to provide as outputs the data representing bit A and bit B, the bits having been the successive binary values on line 1 from the processor. The bits from latches 47 and 48 serve as the enable signals for gates 21 and 22 shown in FIG. 3.”

(Ex. 1005 [Beers] at 5:57 – 6:7)


“FIG. 3 also depicts the current source drivers for line 1 of I/O bus 3. The current source drivers for line 1 of the bus are composed of switch current source 18 and switch current


13


source 19, where the output of current source 18 is either 0 or i/2, and the output of current source 19 is either 0 or i, depending on the respective states of switches 21 and 22. When the switches 21 and/or 22 are enabled, the currents generated in sources 18 and 19 responsive to the reference voltage VREF are provided in respective magnitudes of i/2 or i output current. Preferably, the current sources are current mirror connected field effect transistors. The states of switches 21 and 22 are defined by the binary value associated with respective bits B and A, the bits being derived from interface latches 6 (FIG. 2). The line 1 current iT is the net sum of the two currents generated by current sources 18 and 19, with incremental values as shown in the table of FIG. 2 of 0, i/2, i or 3i/2. A preferred design may inject a bias current into line 1 to optimize field effect transistor operational locations for the digital to analog and analog to digital conversions as shown at 20 in FIG. 3. Current source driver 7 uses the reference signal generated by reference generator 8 to perform the digital to analog conversion between digital bit pair A and B and analog output current iT. Generator 8 also provides the reference current signal IREF to receiving integrated circuit chip 9 to ensure an accurate decode of the analog signal back into digital format. The decoding is accomplished using the circuit in FIG. 4.”

(Ex. 1005 [Beers] at 4:31-58)


14



“FIG. 11 schematically depicts a generalized architecture for performing the interface latches and current source driver


15


functions ascribed to blocks 6 and 7 in FIG. 2 for further levels of analog transmission, whereby additional clock cycles of digital format data are accumulated in the latches at 54, individually converted into current source signals at 56, and accumulated as a single net analog current (Iout) for transmission over a line of the data bus. The invention is particularly valuable in that it defines a system and method which uses accurately coded and decoded analog currents to simultaneously transmit over a single line multiple digital bits between separate integrated circuit devices, effectively extending the line bandwidth.”

(Ex. 1005 [Beers] at 6:55-67)


16



“16. A bus architecture for connecting a processor to a peripheral, comprising: a processor providing digital signals at a first cycle rate;

means for latching the digital format signals for multiple


17


successive cycles;

means for converting latched digital format signals into multilevel analog format signals;

means for sending the analog format signals from a transmitting end of a bus to a receiving end of the bus, the bus characterized in having a maximum operating frequency materially less than the first cycle rate;

means for converting analog format signals received from the bus into received digital format signals distributed over multiple successive cycles;

reference current flowing in a reference line connecting the means for converting latched digital format signals to the means for converting analog format signals; and

a peripheral connected to receive the received digital format signals at the receiving end of the bus.”

(Ex. 1005 [Beers] at Claim 16)

[1b] a multi-level signal bus having a plurality of data lines, connected to said multi-level timing controller, for transferring said multi-level signal display data from said multi-level timing controller;


18


and


“FIG. 8 is a circuit diagram of the bus compression cell included in the bus compressor 34 shown in FIG. 7. The bus compression cell includes a first resistor R1 connected


19


between, for example, an odd-numbered bit line 31A of the first data bus 31 and an output line 51, and a second resistor R2 connected between, for example, an even-numbered bit line 31B of the second data bus 31 and the output line 51. The first resistor R1 drops a voltage level of the odd-numbered bit data Dn from the odd-numbered bit line 31A by ⅓ and delivers the reduced voltage signal to the output line 51. The second resistor R2 drops a voltage level of the even-numbered bit data Dn+1 from the even-numbered bit line 31B by ⅔ and delivers the reduced voltage signal to the output line 51.

Accordingly, the output line 51 outputs an analog signal AMS (Amplitude Modulated Signal) having a sum voltage of voltage signals dropped by the first and second resistors R1 and R2 at the bit transmission line 36A. The analog signal emerging at the output line 51 are applied to the second connector 36A of the FPC cable 36 in FIG. 7.”

(Ex. 1004 [Go] at 4:42-61)


“As shown in FIG. 9, the analog signal AMS has an amplitude varying in accordance with a logical value of the 2 bit data Dn and Dn+l from the odd-numbered and even-numbered bit lines 31A and 31B.”


20


(Ex. 1004 [Go] at 4:62-65; see also id. at 4:66 – 5:5)


“The bus compressor 34 compresses the 18-bit video data VD from the first data bus 31 to 9-analog signals. Specifically, the bus compressor 34 modulates 2 bit data from two bit lines of the first data bus 31 to a single analog signal having a different amplitude signal AMS in accordance with logical values of the 2 bit data. To this end, the bus compressor 34 includes 9-bus compression cells connected to two separate bit lines among the 18 bit lines of the first data bus 31. The 9-analog signals AMS generated by the bus compressor 34 in this manner are transferred to the LCD 40 over the FPC cable 36. As described above, the 18 bit video data are compressed into the 9-analog signals to reduce the number of lines in the FPC cable 36.”

(Ex. 1004 [Go] at 3:50-62; see also id. at 3:39-49) “Similarly, if the bus compression cell of the bus compressor 34 is used for compressing 3-bits of data, then there are three resistors Rl, R2 and R3 outputs of which are connected together. In such case, the values of Rl, R2 and R3 are set to have a ratio of 4 to 2 to 1, respectively.”


21


(Ex. 1004 [Go] at 5:6-10)

“The present invention relates generally to the conversion of signals between digital and analog formats to optimize data transmission over a frequency limited bus. More particularly, the invention is directed to grouping and converting digital signals into multilevel analog signals for current source based transmission over a bus, and related reconversion to digital format at the receiving end of the bus.”

(Ex. 1005 [Beers] at 1:18-25)

“The use of a relatively low frequency capability bus to transmit data between relatively high frequency operation devices is accomplished through the use of an architecture comprising a means for providing digital signals at a first cycle rate, means for latching the digital format signals for multiple successive cycles, means for converting latched digital format signals into multilevel analog format signals, means for sending the analog format signals from a transmitting end of a bus to a receiving end of the bus, the bus characterized in having a maximum operating frequency materially less than the first cycle rate, means for converting analog format signals received from the bus into received digital format signals distributed over multiple successive cycles, and reference current transmitted over a reference line connecting the means for converting latched digital format signals to the means for converting analog format signals. In other forms, the invention relates to the method practiced by the preceding apparatus and to a particularized bus architecture for connecting a processor to a peripheral having the characterized clock frequency relationships.”

(Ex. 1005 [Beers] at 1:66 – 2:18)

“The present invention addresses and overcomes this problem by operating the bus in a multilevel analog mode to


22


simultaneously transmit groups of digital signals from successive clock cycles, whereby the simultaneous multilevel analog transmission of grouped digital signals offsets the lower clock rate capability of the bus.”

(Ex. 1005 [Beers] at 3:18–24)


“FIG. 2 schematically illustrates by functional blocks an embodiment of the present invention in the context of one directional transmission over I/O bus 3. As embodied in FIG. 2, processor 1 is on a common integrated circuit chip, generally 4, with interface latches 6, current source drivers 7, and reference generator 8. Operations performed on integrated circuit chip 4 are generally digital in format.”

(Ex. 1005 [Beers] at 3:33–40)


23



“FIG. 3 also depicts the current source drivers for line 1 of I/O bus 3. The current source drivers for line 1 of the bus are composed of switch current source 18 and switch current source 19, where the output of current source 18 is either 0 or


24


i/2, and the output of current source 19 is either 0 or i, depending on the respective states of switches 21 and 22. When the switches 21 and/or 22 are enabled, the currents generated in sources 18 and 19 responsive to the reference voltage VREF are provided in respective magnitudes of i/2 or i output current. Preferably, the current sources are current mirror connected field effect transistors. The states of switches 21 and 22 are defined by the binary value associated with respective bits B and A, the bits being derived from interface latches 6 (FIG. 2). The line 1 current iT is the net sum of the two currents generated by current sources 18 and 19, with incremental values as shown in the table of FIG. 2 of 0, i/2, i or 3i/2. A preferred design may inject a bias current into line 1 to optimize field effect transistor operational locations for the digital to analog and analog to digital conversions as shown at 20 in FIG. 3. Current source driver 7 uses the reference signal generated by reference generator 8 to perform the digital to analog conversion between digital bit pair A and B and analog output current iT. Generator 8 also provides the reference current signal IREF to receiving integrated circuit chip 9 to ensure an accurate decode of the analog signal back into digital format. The decoding is accomplished using the circuit in FIG. 4.”

(Ex. 1005 [Beers] at 4:31-58)


25



“FIG. 11 schematically depicts a generalized architecture for performing the interface latches and current source driver


26


functions ascribed to blocks 6 and 7 in FIG. 2 for further levels of analog transmission, whereby additional clock cycles of digital format data are accumulated in the latches at 54, individually converted into current source signals at 56, and accumulated as a single net analog current (Iout) for transmission over a line of the data bus. The invention is particularly valuable in that it defines a system and method which uses accurately coded and decoded analog currents to simultaneously transmit over a single line multiple digital bits between separate integrated circuit devices, effectively extending the line bandwidth.”

(Ex. 1005 [Beers] at 6:55-67)


27




means for latching the digital format signals for multiple


28


successive cycles;







[1c] a multi-level input data driver connected to said multi-level signal bus, for receiving said multi-level signal display data input and converting it into a data driving signal to be outputted to said matrix


29


display panel.


“The bus decompressor 46 quantizes and codes the 9-analog signals AMS from the second connector 36B of the FPC cable 36 to substantially reconstruct 18-bit video data VD. The bus


30


decompressor 46 includes 9-bus decompression cells(not shown) responsive and corresponding to the 9-analog signals AMS. The reconstructed video data VD are commonly supplied, via a second data bus 41 comprising 18-bit lines, to the D-ICs 44. The controller 48 also applies the 7-control signals for controlling the operation of the D-ICs 44 using the 10-control signals from the second connector 36B of the FPC cable 36, via the second control bus 43, to the D-ICs 44. The D-ICs 44 sequentially receive the decompressed video data VD from the second data bus 41comprising 7-control signals from the second control bus 43. The video data VD for one pixel line are distributively and simultaneously inputted to each D-IC 44 the output of which are supplied to the liquid crystal panel 42 to drive the pixels for one line. Such operations of the D-ICs 44 and the liquid crystal panel 22 are repeated for the number of pixel lines, thereby displaying a single image.”

(Ex. 1004 [Go] at 4:1-22)

“FIG. 10 is a circuit diagram of the bus decompression cell included in the bus decompressor 46 in FIG. 7. FIG. 11 is operational timing diagrams of each part of the bus decompressor 46 shown in FIG. 10. Referring now to FIG. 10, the bus decompression cell includes first to third level detectors 50, 52 and 54 which are commonly connected to an input line 53 coupled with the second connector 36B of the FPC cable 36 in FIG. 7, and a coder 56 for coding the output signals of the level detectors 50, 52 and 54. The first to third level detectors 50, 52 and 54 detect a voltage level (i.e., amplitude) of an analog signal AMS from the bus compressor 34. A sample AMS signal is shown in FIG. 11. The first level detector 50 generates a low logic of first amplitude detection signal ADl when the analog signal AMS is above a first predetermined voltage level. The second amplitude detection signal AD2 generates a low logic of second amplitude detection signal AD2 when the analog signal AMS is above a second predetermined voltage level. The third


31


amplitude detection signal AD3 generates a low logic of third amplitude detection signal AD3 when the analog signal AMS is above a third predetermined voltage level. The first to third amplitude detection signals ADl to AD3 indicate an amplitude value (or a quantized value) of the analog signal AMS. As a result, the first to third level detectors 50, 52 and 54 serve to quantize the analog signal AMS. The coder 56 codes the amplitude values assigned by the first to third amplitude detection signals ADl to AD3 from the first to third level detectors 50, 52 and 54 into 2 bit data. The low order bit data and the high order bit data coded by the coder 56 are used as the odd-numbered bit data Dn and the even-numbered bit data Dn+l, respectively. The second level detection signal AD2 generated at the second level detector 52 is used as the even-numbered bit data Dn+l. On the other hand, the odd-numbered bit data Dn are generated by logically combining the first to third level detection signals ADl to AD3. To this end, the coder 56 includes first and second AND gates ANDI and AND2, and a negative logic buffer NBl. The odd-numbered and even-numbered bit data Dn and Dn+l reconstructed in this manner are supplied to the second data bus 41 in FIG. 7.”

(Ex. 1004 [Go] at 5:10 – 5:52)


32



“FIG. 12 is a circuit diagram of an embodiment of the level detectors 50 to 54 shown in FIG. 10. The respective level detectors 50, 52 and 54 include an NMOS transistor MPl connected to an input line 53, a ground GND and the node 55, and a third resistor R3 connected between the node 55 and a power supply Vcc. The NMOS transistor MPl bypasses a voltage at the node 55 to the ground GND when an analog signal AMS applied from the input line 53 to the gate terminal thereof is greater than a threshold voltage Vth of the transistor MPl, thereby generating a low logic of amplitude detection signal AD. Alternatively, the NMOS transistor MPl opens the node 55 from the ground GND when the analog signal AMS applied from the input line 53 to the gate terminal thereof is less than the threshold voltage Vth, thereby generating a high logic of amplitude detection signal AD on the node 55. The threshold voltage Vth of the NMOS transistor MPl is determined depending on the voltage levels to be detected by the level detectors 50, 52 and 54. Specifically, the threshold


33


voltage Vth of the NMOS transistor MPl is preferably set to be slightly less than about Vcc/3 in the case of the first level detector 50 detecting a voltage corresponding to 1/3 of the supply voltage Vcc, to about Vcc/3 to Vccx2/3 in the case of the second level detector 52 detecting a voltage corresponding to 2/3 of the supply voltage Vcc, and to about Vccx2/3 to Vcc in the case of the third level detector 54 detecting a voltage corresponding to the supply voltage Vcc. Accordingly, an amplitude detection signal AD generated at the node 55 has a high logic when the analog signal AMS is less than the subject detecting voltage while having a low logic when the analog signal AMS is higher than the subject detecting voltage.”

(Ex. 1004 [Go] at 5:53 – 6:16)


“The present invention relates generally to the conversion of signals between digital and analog formats to optimize data transmission over a frequency limited bus. More particularly, the invention is directed to grouping and converting digital signals into multilevel analog signals for current source based


34


transmission over a bus, and related reconversion to digital format at the receiving end of the bus.”

(Ex. 1005 [Beers] at 1:18-25)

“The use of a relatively low frequency capability bus to transmit data between relatively high frequency operation devices is accomplished through the use of an architecture comprising a means for providing digital signals at a first cycle rate, means for latching the digital format signals for multiple successive cycles, means for converting latched digital format signals into multilevel analog format signals, means for sending the analog format signals from a transmitting end of a bus to a receiving end of the bus, the bus characterized in having a maximum operating frequency materially less than the first cycle rate, means for converting analog format signals received from the bus into received digital format signals distributed over multiple successive cycles, and reference current transmitted over a reference line connecting the means for converting latched digital format signals to the means for converting analog format signals. In other forms, the invention relates to the method practiced by the preceding apparatus and to a particularized bus architecture for connecting a processor to a peripheral having the characterized clock frequency relationships.”

(Ex. 1005 [Beers] at 1:66 – 2:18)

“The present invention addresses and overcomes this problem by operating the bus in a multilevel analog mode to simultaneously transmit groups of digital signals from successive clock cycles, whereby the simultaneous multilevel analog transmission of grouped digital signals offsets the lower clock rate capability of the bus.”

(Ex. 1005 [Beers] at 3:18–24)


35



“FIG. 2 schematically illustrates by functional blocks an embodiment of the present invention in the context of one directional transmission over I/O bus 3. As embodied in FIG. 2, processor 1 is on a common integrated circuit chip, generally 4, with interface latches 6, current source drivers 7, and reference generator 8. Operations performed on integrated circuit chip 4 are generally digital in format. An analogous chip, generally at 9, also operates for the most part in a digital format, and for purposes of the embodiment in FIG. 2 encompasses peripheral 2, peripheral multiplexer 11, multilevel converter 12, and reference replicator 13.”

(Ex. 1005 [Beers] at 3:33–40)


36



“Current source driver 7 uses the reference signal generated by reference generator 8 to perform the digital to analog conversion between digital bit pair A and B and analog output current iT. Generator 8 also provides the reference current


37


signal IREF to receiving integrated circuit chip 9 to ensure an accurate decode of the analog signal back into digital format. The decoding is accomplished using the circuit in FIG. 4.”

(Ex. 1005 [Beers] at 4:31-58)

“A circuit embodying multilevel converter 12 (FIG. 2) is shown in FIG. 4. The analog format current signal iT on line 1 of the I/O bus is sunk by active terminator 23. As noted earlier, the magnitude of the current iT is 0, i/2, i, or 3i/2, generating respective voltages on the terminator and the mirror connected gate electrodes of field transistors 24 and 26. The currents drawn by field effect transistors 24 and 26 are compared in separate channels to currents i/2 and i, generated by current sources 27 and 28. Note that current source 28 is selectively enabled by switch 29 responsive to the binary state of bit A on output line 31. The bit B output on line 32 depends on the current sunk by field effect transistor 26 in relation to the current generated by switched current source 28. Current source 33 provides a bias to center the threshold between the aforementioned levels through the current sinking effects reflected in field effect transistors 34 and 36 as to bits A and B. The table at reference numeral 37 defines the relationships between the analog input current iT and the binary format values of bits A and B.”

(Ex. 1005 [Beers] at 4:59 – 5:11)


38



“FIG. 9 depicts the electronic circuit for multiplexer 11 as originally shown in FIG. 2. The multiplexer effectively converts the decoded digital format data from parallel to serial format in keeping with the order originally transmitted from processor 1 (FIG. 2). Multiplexer 11 is responsive to the I/O clock signal, and in the embodiment of FIG. 9 represents the


39


circuit used for one of the multiple bus lines transmitting data between processor 1 and peripheral 2. The processor clock must be generated in synchronization with I/O clock.”

(Ex. 1005 [Beers] at 6:8–17)


“Multilevel converter 49 as embodied in FIG. 10 illustrates an architecture for a 3-bit multilevel converter. Converter 49 also shows how the basic architecture first described with reference to FIG. 4 may be extended for multiple additional bits through an increase in the number of channels used to perform the comparison, namely, channels 51, 52 and 53, with associated current sources and high speed switches. The basic architecture is particularly unique and valuable in that the comparisons in the various channels 51, 52 and 53 are performed at substantially the same time, and as such cause converter 49 to operate in a manner analogous to a flash converter. The input current iT is a multilevel analog signal now coded to represent three binary bits, characterized in one of eight discrete levels, and by operation of converter 49 generates binary bit equivalents as represented by output bits 1, 2 and 3. The least significant current step shown here is i, where in the previous embodiment the minimum step was i/2. See Table A. The various current sources are created and switched in keeping


40


with the previously described embodiments, where high speed switch 29 is preferably that depicted in FIG. 7. The fundamental architecture of the embodiment in FIG. 10 is extendable to additional bit levels through the use of more channels, and is amenable decimal magnitudes in selectively switched current sources.”

(Ex. 1005 [Beers] at 6:18-42)

(Ex. 1005 [Beers] at 6:43-53)


41




42



means for latching the digital format signals for multiple successive cycles;







Claim: 2

2. The system according to claim 1, wherein said multi-level timing controller comprises a multi-level encoder for encoding said digital

Beers teaches “said multi-level timing controller comprises a multi-level encoder for encoding said digital data input.” See Claim 1[a]. Go teaches “a multi-level encoder for encoding said digital data input.” See Claim 1[a]. Go and Beers each teach “said multi-level input data driver comprises a multi-level decoder for decoding said multi-level signal display data.” See Claim 1[c].


43


data input and said multi-level input data driver comprises a multi-level decoder for decoding said multi-level signal display data.

Claim: 3

3[preamble]. A data transfer method for a multi-level signal for providing a display data to a matrix display panel, said method comprising the steps of:

See Claim 1[preamble].

[3](a) converting a first digital data signal into a multi-level signal display data output by a multi-level

See Claim 1[a].


44


timing controller;

[3](b) transferring said multi-level signal display data by a multi-level signal bus comprising a plurality of data lines; and

See Claim 1[b].

[3](c) converting said multi-level signal display data input into a second digital data signal by a multi-level input data driver.

See Claim 1[c].

Claim: 4

4. The method according to claim 3, further comprising converting said second digital data

On the other hand, in a prior art digital input data driver 20 shown in FIG. 4, data from FIG. 3 passes through an input data register 22, an internal processing logic 24 and a digital-to-analog converter (DAC) to become an analog signal output, which is a data driving signal.

(Ex. 1001 [’247 APA] at 4:28-32)


45


signal into an analog signal.

Claim: 5

5. The method according to claim 3, wherein step (a) comprises encoding said first digital data signal by a multi-level encoder, and step (c) comprises decoding said multi-level signal display data by a multi-level decoder.

Go and Beers each teach “step (a) comprises encoding said first digital data signal by a multi-level encoder.” See Claim 1[a] Go and Beers each teach “step (c) comprises decoding said multi-level signal display data by a multi-level decoder.” See Claim 1[c].

Claim: 6

6[preamble]. A liquid crystal display device, comprising:

“FIG. 7 is a schematic view of an LCD computer systememploying a bus compressor and a bus decompressor according to an embodiment of the present invention.”

(Ex. 1004 [Go] at 3:12-14; see also id. at 3:29-43)


46



“In order to achieve these and other objects of the invention, a bus compressing apparatus according to one aspect of the present invention includes at least two bit lines for receiving a bit data stream each; at least two voltage control means, each provided in the at least two bit lines, for changing voltage


47


levels on each line into a ratio different each other; and adder means for adding the voltage levels changed by the at least voltage control means to generate and transfer an analog signal. A bus decompressing apparatus according to another aspect of the present invention includes means for receiving a single of analog signal in which at least two parallel bit data are compressed; quantizing means for quantizing the analog signal from the receiving means; and coding means for coding the quantized analog signal to reconstruct the at least two bit parallel data. A data interfacing apparatus according to still another aspect of the present invention includes bus compressing means for compressing at least two bit parallel data into a single of analog signal; and bus decompressing means, being installed in a data terminal, for decompressing for decompressing the analog signal from the data compressing means into the at least two bit parallel data. A liquid crystal display according to still another aspect of the present invention includes driver integrated circuits for divisionally driving a liquid crystal panel with at least two bit video data; signal input means for inputting a single analog signal, in which the at least two video data are compressed, from the exterior; and bus decompressing means for decompressing the analog signal from the signal input means into the at least two bit video data and for supplying the decompressed video data to the driver integrated circuits.”

(Ex. 1004 [Go] at 2:26-59; see also id. at Abstract)

“Referring to FIG. 7, there is shown a computer system to which an interfacing device adopting the correlation modulation scheme according to a preferred embodiment of the present invention. As shown in FIG. 7, the computer system includes a computer body 30 having a video card 32 and a bus compressor 34, and an LCD 40 connected to the video card 32


48


and the bus compressor over an FPC cable 36. The video card 32 is responsible for converting text and image information into video data in such a manner that the information is displayed as a picture by means of the LCD 40. The video data generated by the video card 32 include red(R), green(G), and blue(B) data for each pixel. Each one of the R, G, and B data has a 6-bit length, and hence the video data has a 18-bit length for each pixel. The video data VD comprising 18 bit lines are supplied, via a first bus line 31, to the bus compressor 34. Further, the video card 32 applies control signals including a data clock representing a period of the video data VD as well as various timing signals, via the first control bus 33, to a first connector 36A of the FPC cable 36. The bus compressor 34 compresses the 18-bit video data VD from the first data bus 31 to 9-analog signals. Specifically, the bus compressor 34 modulates 2 bit data from two bit lines of the first data bus 31 to a single analog signal having a different amplitude signal AMS in accordance with logical values of the 2 bit data. To this end, the bus compressor 34 includes 9-bus compression cells connected to two separate bit lines among the 18 bit lines of the first data bus 31. The 9-analog signals AMS generated by the bus compressor 34 in this manner are transferred to the LCD 40 over the FPC cable 36. As described above, the 18 bit video data are compressed into the 9-analog signals to reduce the number of lines in the FPC cable 36. The LCD 40 includes a number of D-ICs 44 for divisionally and selectively driving the pixels in the liquid crystal panel 42, a bus decompressor 46 for receiving the 9-analog signals AMS from a second connector 36B of the FPC cable 36, and a controller 48 for receiving 10-control signals from the second connector 36B of the FPC cable 36. The bus decompressor 46 quantizes and codes the 9-analog signals AMS from the second connector 36B of the FPC cable 36 to substantially reconstruct 18-bit video data VD.”


49


(Ex. 1004 [Go] at 3:29 – 4:4)

[6a] a matrix liquid crystal display panel;


A liquid crystal display according to still another aspect of the present invention includes driver integrated circuits for divisionally driving a liquid crystal panel with at least two bit


50


video data; signal input means for inputting a single analog signal, in which the at least two video data are compressed, from the exterior; and bus decompressing means for decompressing the analog signal from the signal input means into the at least two bit video data and for supplying the decompressed video data to the driver integrated circuits.”

(Ex. 1004 [Go] at 2:50-59; see also id. at at 3:29 – 4:4)

“For example, in a 6-bit XGA notebook computer, data transfer system of the LCD is shown in FIG. 2. An input interface 50 utilizes a transceiver for low voltage differential signal (LVDS). The transceiver receives a digital input signal and then outputs it to a digital timing controller 40 where it is converted into a digital display data signal and sent to a digital input data driver 20. Digital data bus lines between the digital timing controller 40 and digital input data driver 20 only carry signals of either logic ‘0’ or ‘1’.”

(Ex. 1001 [’247 APA] at 2:19-27)

“FIG. 2 is a schematic view of a conventional data transfer system of a LCD for a notebook computer with a 6-bit XGA.”

(Ex. 1001 [’247 APA] at 3:11-12)

(Ex. 1001 [’247 APA] at Figure 2)

[6b] a scan driver for providing a

“FIG. 1 is a block diagram showing a conventional active matrix LCD. A LCD panel 100 comprises a plurality of data bus lines X1, X2, . . . , Xm, a plurality of scan bus lines Y1,


51


scan voltage signal to said liquid crystal display panel by a plurality of scan bus lines; and

Y2, . . . , Yn, and a plurality of pixels disposed between the data bus lines and scan bus lines. Each of the pixels consists of a liquid crystal cell and a switching element. In this case, the switching element is a thin film transistor (TFT). The TFT is connected between the liquid crystal cell and one of the data bus lines, and it has a gate connected to one of the scan bus lines. A scan driver 10 selects one of the TFTs in a LCD panel 100 and a digital input data driver 20 provides a data driving signal. A voltage signal required by the scan driver 10 and the digital input data driver 20 is provided by a DC-DC and γ voltage generator 30. A display data required for image display is generated by a digital timing controller 40 through an input interface 50, and is sent to the digital input data driver 20 via a digital bus 60.”

(Ex. 1001 at 1:26-43 (Background of the Invention), Fig. 1).


52




53


[6c] a display data transfer system for providing a data driving signal to said liquid crystal display panel by a plurality of data bus lines, said display data transfer system comprising:

(Ex. 1004 [Go] at Figure 7 (For clarity, the material components of Figure 7 are highlighted as follows: Bus compressor 34 (blue); FPC cable 36 (yellow); Bus decompressor 46 (pink); Liquid crystal panel 42 (green); D-IC 44 (grey))

“The LCD 40 includes a number of D-ICs 44 for divisionally and selectively driving the pixels in the liquid crystal panel 42,


54


a bus decompressor 46 for receiving the 9-analog signals AMS from a second connector 36B of the FPC cable 36, and a controller 48 for receiving 10-control signals from the second connector 36B of the FPC cable 36.”

(Ex. 1004 [Go] at 3:63 – 4:1)

The bus decompressor 46 includes 9-bus decompression cells(not shown) responsive and corresponding to the 9-analog signals AMS. The reconstructed video data VD are commonly supplied, via a second data bus 41 comprising 18-bit lines, to the D-ICs 44. The controller 48 also applies the 7-control signals for controlling the operation of the D-ICs 44 using the 10-control signals from the second connector 36B of the FPC cable 36, via the second control bus 43, to the D-ICs 44. The D-ICs 44 sequentially receive the decompressed video data VD from the second data bus 41 comprising 7-control signals from the second control bus 43. The video data VD for one pixel line are distributively and simultaneously inputted to each D-IC 44 the output of which are supplied to the liquid crystal panel 42 to drive the pixels for one line. Such operations of the D-ICs 44 and the liquid crystal panel 22 are repeated for the number of pixel lines, thereby displaying a single image.

(Ex. 1004 [Go] at 4:5-21)

[6d] a multi-level timing controller for receiving a digital data input and converting it into a multi-level signal display data

See Claim 1[a]


55


output;

[6e] a multi-level signal bus having a plurality of data lines, connected to said multi-level timing controller, for transferring said multi-level signal display data from said multi-level timing controller; and

See Claim 1[b]

[6f] a multi-level input data driver connected to said multi-level signal bus, for receiving said multi-level signal display data input and converting it into said data driving signal.

See Claim 1[c]


56


Claim: 7

7. The device according to claim 6, wherein said multi-level timing controller comprises a multi-level encoder for encoding said digital data input and said multi-level input data driver comprises a multi-level decoder for decoding said multi-level signal display data.

Beers teaches “said multi-level timing controller comprises a multi-level encoder for encoding said digital data input.” See Claim 1[a]. Go teaches “a multi-level encoder for encoding said digital data input.” See Claim 1[a]. Go and Beers each teach “said multi-level input data driver comprises a multi-level decoder for decoding said multi-level signal display data.” See Claim 1[c].

Claim: 8

8. The system according to claim 1, wherein said multi-level signal display data is in the

“Similarly, if the bus compression cell of the bus compressor 34 is used for compressing 3-bits of data, then there are three resistors Rl, R2 and R3 outputs of which are connected together. In such case, the values of Rl, R2 and R3 are set to have a ratio of 4 to 2 to 1, respectively.”

(Ex. 1004 [Go] at 5:6-10)

“FIG. 10 is a circuit diagram of the bus decompression cell


57


form of digital signals with amplitudes equal to one of eight values.

included in the bus decompressor 46 in FIG. 7. FIG. 11 is operational timing diagrams of each part of the bus decompressor 46 shown in FIG. 10. Referring now to FIG. 10, the bus decompression cell includes first to third level detectors 50, 52 and 54 which are commonly connected to an input line 53 coupled with the second connector 36B of the FPC cable 36 in FIG. 7, and a coder 56 for coding the output signals of the level detectors 50, 52 and 54. The first to third level detectors 50, 52 and 54 detect a voltage level (i.e., amplitude) of an analog signal AMS from the bus compressor 34. A sample AMS signal is shown in FIG. 11. The first level detector 50 generates a low logic of first amplitude detection signal ADl when the analog signal AMS is above a first predetermined voltage level. The second amplitude detection signal AD2 generates a low logic of second amplitude detection signal AD2 when the analog signal AMS is above a second predetermined voltage level. The third amplitude detection signal AD3 generates a low logic of third amplitude detection signal AD3 when the analog signal AMS is above a third predetermined voltage level. The first to third amplitude detection signals ADl to AD3 indicate an amplitude value (or a quantized value) of the analog signal AMS. As a result, the first to third level detectors 50, 52 and 54 serve to quantize the analog signal AMS. The coder 56 codes the amplitude values assigned by the first to third amplitude detection signals ADl to AD3 from the first to third level detectors 50, 52 and 54 into 2 bit data. The low order bit data and the high order bit data coded by the coder 56 are used as the odd-numbered bit data Dn and the even-numbered bit data Dn+l, respectively. The second level detection signal AD2 generated at the second level detector 52 is used as the even-numbered bit data Dn+l. On the other hand, the odd-numbered bit data Dn are generated by logically combining the first to third level detection signals ADl to AD3. To this end, the coder 56 includes first and second AND gates ANDI and AND2, and a negative logic buffer NBl. The odd-


58


numbered and even-numbered bit data Dn and Dn+l reconstructed in this manner are supplied to the second data bus 41 in FIG. 7.”

(Ex. 1004 [Go] at 5:10 – 5:52)


“Multilevel converter 49 as embodied in FIG. 10 illustrates an architecture for a 3-bit multilevel converter. Converter 49 also shows how the basic architecture first described with reference to FIG. 4 may be extended for multiple additional bits through an increase in the number of channels used to perform the comparison, namely, channels 51, 52 and 53, with associated current sources and high speed switches. The basic architecture is particularly unique and valuable in that the comparisons in the various channels 51, 52 and 53 are performed at substantially the same time, and as such cause converter 49 to operate in a manner analogous to a flash converter. The input current iT is a multilevel analog signal now coded to represent three binary bits, characterized in one of eight discrete levels,


59


and by operation of converter 49 generates binary bit equivalents as represented by output bits 1, 2 and 3. The least significant current step shown here is i, where in the previous embodiment the minimum step was i/2. See Table A. The various current sources are created and switched in keeping with the previously described embodiments, where high speed switch 29 is preferably that depicted in FIG. 7. The fundamental architecture of the embodiment in FIG. 10 is extendable to additional bit levels through the use of more channels, and is amenable decimal magnitudes in selectively switched current sources.”

(Ex. 1005 [Beers] at 6:18-42)

(Ex. 1005 [Beers] at 6:43-53)


60




61


Claim: 9

9. The method according to claim 3, wherein said multi-level signal display data is in the form of digital signals with amplitudes equal to one of eight values.

Claim 9 requires “said multi-level signal display data is in the form of digital signals with amplitudes equal to one of eight values.” Claim 8 requires the same limitation but rather than depend from claim 3, claim 8 depends from claim 1. See Claim 8.

Claim: 10

10. The device according to claim 6, wherein said multi-level signal display data is in the form of digital signals with amplitudes equal to one of eight values.

Claim 10 requires “said multi-level signal display data is in the form of digital signals with amplitudes equal to one of eight values.” Claim 8 requires the same limitation but rather than depend from claim 6, claim 8 depends from claim 1. See Claim 8.

Ex. 1009: Invalidity of the ’247 Patent [Ex. 1001] over Go [Ex ......Ex. 1009: Invalidity of the...

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