Evolium BSC Hardware Description

Alcatel-Lucent GSM

9120 BSC Hardware Description

BSC & TC Document

Sub-System Description

Release B10

3BK 21239 AAAA TQZZA Ed.04

Status RELEASED

Short title BSC HW Descr.

All rights reserved. Passing on and copying of this document, useand communication of its contents not permitted without writtenauthorization from Alcatel-Lucent.

BLANK PAGE BREAK

2 / 142 3BK 21239 AAAA TQZZA Ed.04

Contents

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.1 Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141.2 Common Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.2.1 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151.2.2 Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 CPRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.2 CEPK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2.1 Onboard Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.2.2 OBC Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192.2.3 Common RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.2.4 EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.2.5 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.2.6 Inventory EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.2.7 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3 CENK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.3.1 OBCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.3.2 OBCI SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.3.3 Cyclic Redundancy Check and Bit-Flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312.3.4 Cyclic Redundancy Check Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.4 CEBK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342.4.1 Broadcast Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342.4.2 Driver and Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2.5 External Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.5.1 DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.5.2 SCC/SCSI SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.5.3 SCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.5.4 X.25 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.5.5 Man-Machine Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.5.6 Modem Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.5.7 Interface Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.6 Memory Disk Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.7 Memory Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.7.1 CMDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422.7.2 CMFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

2.8 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442.9 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452.10 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

2.10.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.10.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.10.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.11 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3 TCUC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503.2 Abis Logic Cell Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.1 Abis Multirate Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.2.2 Abis Multirate Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523.2.3 Abis Multirate Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.2.4 BIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.3 BSI Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.3.1 Drivers and Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.3.2 Internal Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3BK 21239 AAAA TQZZA Ed.04 3 / 142

Contents

3.3.3 External Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.4 ILC Signaling Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.5 Signaling Link Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.6 Multirate Traffic Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573.7 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583.8 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58



4 DTCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624.2 Trunk Access Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.2.1 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624.2.2 2048 kbit/s PCM Trunk Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634.2.3 4096 kbit/s PCM Link Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.2.4 Clock Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.2.5 OBC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644.2.6 Diagnostic Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3 ILC Signaling Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.3.1 HDLC Formatters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.3.2 Signaling Link Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.3.3 Transmit Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.3.4 Receive Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

4.4 Ater Logic Cell Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.4.1 Ater Multirate Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.4.2 Ater Multirate Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.4.3 Ater Multirate Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

4.5 BSC Clock A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684.6 Signaling Link Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.7 Multirate Traffic Channel Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694.8 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704.9 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70



5 SWCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.1.1 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.1.2 Variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745.1.3 Functional Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.2 Switching Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.2.1 Switching Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.2.2 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775.2.3 Phase-locked Loop Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

5.3 Serial Line Receivers and Line Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.4 Clock Input Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.5 Voltage-controlled Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.6 Power-on Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.7 Clock Buffers and Frame Delay Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785.8 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795.9 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

6 BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826.2 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4 / 142 3BK 21239 AAAA TQZZA Ed.04

Contents

6.2.1 Reference Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.2.2 Phase-locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.2.3 Master Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846.2.4 Output Clock Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.3 Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856.3.1 SYS-BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856.3.2 RACK-BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.4 Broadcast Bus Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856.4.1 SYS-BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856.4.2 RACK-BCLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6.5 Remote Inventory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856.6 DTCC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.6.1 Clock Control Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.6.2 Alarm Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.6.3 Status Change Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.7 External Alarm Scanning and Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.7.1 Alarm Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.7.2 Alarm Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

6.8 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866.8.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876.8.2 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88


7 DC/DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.1.1 Output Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927.1.3 Automatic Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

7.2 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927.2.1 Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927.2.2 Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

7.3 Voltage and Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957.3.1 Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957.3.2 Output Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

7.4 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977.5 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

8 ASMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008.2 Onboard Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018.3 Ater Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

8.3.1 Clock Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018.3.2 HDB3 to NRZ Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018.3.3 Re-timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018.3.4 Frame Alignment Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028.3.5 CRC4 Monitoring and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028.3.6 Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028.3.7 Fault Indications Sent to Remote End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028.3.8 TCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

8.4 Ater Mux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038.5 Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

8.5.1 Sub-rate Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038.5.2 Time Space Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8.6 TS0 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058.7 Serial Communication Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068.8 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078.9 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078.10 Remote Inventory EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

3BK 21239 AAAA TQZZA Ed.04 5 / 142

Contents

8.11 Local Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078.12 Remote Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088.13 Qmux Address Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088.14 Man-Machine Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088.15 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

8.15.1 Onboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088.15.2 TS0 Logic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108.15.3 SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108.15.4 TSSW Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118.15.5 SRS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

8.16 Watchdog Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118.17 Long Range Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118.18 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

8.18.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128.18.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128.18.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

8.19 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

9 BIUA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169.2 Onboard Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179.3 Abis Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

9.3.1 Clock Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179.3.2 HDB3 to NRZ Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179.3.3 Re-timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179.3.4 Frame Alignment Supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1179.3.5 CRC4 Monitoring and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189.3.6 Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189.3.7 Fault Indications Sent to Remote End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189.3.8 TCC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

9.4 BSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1189.5 Sub-rate Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199.6 Time Space Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219.7 TS0 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1219.8 Serial Communication Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239.9 Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239.10 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249.11 Remote Inventory EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249.12 Local Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249.13 Remote Qmux Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249.14 Qmux Address Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249.15 Man-Machine Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259.16 LAPD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259.17 Alarm Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259.18 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

9.18.1 Onboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259.18.2 TS0 Logic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289.18.3 SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289.18.4 TSSW Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289.18.5 SRS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

9.19 Watchdog Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299.20 Long Range Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299.21 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

9.21.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309.21.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309.21.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130


6 / 142 3BK 21239 AAAA TQZZA Ed.04

Contents

10 TSCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13310.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13410.2 Onboard Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13410.3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13510.4 Memory Controller and Register Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13510.5 Serial Communication Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

10.5.1 SCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13610.5.2 SCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13610.5.3 SCC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

10.6 Local Qmux Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13610.7 Remote Qmux Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13710.8 Man-Machine Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13710.9 LAPD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13710.10 Remote Inventory EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13710.11 Watchdog Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13810.12 Long Range Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13810.13 Test Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

10.13.1 Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13810.13.2 Extended Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

10.14 Onboard Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13910.14.1 SCC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13910.14.2 DRAM Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13910.14.3 FLASH EPROM Bank Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13910.14.4 Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14010.14.5 Wait State Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14010.14.6 Parity Location Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14010.14.7 Remote Inventory Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14010.14.8 LED Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

10.15 O&M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14110.15.1 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14110.15.2 Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14110.15.3 Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141


3BK 21239 AAAA TQZZA Ed.04 7 / 142

Figures

FiguresFigure 1: BSC Functional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2: Simplified CPRC PBA Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 3: CEPK Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 4: CENK Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 5: Broadcast Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 6: External Communication Interface Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 7: DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 8: CMDA Simplified Functional Diagram for 3BK 06428 Ax Variant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 9: CMFA Simplified Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 10: CPRC PBA - Main Data Flow Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 11: CPRC Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 12: TCUC PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 13: Abis LCA Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 14: Signaling Termination Data and Control Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 15: Multirate Traffic Switching - Data and Control Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 16: TCUC PBA - Main Data Flow Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 17: TCUC Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 18: DTCC PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 19: Signaling Link Handling - Data and Control Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 20: Ater LCA Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 21: Multirate Traffic Switching - Data and Control Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 22: DTCC PBA - Main Data Flow Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 23: DTCC Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure 24: Switch PBA, AS Variant Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Figure 25: Switch PBA, GS Variant Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Figure 26: SWCH Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Figure 27: SYS-BCLA Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Figure 28: RACK-BCLA Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 29: BCLA Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 30: DC/DC Converter Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 31: ASMB PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 32: Ater Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 33: Clock Selection and Synchronization Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 34: TS0 Logic - Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figure 35: ASMB Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 36: BIUA PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Figure 37: Abis Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Figure 38: BSI Drivers and Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 39: Clock Synchronization Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

8 / 142 3BK 21239 AAAA TQZZA Ed.04

Figures

Figure 40: TS0 Logic - Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Figure 41: BIUA Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

Figure 42: TSCA PBA Simplified Hardware Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Figure 43: TSCA Front Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

3BK 21239 AAAA TQZZA Ed.04 9 / 142

Tables

TablesTable 1: PBA Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 2: PCR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 3: EPCR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 4: TOR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5: NMIR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 6: MREG Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 7: INVR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 8: CBR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 9: MCR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 10: CPR LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 11: TCUC LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 12: DTCC LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 13: DTCC LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 14: BCLA PBA - LED 4 Flashing Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 15: Maximum Output Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 16: Static Regulation Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Table 17: Output Ripple and Noise Peak . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 18: Maximum Output Current - Short-Circuit Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 19: DC/DC Converter LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Table 20: TS0 Logic - Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Table 21: ASMB Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 22: ASMB Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Table 23: RINVR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 24: QAR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 25: ASMB LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

Table 26: TS0 Logic - Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 27: BIUA Clock Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Table 28: BIUA Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Table 29: RINVR Bits BIUA PBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Table 30: QAR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 31: LAPD Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

Table 32: BIUA LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 33: TSCA Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

Table 34: TSCA LED Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10 / 142 3BK 21239 AAAA TQZZA Ed.04

Preface

Preface

Purpose This document describes the hardware of the 9120 BSC.

What’s New In Edition 04Update for new equipment naming.

In Edition 03Overall document quality was improved following a quality review.

In Edition 02Update of system title.

In Edition 01First official release of document.

Audience This document is intended for:

Commissioning personnel

System support engineers

Any other personnel interested in the structure of the BSC hardware.

Assumed Knowledge The reader must have general knowledge of telecommunications systems andterminology, electronics and the BSC functions.

3BK 21239 AAAA TQZZA Ed.04 11 / 142

Preface

12 / 142 3BK 21239 AAAA TQZZA Ed.04

1 Introduction

1 Introduction

This document provides an introduction to the hardware of the functional unitsof the BSC. It also provides information which is common to a number of PBAs.

3BK 21239 AAAA TQZZA Ed.04 13 / 142

1 Introduction

1.1 Functional UnitsThe following figure shows the breakdown of the BSC into functional units. Ascan be seen from the figure, each functional unit comprises one or more PBAs.

TSC Terminal

Clock/BC A

Clock/BC B

8

TCUC1

Abis TSU

DTCC

Ater TSU

OSI−CPRC SYS−CPRC

Common TSU

BC−CPRC

DSN

SWCH

Transcoder Submultiplexer Controller Clock and Alarm System

OMC−R BSC Terminal External Alarms

Qmux bus

BTS BIUA

Active

Standby

Active

Standby

ASMB

TSCA

1−4

5−8

1

n

1

n

1

2

n

1SYS−BCLA

M

S S

M

RACK−BCLA1

1

n

n

MSC

MSC

M : Master

S : Slave

BC : Broadcast

TSU : Terminal Sub-Unit

OSI : Open System Interconnection

SYS : System

Figure 1: BSC Functional Units

Refer to the following sections for more information about the PBAs whichcompose the functional units.

14 / 142 3BK 21239 AAAA TQZZA Ed.04

1 Introduction

1.2 Common InformationThis section describes information which is common to a number of PBAs.

1.2.1 Dimensions

The following table gives the physical dimensions of the PBAs and the numberof PBA slots occupied.

PBA Height DepthWidth (PBASlots)

All except DC/DC Converter 221 mm 254 mm 1.6 mm (1)

DC/DC Converter 221 mm 254 mm 3.2 mm (2)

Table 1: PBA Dimensions

1.2.2 Temperature Range

At altitudes between sea level and 500 meters, the temperature range is + 10Cand 30C. The relative humidity must be within a range from 20% to 80%.

For further information about the environmental characteristics of the BSCequipment, refer to the BSC Cabinet and Subrack Description.

3BK 21239 AAAA TQZZA Ed.04 15 / 142

1 Introduction

16 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2 CPRC

This section describes the hardware architecture of the CPRC PBA.

3BK 21239 AAAA TQZZA Ed.04 17 / 142

2 CPRC

2.1 IntroductionThe following figure shows a simplified diagram of the hardware architectureof the CPRC PBA. Some functions of the CPRC PBA are common to theTCUC and DTCC PBAs.

These functions are the:

CEPK (Control Element Processor Kernel)

CENK (Control Element Network Kernel)

CEBK (Control Element Broadcast Kernel).

Although these functions are common, there are some differences betweenthe functions provided in the CPRC, TCUC and DTCC PBAs. Refer to thecorresponding sections of this document for more information.

Two functional variants exist for the CPRC PBA (see the following sections):

3BK 06428 Ax

3BK 06428 Bx

PCM Links To/From DSN

External Alarms

Remote Inventory

LEDsPush Button

Broadcast Bus

SCSI for 3BK 06428 AxEthernet 10BaseT for 3BK 06428 Bx

X.25 Link

RS−232 Link

CPRC PBA

= Common Parts with other Control Element PBAs

Only the main functions are shown. Ancillary circuits such as the bus control, chip select logic, reset, etc., are not shown.

Control Element Network Kernel

External Communication

Interface

Control Element

Processor Kernel

Control Element

Broadcast Kernel

Memory Disk Interface

Memory Disk

− Code/Data Backup or

− Measurements Data Storage

Digital Switching Network (DSN)Pulse Code Modulation (PCM)

*

* *

*

*

Figure 2: Simplified CPRC PBA Hardware Architecture

There are three main types of CPRC PBA:

SYS-CPRC

OSI-CPRC

Broadcast-CPRC.

Most of the CPRC PBA hardware is the same, irrespective of its type. Themain difference is whether a memory disk is fitted and, if so, what type (seeMemory Disk (Section 2.7)).

18 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.2 CEPKThe following figure shows a simplified functional diagram of the CEPK. TheCEPK includes all the processor-related functions.

External Alarms

Remote Inventory

LEDsPush button

Control Element Processor Kernel


32−bit 32−bit

To/From Other Circuits on PBAOn−Board Controller

Data Buffer

On−Board Controller Peripherals Data Buffer

Common DRAM/SDRAM− Data Storage− Code Storage

FLASH MemoryInventory EEPROM

Control and Status

Registers

EPROM − Program

Storage

Figure 3: CEPK Functional Diagram

2.2.1 Onboard Controller

The heart of the CPRC PBA is the Onboard Controller, which is a 32-bitmicroprocessor operating at 25 MHz.

The OBC has the following integrated features:

32-bit 386DX microprocessor

Very large address range

Memory management unit.

2.2.2 OBC Peripherals

The OBC does not have any integrated peripherals (e.g., timers, interruptcontroller, etc.). Therefore, these are implemented either by discrete logicor as part of an integrated device.

The OBC provides the following devices:

Counter/Timer

Interrupt Controllers

Bus Arbitration Logic.

3BK 21239 AAAA TQZZA Ed.04 19 / 142

2 CPRC

2.2.2.1 Counter/TimerAn integrated counter/timer provides three programmable counter/timers (0, 1and 2). An 8 kHz signal, derived from the network frame pulse, provides theinput clock for the counter/timers.

The three programmable counter/timers are used as follows:

Counter/Timer 0 operates as an Interval Timer and System Timer. It

generates cyclic interrupts under software control, typically at 10 millisecond(ms) intervals.

Counter/Timer 1 operates as a Watchdog Timer (or Sanity Timer)

Counter/Timer 2 operates as a Software Timer. It generates cyclic interrupts

under software control, typically at 2 ms intervals.

2.2.2.2 Interrupt ControllersThe OBC can only receive one interrupt. Therefore, all the interrupt requestsgenerated on the PBA are applied to two programmable interrupt controllers.These controllers are connected in a master/slave configuration. The interruptcontrollers merge the interrupt requests on a priority basis.

2.2.2.3 Bus Arbitration LogicThe bus arbitration logic enables the OBCI (Onboard Controller Interface),BCU (Broadcast Control Unit), SCC (Serial Communication Controller), andthe SCSI controller to operate independently of the OBC. This allows thesedevices to transmit and receive data packets at their own speed, withoutinterrupting the OBC. When the OBC wants to access one of these devicesduring a Direct Memory Access cycle, extra wait states prevent the processorseizing control immediately.

On the TCUC and DTCC PBAs, the bus arbitration logic allows the OBCI, theBCU and the ILC (Integrated Services Digital Network Link Controllers) tooperate independently of the OBC.

2.2.3 Common RAM

2.2.3.1 Case of 3BK 06428 Ax VariantThere are 8 Mbytes of common DRAM connected to a 32-bit data bus. TheDRAM, which is organized as four 16-bit banks, can be addressed in byte, wordor double-word mode. Byte-based parity detection is provided. Programmablelogic controls the DRAM. This logic supports OBC pipeline and interleavedmemory access.

2.2.3.2 Case of 3BK 06428 Bx VariantThere are 16 Mbytes of common SDRAM connected to a 32-bit data bus. TheSDRAM, which is organized as four 16-bit banks can be addressed in byte,word or double-word mode. Programmable logic controls the SDRAM. Thislogic supports OBC pipeline and interleaved memory access.

2.2.4 EPROM

The EPROM stores power-on and autonomous recovery firmware. It has 256kbytes of non-volatile read-only memory organized as 128 kwords.

20 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.2.5 FLASH Memory

The FLASH memory is non-volatile read/erase/write memory based on EPROMtechnology. There are 512 kbytes of FLASH memory organized as a number of16-bit banks of various sizes.

Access is as follows:

Read access to the FLASH memory can be in byte, word or double-word

mode. During an erase or program write sequence, read access is notpossible.

Write access is always in word mode. At the start of a write access, the

software disables the FLASH write protection logic.

2.2.6 Inventory EEPROM

The Inventory EEPROM stores remote inventory information.

The remote inventory information includes items such as:

PBA manufacturing information

PBA identification information

Repair information

Calibration information

PBA history information

Miscellaneous information.

Access to the Inventory EEPROM is via the inventory register (see Control andStatus Registers (Section 2.2.7)).

2.2.7 Control and Status Registers

The control and status registers comprise the:

PCR (Processor Control Register)

EPCR (Extended Processor Control Register)

TOR (Take-Over Register)

NMIR (Non Maskable Interrupt Register)

SRR (Special Reset Register)

SRC (Special Reset Command)

LTEC (Level-to-Edge Converter)

MREG (Miscellaneous Register)

INVR (Inventory Register)

ALR (Alarm Register).

The bits of the control/status registers can be Read-only, Write-only, Read/Writeor Read-only/Write-clear. Access to all the registers can be in byte, word ordouble-word mode.

3BK 21239 AAAA TQZZA Ed.04 21 / 142

2 CPRC

2.2.7.1 Processor Control RegisterThe PCR is a 16-bit register that allows software control of memory andprocessor-related states. Access to the register can be in 8-bit or 16-bit mode.The following table describes the used bits of the PCR.

Bit Name Access Description

PARDIS RW Parity Disable This bit enables the testing of the DRAM and the associated parityerror detection logic. The bit inhibits the writing of the parity code during a writeaccess to the common DRAM. This means that for a write operation, the data fieldin the memory is changed while the parity code field remains unchanged.

For a read operation from the DRAM, the parity disable bit prevents parity errordetection. The OBC reads the unchecked data field. Memory errors are notdetected and an NMI due to memory errors is not generated.

The PARDIS bit is sometimes known as the check inhibit bit.

WDXPTH RW Watchdog Timer Expired Path Select. This bit controls the function of the watchdogtimer. Depending on the state of the bit when the watchdog timer expires, eithera reset signal, or an NMI is generated. A reset signal causes the PBA circuits tobe reset.

LEDs 1 - 3 RW These bits each control one of the three LEDs mounted on the lower part of the frontedge of the PBA. The LEDs provide status indications during diagnostic tests.

LED 4 RW This bit controls a LED mounted on the upper part of the front edge of the PBA. Thismaintenance bit is also known as the Prompt Maintenance Alarm bit. The softwarewrites this bit, which is also activated when the watchdog timer expires. When thewatchdog timer is active, the software cannot write this bit.

When the reset button is pressed, LED 4 toggles. If the button is pressed for morethan two seconds, LED 4 toggles again. This toggling is not reflected by the LED4 bit.

BSCG RO BSC Back panel Generation. These bits define the generation of the BSC backpanel in which the PBA is used. The bits indicate the state of the BSC strappinginput on the back panel.

DSKPR RO Disk Present (not used on the TCUC and DTCC). This bit indicates whether aMemory Disk daughter board is fitted to the PBA.

CEID RO Control Element Identity. This bit indicates the state of the back panel ControlElement identity strap. The bit is 0 for even network addresses and 1 for oddnetwork addresses.

Table 2: PCR Bits

22 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.2.7.2 Extended Processor Control RegisterThe EPCR is a 16-bit register that allows software control of memory andprocessor-related states. Access to the register can be in 8-bit or 16-bit mode.The following table describes the used bits of the EPCR.


SREN RW Special Reset Enable. This bit allows the firmware or software to reset one or moresingle devices. Each device must be programmed in the SRR and the reset isinitiated by writing to the SRC Register.

FWPE RW FLASH Write Protection Enable. This read/write bit enables and disables writecycles to the FLASH memory. When the bit is 0, the write protection hardware isenabled and the FLASH write hardware is disabled. An attempt to write to theFLASH memory results in the generation of an NMI. When the bit is 1, the writeprotection hardware is disabled and the FLASH write hardware is enabled.

FRDY RW FLASH Ready. This bit indicates the status of the FLASH memory. A 1 indicatesthat the memory is ready.

REFALM RO Refresh Alarm. This bit indicates whether or not the refresh counter is operatingcorrectly. 1 indicates correct operation, and 0 indicates a failure of the refreshcounter.

T250US RO Time 250 microseconds (T250US). This bit, which reflects the frame pulse dividedby two, toggles every 125 [mu ]s.

RAPON RO Reset After Power On. This bit indicates whether the PBA was reset as a result ofpower on (1) or for any other reason (0). The bit cannot be reset by the firmwareor software. It can only be reset by the first reset which is not due to a power-oncondition.

Table 3: EPCR Bits

3BK 21239 AAAA TQZZA Ed.04 23 / 142

2 CPRC

2.2.7.3 Take-Over RegisterAn 8-bit register controls the takeover function if the active CPRC fails. Two bitsare read/write and the other six are read-only (only three of these bits are used).

The OBC writes two status bits to the TOR via the peripheral data bus. Onestatus bit is the own-CPRC status; the other is the takeover test status. TheTOR signals the own-CPRC status to the other CPRC.

Each CPRC stores the status of the other CPRC.

The following table describes the used bits of the TOR.


OAVL RW Own Processor Available. This bit controls the status of its own CE processor. Onlythe firmware and software can write to the bit.

PAVL RO Partner Processor Available. This bit indicates the status of the partner CEprocessor. 0 indicates that the partner processor is available. 1 indicates that thepartner processor is not available, e.g., has been pulled out. A transition of this bitfrom 0 to 1 indicates that the partner CE has become inactive.

TOTST RW Take-Over Test. This bit tests the takeover function.

TOINT RO Take-Over Interrupt. This indicates that the other CPRC has become inactive. Inconjunction with the takeover test bit, the bit can also test the takeover function.

PDI RO Power Down Indicator. (not used on the TCUC and DTCC). This read-only bitindicates whether a battery backup unit is equipped, or provides power backup forthe Memory Disk daughter board type CMDA (Common Memory Disk Assembly).The bit is not used when the CPRC is fitted in an BSC.

Table 4: TOR Bits

2.2.7.4 Take-Over Test FunctionA test function checks the operation of the takeover function. The OAVL andTOTST bits control the test function.

A takeover test can be performed with or without interrupts being generated.

Test Without Interrupt The test function performs the following actions (undersoftware control) for a test without interrupt activity:

Sets the TOTST bit to 1 (after a hardware reset, this bit is set to 1)

Resets the OAVL bit to 0

Checks if the TOINT bit is set to 1. The bit remains unchanged until the

OAVL bit is set to 1 again.

Test With Interrupt A takeover test with interrupt activity is similar to a testwithout interrupt activity. However, when the OAVL bit is reset to 0, a maskabletake-over interrupt is generated. The interrupt controller performs maskingof the interrupt. A read of the TOR during a takeover test with interruptactivity does not reset the takeover interrupt. This is done by setting theOAVL bit to 1 again.

24 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.2.7.5 Non-Maskable Interrupt RegisterThe OBC can obtain the source of an NMI by reading the 8-bit NMIR. A writeoperation on the NMIR clears bits 0 to 6, allowing a new NMI to be generated.The following table describes the used bits of the NMIR.


MMPERR RORC Main Memory Parity Error. This indicates that a parity error was detected duringa read operation on the DRAM. The bit is set to 1 (parity error) only if the parity isenabled (see the PARDIS bit of the PCR).

This bit is not used in case of CPRC variant 3BK 06428 Bx.

WDALM RORC Watchdog Alarm. This bit is set if the watchdog timer expires and the NMI pathis enabled (see the ENNMI bit below).

DSKERR RORC Disk Error (not used on the TCUC and DTCC). This bit is set if the hardware detectsan error during a read operation on the memory disk daughter board. Errors includeparity error, backup power failure, etc. The bit can only be set when the NMI isenabled in the memory disk registers.

DSKWPV RORC Disk Write Protection Violation (not used on the TCUC and DTCC). This bit is set ifa write protection violation of the disk memory occurs after a PBA reset.

FWPV RORC FLASH Write Protection Violation. This bit is set if a write protection violation of theFLASH memory occurs.

UPSDN RORC Microprocessor Shutdown. The OBC sets this bit if a processor shutdown occurs.The bit can be set together with the watchdog alarm bit.

PBNMI RORC Push button NMI. This bit indicates that the NMI was generated as a result of thefront panel push button being pressed.

ENNMI RORC Enable NMI. When a 1 is written to this bit, the NMI path is enabled. The NMI pathcannot be disabled until a PBA reset is performed.

Table 5: NMIR Bits

3BK 21239 AAAA TQZZA Ed.04 25 / 142

2 CPRC

2.2.7.6 Special Reset RegisterThe 16-bit SRR allows one or more devices to be reset without resetting thecomplete PBA. The reset function has no effect on the RAPON bit of the EPCR.The SRR programs the devices which are to be reset. A reset is triggered bywriting to the SRC.

On the CPRC, the used SRR bits are:

Special reset OBCI

Special reset SCC

Special reset DMA controllers

Special reset SCSI controllerThis bit is not used in case of CPRC variant 3BK 06428 Bx.

Special reset broadcast hardware.

On the TCUC, the used SRR bits are:

Special reset OBCI

Special reset ILC0

Special reset ILC1

Special reset ILC2

Special reset Abis logic


On the DTCC, the used SRR bits are:

Special reset OBCI

Special reset ILC0

Special reset Trunk Access Circuit

Special reset Ater logic

Special reset BCLA PBA


When one of these RW bits is set to 1, a write to the SRC resets the relateddevice.

2.2.7.7 Special Reset CommandThe SRC resets the devices programmed in the SRR. Provided the SREN bit ofthe EPCR is set, a write operation to any of bits 0 to 7 resets the devices. Thevalue written to the bit does not matter.

Bit 0 of the register indicates whether the SRC is active or not.

26 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.2.7.8 Level-To-Edge ConverterThe interrupt controllers are initialized in the edge mode. The OBCI and theBCU, however, operate in the level mode. The LTEC register generates aspecial end of interrupt at the end of the OBCI and BCU interrupt routines. Thisinterrupt clears the level-to-edge flip-flop.

The used LTEC bits are:

LTEC for OBCI interrupt

LTEC for BCU interrupt

LTEC for ILC interrupts (only DTCC and TUCC).

Writing a one-to-one of these write-only bits clears the OBCI converter or BCUconverter flip-flop as appropriate.

2.2.7.9 Miscellaneous RegisterThe MREG monitors and controls various functions of the DTCC PBA. Theregister is not provided on the CPRC and TCUC PBAs. The following tabledescribes the used bits of the MREG.


BPE RW BCLA Interface Parity Error. When set, this bit indicates that the BCLA PBAInterface has detected a parity error. Writing a zero to the bit resets it. It can only bereset in this way.

ATERLCA RO Ater LCA. When set, this indicates that the Ater LCA is present.

ILCSLP RW ILC Loop. If this bit is set, the outputs of the ILC are looped back to its inputs.

ELPR RO External Loop Plug Present. When this bit is set, it indicates that the trunk loop plugis present on the back panel.

TAVL RW Trunk Available. This bit is set by the software/firmware to indicate the status of thetrunk. Setting the bit enables the extracted clock output driver.

FCLK RW Force Clock. This bit is used for test purposes. It enables the extracted clock outputdriver irrespective of whether there are trunk alarms or the TAVL bit is set.

Table 6: MREG Bits

3BK 21239 AAAA TQZZA Ed.04 27 / 142

2 CPRC

2.2.7.10 Inventory RegisterThe INVR controls access to the Inventory EEPROM. The following tabledescribes the bits of the INVR.


SK RW EEPROM Clock Signal. This bit drives the clock signal of the Inventory EEPROM.The firmware/software toggles the bit from 0 to 1 to enable the EEPROM clock input.

CS RW EEPROM Chip Select. This bit enables the Inventory EEPROM when it is set (1).

DI RW EEPROM Data Input. This bit enables the Inventory EEPROM data inputs.

DO RO EEPROM Data Output. This bit enables the Inventory EEPROM data outputs.

PRE RW Protected Register Enable. This bit enables the protected register when it is set (1).

IAE RO Inventory EEPROM Indication Access Enabled. This bit indicates whether the OBCcan access the Inventory EEPROM.

Table 7: INVR Bits

2.2.7.11 Alarm RegisterAn 8-bit read-only register stores external alarm events.

2.3 CENKThe following figure shows a simplified functional diagram of the CENK. TheCENK includes all the network related functions.



16−bit

To/From Other Circuits on PBA


Static Random Access Memory (SRAM)

OBCI SRAM−DMA

On−Board Controller

Data Buffer

Cyclic Redundancy

Check Registers

On−Board Controller Interface

Cyclic Redundancy Check and

Bit−Flip

Figure 4: CENK Functional Diagram

28 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.3.1 OBCI

The OBCI provides a control and transmission interface between the terminals.

2.3.1.1 SwitchingThe main task of the OBCI is to switch incoming channels from one port, tooutgoing channels. The outgoing channel can be on the same or another port.The switching of ports is transparent. The OBC controls the OBCI.

The OBCI switches paths from the terminals to the OBC and vice versa.It does this by receiving, executing and transmitting packets in a series ofcommands. This sets up a link in both directions between one of the port’schannels and the OBC. The OBCI also obtains and alters read and writeOBCI internal information.

2.3.1.2 LoopbackThe loopback facility allows the OBCI to switch any incoming channel to anyoutgoing channel of any port. In addition, the OBCI supports temporary linksvia the command register.

2.3.1.3 Scratch Pad MemoryThe RAM scratch pad memory connects the channels to each other. Thememory stores the incoming data from the input channels and writes it tothe output channels.

2.3.1.4 CommandsWhen commands are received, the OBCI connects its command register toa channel. The OBCI interprets the channel contents as a command andexecutes the required actions.

One-word commands initiate the OBCI tasks. The commands are assembledinto packets and usually appear in the following order:

1. OBCI select-frame command.

2. Task commands to set up or unassign a path.

3. Task commands to read or write a register.

4. OBCI deselect-frame command.

The frame commands inform the OBCI that all successive words arecommands, or terminate the work.

3BK 21239 AAAA TQZZA Ed.04 29 / 142

2 CPRC

2.3.1.5 Control and Status RegistersThe OBCI uses numerous control and status registers to achieve these tasks.The OBCI has four main parts:

Serial Interface Ports

Interface for the OBC

Switch

Clock and Synchronization Circuit.

Serial Interface Ports Ports 2 and 3 connect to the DSN (Digital SwitchingNetwork) via two independently-operating duplex PCM (Pulse CodeModulation) links.

Each PCM link operates at 4 Mbit/s and carries 32 channels. Port 4 is providedfor the auxiliary links, which connect the PBA to the OMC-R or the BSCTerminal (only the CPRC). Each auxiliary link transmits one channel per frameat a rate of 64 kbit/s or 128 kbit/s.

Interface for the OBC The interface is connected to port 4. This is wherethe serial bit stream, to and from a channel of the OBCI, is converted intoparallel input and output.

The mechanism for transferring data between the OBCI and the OBC is basedon DMA operations. The DMA works in cycle-stealing mode. This means thatduring the transfer, the OBC is put in the hold state. The OBC suspends itsnormal operation and relinquishes control of the data and address bus. TheOBC acknowledges the hold. From now on, the data and address bus is underthe control of the OBCI. Memory transfer without OBC intervention is nowenabled to and from the common SRAM.

Termination of the DMA transfer is performed when the DMA controlling partdetects the End Of Packet. The OBCI generates an interrupt for the OBC. TheOBC is informed that data has been received or that output data has beentransmitted.

Up to eight DMA transfers in both directions can be made in one frame.

30 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

Switch

The switch connects the serial ports with each other or the OBC via the OBCI.It comprises:

A scratch pad memory

Command and status registers

A logic part.

The switch detects packets from the switch links or the OBC. It switches thelinks and sends packets to the OBC or the switch.

The OBCI continuously scans all channels for a select command. When theOBCI detects such a command, it assigns one of the five available commandregisters to the incoming channel. The OBCI unassigns the command registerwhen it detects an unassign command.

There are six categories of OBCI commands:

Frame commands direct the packet to the right destination address

Assignment commands join and release an incoming and outgoing channel

Read/write commands read from, and write to, registers and memory

Transfer commands send data to, or receive data from, the OBC

Copy commands manipulate temporary register addresses and content

Miscellaneous commands without operation.

Clock and Synchronization Circuit

This circuit generates the timing signals for the OBCI.

2.3.2 OBCI SRAM

The 256 kbytes of SRAM are word organized. On the CPRC PBA, the OBCIuses 64 kbytes of SRAM for DMA transfers. The SRAM is always enabledfor DMA access. The BCU shares the same memory. The firmware andsoftware use 192 kbytes.

On the TCUC and DTCC PBAs, the OBCI uses 64 kbytes during DMAtransfers. The ILCs use 192 kbytes during memory transfers (the BCU sharesthis memory).

2.3.3 Cyclic Redundancy Check and Bit-Flip

2.3.3.1 Cyclic Redundancy CheckThe Cyclic Redundancy Check circuit detects transmission errors in thereceived serial data streams. To allow detection of errors, at the transmitter, thebit stream is divided by a constant bit pattern. The CRC word is the result of thedivision and is added to the data stream. When the CRC circuit receives thedata stream, it makes another CRC check. If no errors have occurred, this CRCword is the same as that received in the bit stream. The CRC circuit stores theCRC result in the CRC Result Register.

3BK 21239 AAAA TQZZA Ed.04 31 / 142

2 CPRC

2.3.3.2 Bit-FlipThe Bit-Flip circuit modifies the order of the data bits sent between the OBCand the RAM to allow channel 16 to be used. In channel 16, bits 0 to 4 and Dof the channel word are assigned to Negative Acknowledgement data. Thismeans that they cannot transfer data as in the 30 other channels. The Bit-Flipfacility means that different software handling is not needed for the data onthe other channels.

During CRC and/or bit-flip operations, the Bit-Flip circuit performs byte to word,or word to byte, format conversion.

The CRC and Bit-Flip Register controls the CRC and Bit-Flip circuits.

2.3.4 Cyclic Redundancy Check Registers

There are two CRC registers:

CBR

CRCRR.

32 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.3.4.1 CRC and Bit-Flip RegisterThe CBR controls the CRC and bit-flip functions. The following table describesthe used bits of the CBR.


BITEN RW Bit-Flip Enable. When set to 1, this bit enables the bit-flip function.

CRCEN RW CRC Enable. When the bit-flip function is enabled, this bit is automatically set toenable CRC generation. When the bit is set, only accesses to and from the OBCISRAM are affected.

IAB RW Interrupt Active Bit. When this bit is set to 1, the CRC and bit-flip functions aresuspended (if they are active). When the bit is set to 0, the CRC and bit-flip functionsare resumed (provided they were originally active when the bit was set to 1).

D_Bit RW D_Bit (NACK of channel 16). This is the NACK validation bit for channel 16. The bitis automatically added to the word written into the OBCI SRAM when the followingconditions are met:

The BITEN or CRCEN bit is set to 1

A transmit packet is being moved from the DRAM or SRAM to the OBCI SRAM.

If these conditions are not met, and the bit is set, the OBCI SRAM operations arenot affected.

Protocolbits

RW Protocol bits (E_bit and F_bit). These protocol bits are automatically added to theword written into the SRAM when the following conditions are met:

The BITEN or CRCEN bit is set to 1

A transmit packet is being moved from the DRAM or SRAM to the OBCI SRAM.

If these conditions are not met, and the bit is set, the OBCI SRAM operations arenot affected.

PRCRC RW Preset CRC Register. A set (1) / reset (0) sequence of this bit initializes the CRCRRfor a new CRC calculation.

Table 8: CBR Bits

2.3.4.2 CRC Result RegisterThe 16-bit CRCRR stores the results of the CRC calculations.

3BK 21239 AAAA TQZZA Ed.04 33 / 142

2 CPRC

2.4 CEBKThe following figure shows a simplified functional diagram of the CEBK. TheCEBK includes all the broadcast-related functions.

Control Element Broadcast Kernel



Driver

Receiver

Receiver

Broadcast BusA B

On−board Controller

Broadcast Control Unit

Receive

Transmit

Bus A

Bus B

Figure 5: Broadcast Hardware Architecture

2.4.1 Broadcast Control Unit

The BCU is an FPCA (Field-Programmable Gate Array) chip which providesa fast paging mechanism. It can also be used to download software anddata to the CEs of the BSC.

2.4.2 Driver and Receivers

2.4.2.1 Broadcast BusA driver and two receivers connect the BCU to the broadcast bus. This buscomprises one transmit link and two receive serial links. The broadcast bususes a type of High Level Data Link Control protocol. This protocol is bitoriented and code independent.

2.4.2.2 Transmit LinkOn the transmit link, the BCU performs:

Flag generation

Bit stuffing

DMA under-run detection

Abort (and idle) sequence generation

CRC generation.

The transmit link is not used on the TCUC and DTCC.

34 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.4.2.3 Receive LinksOn the receive links, the BCU performs:

Abort (and idle) detection

Flag detection

Bit de-stuffing

CRC checking

DMA overrun detection.

Under software or hardware control, the BCU selects one of the receive links.

2.4.2.4 DMA ChannelsThe BCU has four receive DMA channels. The first byte of a frame containsthe station address. The BCU uses this as a pointer to a lookup table. If thebit accessed in this table is set, the BCU accepts the frame. If the bit is notset, the BCU discards the frame.

The BCU transfers accepted frames received on the selected link to memoryusing DMA transfers. If the length of a frame exceeds a predefined threshold,the BCU discards it. The BCU then reports a frame too long error to thesoftware.

The BCU has two transmit DMA channels. From a software point of view, atransmit DMA channel is identified by:

A 20-bit byte pointer

A 16-bit message length counter.

The BCU scans both channels. When the software activates a transmitchannel, the BCU starts transmitting the message on that channel. When theframe has been transmitted, the BCU starts to transmit the frame on the othertransmit channel (if it is active). The BCU reports under-run errors to thesoftware. To reduce the probability of under-run, the BCU has an 8-byte firstin-first out register.

3BK 21239 AAAA TQZZA Ed.04 35 / 142

2 CPRC

2.4.2.5 OBC Interface RegistersThe interface with the OBC comprises a set of registers:

A Broadcast Control Register

An Event Register

A Channel Status Register

A Broadcast Bus Status Register

A Bus Quality Register

16 Station Address Registers

Eight Transmit DMA Descriptor Registers

13 Receive DMA Descriptor Registers.

All the registers are word-oriented. The BCU generates a level type interruptwhen:

A frame is transmitted

A frame is received

The Received Frame Counter or the CRC Error Counter reaches itsmaximum count.

The OBC polls other error and status information.

2.5 External Communication InterfaceThe following figure shows a simplified functional diagram of the ExternalCommunication Interface. This interface provides for all external communicationto the BSC, other than for telecommunication purposes.

External Communications Interface


16−bit


Serial Communication

Controller

X.25 Interface

Man−Machine Interface

X.25 Link

RS−232 Link

SCSI Linkfor 3BK 06428 Ax

SCC/SCSI SRAM−DMA−BC Functions


Data Buffer

DMA Controllers

SCSI

Ethernet

Modem Control Register 10 BaseT

Ethernetfor 3BK 06428 Bx

Figure 6: External Communication Interface Functional Diagram

36 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.5.1 DMA Controllers

Four devices perform DMA transfers:

OBCI

SCC

SCSI controller

BCU.

The OBCI and the BCU have built-in DMA controllers. A DMA controller isprovided for the SCC and the SCSI controller.

This controller can operate in three modes:

Single transfer

Block transfer

Demand transfer.

As shown in the following figure, the DMA controller comprises two externalDMA controllers connected in cascade. The controllers transfer data betweenthe SCC, SCSI controller and the SCC/SCSI SRAM.

DMA Controller 1

Ch0

Ch1

Ch2

Ch3

DMA Controller 2

Ch0

Ch1

Ch2

Ch3

SCC B TX

SCC B RX

Not used

Not used

To/From Control Logic

SCC A TX

SCC A RX

SCSI Controller

Figure 7: DMA Controllers

The DMA controllers can only handle 64 kbytes of memory. External DMApage registers extend this range to 256 kbytes. A page register is provided foreach used DMA channel.

The SCC transmit channels have DMA request flip flops. These flip flops allowthe DMA controllers to be connected to the SCC. During DMA operations,the hardware clears the flip flops.

3BK 21239 AAAA TQZZA Ed.04 37 / 142

2 CPRC

2.5.2 SCC/SCSI SRAM

The DMA controllers use this 256 kbyte SRAM to transfer data to and fromthe SCC and the SCSI interface. The BCU shares the SRAM, which is wordorganized.

2.5.3 SCC

The SCC provides an X.25 connection and a serial RS-232 interface for aman-machine terminal (the BSC Terminal). The X.25 connection can be tothe OMC-R or to the BSC Terminal, depending on whether the PBA is usedas an S-CPRC or an OSI-CPRC.

The SCC is a dual channel, multi-protocol data communication controller. Itfunctions as a serial-to-parallel and as a parallel-to-serial converter/controller.

Two independent full-duplex channels can be programmed for use in:

Common synchronous communication

Asynchronous data communication.

2.5.3.1 LinksThe two links are:

Channel A, a full duplex X.25 link with synchronous data transfer (DMA

mode) which can be used for:

Low-speed mode (9600 bit/s) using a V.28 interface

High-speed mode (64 kbit/s) using an X.21 interface

Connection to the AUX1 port of the OBCI.

Channel B, can be used for:

A full duplex MMI link with asynchronous data transfer (interrupt vectormode)

A full duplex X.25 link (relay function) (DMA mode) connected to theAUX2 port of the OBCI.

2.5.3.2 Interrupt Vector ModeIn the interrupt vector mode, when the SCC generates an OBC interrupt, italso delivers a valid interrupt vector in response to two back-to-back cyclesoriginated by the OBC.

2.5.3.3 DMA ModeIn the DMA mode, when the SCC has data to transfer it sends a request to theDMA controller (see DMA Controllers (Section 2.5.1)). The DMA controllerthen performs the transfer. At the end of the transfer, the DMA controllergenerates an interrupt.

38 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.5.4 X.25 Interface

The X.25 Interface comprises a number of receivers and drivers. The X.25Interface connects to a 25-pin female connector mounted on the front ofthe PBA.

The interface can operate in the following modes:

Low-speed mode with synchronous transmission (up to 9600 bit/s)

High-speed mode according to X.21 circuits (up to 64 kbit/s).

2.5.4.1 Low-Speed ModeIn low-speed mode, a V.24/V.28 modem or a null-modem X.25 terminal canbe connected to the CPRC PBA.

2.5.4.2 High-Speed ModeIn high-speed mode, a high-speed modem using X.21 circuits can be connectedto the CPRC PBA.

2.5.5 Man-Machine Interface

The MMI comprises a number of receivers and drivers that connect the BSCTerminal via the RS-232 interface.

The MMI connects to a 9-pin female connector on the front of the PBA.

3BK 21239 AAAA TQZZA Ed.04 39 / 142

2 CPRC

2.5.6 Modem Control Register

The 16-bit MCR controls and scans the status of the X.25 link and the MMI.The lower byte relates to SCC channel A and the upper byte relates to SCCchannel B. The following table describes the used bits of the lower byte.


X.25DTR RW X.25 Data Terminal Ready (X.25DTR). This bit controls the Data Terminal Readysignal of the DCE (Data Control Equipment). This is connected to a connector onthe front of the PBA. When a modem is connected, the signal is also known asconnect Data Set to Line Circuit.

MODCLP RW Modem Local Loopback. This bit controls the Local Loopback (loop 3) signal of theDCE. The bit is only used in low-speed mode when a modem is equipped.

MODRML RW Modem Remote Loopback. This bit provides firmware and software compatibilitywith earlier versions of the CPRC PBA. The bit is not used by the hardware, so ithas no impact on the CPRC PBA.

OBCISEL RW OBCI Select. This bit controls the SCC channel A connection so that the SCCX.25 port is connected to:

The front connector (for connection to a modem or an X.25 terminal)

Auxiliary port 1 of the OBCI.

X.25DSR RO X.25 Data Set Ready (X.25DSR). In low-speed mode, this bit indicates the presenceof a DCE (X.25 link or modem) which is ready to operate. In high-speed mode, thebit indicates the state of the X.25DTR signal.

MODTST RO Modem Test Indicator. In low-speed mode, this bit signals a maintenance condition.This can be either a local loopback or a remote loopback. The signal is only effectiveif a modem is equipped. The bit is not used in high-speed mode.

MMIDSR RO MMI Data Set Ready. This bit relates to SCC channel B. It is only provided forfirmware and software compatibility with earlier versions of the CPRC PBA.

X.21/V.28 RO X.21/V.28. This bit selects the X.25 front connector type/interface mode. When thebit is 1, the X.25 Interface mode is selected. When the bit is 0, the V.28 interfacemode is selected.

Table 9: MCR Bits

The used bits of the upper byte are:

Interface Selection

MMI DSR.

2.5.6.1 I/F SELThis RW bit controls the connection made to the B channel of the SCC. Whenthe bit is set to 1, the channel is connected to Auxiliary port 2 of the OBCI.When the bit is set to 0, the channel is connected to the MMI 9-pin connectoron the front of the PBA.

40 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.5.6.2 MMIDSRThis RO bit indicates the state of the Data Set Ready circuit of the MMI link.The signal indicates that the terminal is ready to operate. If a terminal isnot connected, the bit is set to 0.

2.5.7 Interface Controller

2.5.7.1 SCSI Controller for 3BK 06428 Ax VariantThe SCSI controller allows either the:

Memory of the CPRC PBA to be extended (by external devices), or

Fast loading of the CPRC memory.

Connection to the SCSI controller is via the back panel. The controller operatesin both the target and initiator modes.

The main functions of the SCSI controller are to:

Provide an SCSI interface with a minimum DMA transfer rate of 1 Mbytes/s

Generate parity bits on the SCSI and provide optional checking of these bits

Support the bus arbitration function

Directly control the bus signals

Provide high current outputs to allow direct driving.

2.5.7.2 Ethernet Controller for 3BK 06428 Bx VariantThe Ethernet controller provides an Ethernet interface at 10 Mbps link rate.

2.6 Memory Disk InterfaceThe memory disk interface allows additional memory (on a daughter board)to be added to the CPRC PBA. All the address, data and control signals areconnected to the daughter board (known as the memory disk) via this interface.

2.7 Memory DiskThere are two types of daughter board which can be added to extend thememory of the CPRC PBA.

These are the:

CMDA, which is used on the OSI-CPRC functional variant 3BK 06428 Ax

CMFA (Common Memory Flash Disk A), which is used on the S-CPRC.

On the CPRC functional variant 3BK 06428 Bx the CMDA is integrated inSDRAM.

The BC-CPRC does not have a memory daughter board.

3BK 21239 AAAA TQZZA Ed.04 41 / 142

2 CPRC

2.7.1 CMDA

The following figure shows the simplified functional diagram of the CMDAdaughter board. This provides an additional 32 Mbytes of DRAM for thebackup storage of code and data.

For the functional variant 3BK 06428 Bx the CMDA function is integratedin onboard SDRAM.

Direction and Tri−state Control

Logic

5V (from CPRC)

CPRC Buses

Control Signals

Data

Data and Parity

Address and Byte Enable

To other circuits

Parity Bus

DRAM Control Signals

Data Bus

Power Down Indicator

DRAM Banks

CPRCSupplyMonitor

CPRC DataTransceivers

DRAM DataTransceivers

Address Latches and Multipexers

CMDA Logic Cell

Array

Buffers

Figure 8: CMDA Simplified Functional Diagram for 3BK 06428 Ax Variant

The DRAMs are organized in eight 4-Mbyte blocks, each with an additionalparity DRAM block.

42 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

Functions performed by the CMDA include:

Memory write in byte or word mode. This includes the generation of one or

two parity bits, if parity write is enabled. The parity bit is written into theparity DRAM

Memory read in byte or word mode, including parity checking. If parity

checking is enabled and an error is detected, the CMDA sends an NMIinterrupt to the OBC

Write protection of the complete memory range. If an attempt is made to

write to protected memory, the write protection circuit generates an NMI

Generation of all the DRAM control signals, e.g., write enable, output

enable, etc.

Power down detection

Status monitoring

Last accessed address storage. If a write protection violation or parity error

occurs, the address of the access which caused the problem is frozen.

The address remains unchanged until all the control registers have beenread by the OBC.

The CMDA Logic Cell Array performs most of the memory control functions.

2.7.2 CMFA

The following figure shows a simplified functional diagram of the CMFAdaughter board. The CMFA provides 124 Mbytes of FLASH memory and 4Mbytes of SRAM for the storage of measurements data. The memory isorganized as eight 16-Mbyte banks. Six of the banks have eight FLASHdevices, each with 2 Mbytes of storage. The other two banks have 2 Mbytes ofSRAM and 14 Mbytes of FLASH memory.

Lithium Battery

Battery Supervision

5V Supply (from CPRC)

CPRC Buses

Backup Supply

Data

Data

Address

Address

Memory Banks

To other circuits

Control Logic

Transceiver

FLASH (124 Mbyte)

Isolation Buffers

SRAM (4 Mbyte)

Buffer

Figure 9: CMFA Simplified Functional Diagram

3BK 21239 AAAA TQZZA Ed.04 43 / 142

2 CPRC

2.7.2.1 Memory Control LogicThe memory control logic comprises two status registers and an identificationregister. The status registers store the ready/busy states of the FLASH devices.The OBC use these states to control access to the devices.

The hard-wired identification register stores the size of the disk and anindication that it has FLASH and SRAM devices.

2.7.2.2 Battery SupervisionThe battery supervision circuit constantly monitors the power supply from theCPRC PBA. If the supply voltage decreases below 4.65 V, a lithium batterysupplies standby power to the SRAM devices. The battery is connected tothe battery supervision circuit via the back panel.

The normal output of the lithium battery is 3.6V. The supervision circuitmonitors the voltage and sets an alarm bit in a status register if it decreases toless than 2V. This allows the OBC to generate an alarm to indicate that thebattery must be replaced.

Danger of explosion if battery is incorrectly replacedReplace only with the same or equivalent type as recommended by themanufacturer.Dispose of the used batteries according to the manufacturer’s instructions.

2.8 Reset CircuitThe reset circuit resets the OBC, OBCI, BSR, MCR and PCR:

During power-up

When the supply voltage decreases below the nominal value

When the front panel push button is pressed

When an external reset is received

When the watchdog timer expires.

44 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.9 Data FlowThe following figure shows the main data flow paths of the CPRC PBA.

MMI MUX

MUX

AUX2

AUX1

OBCI

SCSI Interfacefor 3BK 06428 Ax

Broadcast Interface

X,25

Cable

A

B

To/From DSN

OBC Memory

OBC

Ch A Ch B

SCC

SCSI

BCU

15 pin

25 pin

9 pin

EthernetEthernetInterfacefor 3BK 06428 Bx

Figure 10: CPRC PBA - Main Data Flow Paths

2.10 O&MThis section describes the O&M facilities provided on the CPRC.

It comprises:

LEDs

Push button

Replacement.

3BK 21239 AAAA TQZZA Ed.04 45 / 142

2 CPRC

2.10.1 LEDs

As previously stated, there are four LEDs mounted on the front panel. Thefollowing table describes the functions of the LEDs.

LED Description

4 Indicates a Prompt Maintenance Alarm and is lit when:

An NMI is generated

A watchdog timeout occurs

A PMA is generated.

3 Indicates a service alarm when lit.

1 and 2 When Flashing (normal condition), indicate that the OBC isactive.

Table 10: CPR LED Description

2.10.2 Push Button

The push button on the front edge of the PBA generates either a reset or anNMI, depending on the period for which it is pressed. If the push button ispressed for less than two seconds, a reset signal is generated. If the pushbutton is pressed for longer than two seconds, an NMI is generated.

When the push button is pressed, the top LED (LED 4) toggles to the oppositestate, e.g., if it was off, it is lit. After two seconds, the LED toggles again. Whenthe push button is released, the reset or an NMI is generated.

2.10.3 Replacement

Hot insertion circuits allow the PBA to be inserted into, or removed from, theback panel with the power still on.

These circuits ensure that:

The hardware of the PBA is not damaged

Power drops do not occur on the other PBAs.

46 / 142 3BK 21239 AAAA TQZZA Ed.04

2 CPRC

2.11 Physical DescriptionDimensions

Refer to Common Information (Section 1.2) .

Power Supply

The CPRC operates from a +5 V +/-5% supply.

Front Panel

The following figure shows the front panel layout.

Turn−button Latch

Turn−button Latch

LED 1 (Red)

LED 2 (Red)

LED 3 (Red)

LED 4 (Red)

Push button

9−pin Connector (MMI)

25−pin Connector (X.25 Interface)

PBA Identifying Label

Turn−button Latch

Turn−button Latch

LED 1 (Red)

LED 2 (Red)

LED 3 (Red)

LED 4 (Red)

Push button

9−pin Connector (MMI)

25−pin Connector (X.25 Interface)


RJ−45 Connector (Ethernet)

CPRC Variant 3BK 06428 Ax CPRC Variant 3BK 06428 Bx

Figure 11: CPRC Front Panel

3BK 21239 AAAA TQZZA Ed.04 47 / 142

2 CPRC

48 / 142 3BK 21239 AAAA TQZZA Ed.04

3 TCUC

3 TCUC

This section describes the hardware architecture of the TCUC PBA.

3BK 21239 AAAA TQZZA Ed.04 49 / 142

3 TCUC

3.1 IntroductionThe following figure shows a simplified diagram of the hardware architecture ofthe TCUC PBA. The CEPK, CENK and CEBK are similar to those of the CPRC.For more information about their functions, refer to CPRC (Section 2)).


External Alarms

Remote Inventory

Light Emitting Diodes

Push Button

Broadcast Bus

TCUC PBA



2 Mbit/s PCM Links To/From the Base Station Interface and the Abis Interface

Control Element

Broadcast Kernel


Control Element

Processor Kernel

Base Station Interface Buffers

Abis Logic Cell Array

ILC Signalling Handling

*

*

*

*

Figure 12: TCUC PBA Simplified Hardware Architecture

3.2 Abis Logic Cell ArrayThe following figure shows a simplified functional diagram of the Abis LCA(Logic Cell Array).

The LCA is an FPGA which is involved in two main functions performed bythe TCUC PBA:

Termination of the signaling links

Multirate switching of the traffic channels.

Base Station Interface Registers

Multirate Switch

Abis LCA

Signalling Link Multiplexer and Pulse Absence

Detector

Signalling Link Multiplexer

ILC1Switch

To/from Base Station Interface Buffers

To on−board loop circuit

From OBC

To/from OBCI

To/fromILC0 and

ILC2

To/from ILC1

Figure 13: Abis LCA Functional Diagram

50 / 142 3BK 21239 AAAA TQZZA Ed.04

3 TCUC

As shown in the figure above, the Abis LCA comprises:

An SLM (Signaling Link Multiplexer) and Pulse Absence DetectorThis provides the interface with the BSI and multiplexes the signals tothe Multirate Switch and the ILCs. It also monitors the status of the linkswith the BSI.

A Multirate SwitchThis performs the multirate switching of the traffic channels. It also performsframe re-timing and resynchronization of the clock signals.

An SLMThis provides the interface with the OBCI. It also multiplexes the signal fromthe DSN to the Multirate switch and the ILC1 switch.

An ILC1 switchThis connects ILC1 to BSI-A, BSI-B or the DSN (via the OBCI), as required.

BSI Registers.These allow the OBC to control the Abis LCA and monitor the operations ofthe BS Interfaces.

The registers include the:

Abis Multirate Registers 0, 1 and 2

BSI Register.

The AMBR and BIR are 16-bit registers. The bits of the registers can beread-only, read/write or read-only with clear. The registers can be written andread together in word access, or low and high byte separately in byte access.

For more information about the bits, refer to:

Abis Multirate Register 0 (Section 3.2.1)

Abis Multirate Register 2 (Section 3.2.3)

BIR (Section 3.2.4).

3.2.1 Abis Multirate Register 0

The used bits of the ABMR0 are as follows:

Channel block 1 - quadruple-rate Traffic Channel (TCH) 0

Channel block 1 - quadruple-rate TCH 1


Channel block 3 - quadruple-rate TCH 1.

Quadruple-rate TCH

This is a read/write Channel Block n- Quadruple-rate TCH n bit that allows a 64kbit/s TCH to be allocated to a channel block. For example, the Channel block1 - quadruple-rate TCH 0 bit allows TCH 0 to be allocated to channel block 1.

3BK 21239 AAAA TQZZA Ed.04 51 / 142

3 TCUC



Channel block 1 - double-rate TCH 0








Mode select bit 0

Mode select bit 1

Submode select bit 0

Submode select bit 1

SPC (Semi-Permanent Connection) selection.

3.2.2.1 Double-rate TCHThe read/write Channel Block n - Double-rate TCH n bits allow the 32 kbit/sTCH to be allocated to the appropriate channel block.

3.2.2.2 Mode SelectThe read/write mode select bits configure the operating mode of the multirateswitch, e.g., mode 3.

3.2.2.3 Submode SelectThe read/write submode select bits configure the operating mode (thesubmode, e.g., 1) of the multirate switch, when mode 3 is selected.

3.2.2.4 SPC SelectionWhen the read/write SPC selection bit is set to 1, it enables transparentswitching of eight 64 kbit/s channels (per BSI) through the multirate switch. Thisoverrides other switching arrangements in the involved time slots (TSs).

52 / 142 3BK 21239 AAAA TQZZA Ed.04

3 TCUC



Channel block 1 - full-rate TCH 0








Channel block 2 or 3 - full-rate TCH 0







Channel block 2 or 3 - full-rate TCH 7.

Full-rate TCH The read/write full-rate TCH n bits allow a full-rate TCH to beallocated to channel block 1.

3.2.4 BIR

The used bits of the BIR are:

ILC1 switch select bit 0

ILC1 switch select bit 1

Internal loop selection

External loop present

Pulse absence detect on frame of BSI-A

Pulse absence detect on clock of BSI-A

Pulse absence detect on frame of BSI-B

Pulse absence detect on clock of BSI-B.

3.2.4.1 ILC1 Switch SelectThe read/write ILC1 switch select bits select the 2 Mbit/s link which is to beterminated by ILC1.

3BK 21239 AAAA TQZZA Ed.04 53 / 142

3 TCUC

3.2.4.2 Internal Loop SelectionThe read/write internal loop selection bit controls the internal looping of boththe BSIs at the same time (see BSI Buffers (Section 3.3)). In switching mode2, signaling packets sent by ILC1 to a BSI-B can be looped back to the inputof ILC1. During loopback, the BSI receivers and drivers are set to the highimpedance state.

3.2.4.3 External Loop PresentThe read-only external loop present is set when an external loop is connected(see BSI Buffers (Section 3.3)).

3.2.4.4 Pulse Absence DetectThe pulse absence detect bits on the clock (or frame) of BSI-A (or BSI-B)indicate the absence of either the:

4 MHz clock or

8 kHz frame signal.

The bits remain set until they are written to with a 0, provided the relatedsignal is no longer absent.

3.3 BSI Buffers

3.3.1 Drivers and Receivers

A number of drivers and receivers connect the PCM links to and from the BSI.

3.3.2 Internal Loopback

An internal loopback test facility tests the BSIs of the TCUC by allowing trafficto be sent back to the OBCI and the ILCs. For example, traffic sent from theoutput of the OBCI in TS0 is looped back to the input of the OBCI in the sameTS. The OBC controls the internal loopback facility via the BIR. The loopback isperformed at the inputs and outputs of the Abis LCA. In addition, the frame andclock outputs of the OBCI are looped to the frame and clock inputs of the AbisLCA. This means that the drivers and receivers are not tested.

3.3.3 External Loopback

A loopback plug or cable connected to the back panel in which the PBA isinserted allows the TCUC to perform an external loopback. In this case, the BSIcable is disconnected. The external loopback facility is the same as the internalloopback except that it tests the BSI drivers and receivers.

54 / 142 3BK 21239 AAAA TQZZA Ed.04

3 TCUC

3.4 ILC Signaling HandlingThree ILCs perform handling of layer 1, and part of layer 2, of the LAPD protocolon the signaling channels of the BSI or the DSN Interface. Each ILC terminatestwo signaling channels. ILC0 and ILC2 always terminate signaling on the BSI-A.ILC1 can terminate links on BSI-A, BSI-B or from the DSN (via the OBCI).

Each ILC has two HDLC formatters. Each formatter, which handles a serial fullduplex channel from a 2 Mbit/s PCM link, performs:

Generation of HDLC flags

Automatic zero insertion and deletion

Abort generation and detection

Generation of inter-frame fill characters

Frame check sequence.

The ILCs operate in the 2 Mbit/s mode. They can terminate either 64 kbit/sor 16 kbit/s signaling links. If a link is terminated, the ILC sends all 1s inthe unused TSs.

When a message is to be sent to an ILC, the OBC stores it in the SRAM.The OBC then sends an appropriate command to the ILC. The ILC gets themessage packet from the SRAM using a DMA access.

When an ILC receives a messages, it stores it in the SRAM using a DMAaccess. After a complete packet has been received, the OBC can access itin the SRAM.

3BK 21239 AAAA TQZZA Ed.04 55 / 142

3 TCUC

3.5 Signaling Link TerminationThe following figure shows the main signaling data and control paths forterminating the signaling links on the TCUC PBA.

Abis LCA

SLM and PADR SLM

ILC1 Switch

OBCI

BSI−A

BSI−B DSNInterface

Signalling Data

Control Data

Alternative Paths

BSI Buffers

BSIRegisters

Internal Loopback

OBC

Multirate Switch

ILC2

SRAM

ILC0 ILC1

Figure 14: Signaling Termination Data and Control Paths

As previously stated, ILC1 can terminate two signaling links on BSI-A or BSI-B,or on the DSN side. The ILC1 switch selects the links to be terminated. TheOBC controls this switch by writing to the BIR of the Abis LCA.

Signaling can also be switched through the multirate switch using SPCs.

An ILC receives the complete bit stream from the 2 Mbit/s link to which it isconnected. The ILC receives data in either one or two TSs of the bit stream.

The 2 Mbit/s stream from an ILC is ANDed on the appropriate 2 Mbit/s linkin the Abis LCA. An ILC can send data in one or two separate TSs of this bitstream (the same TSs as in the receive bit stream). A 1 is transmitted in allthe other TSs.

56 / 142 3BK 21239 AAAA TQZZA Ed.04

3 TCUC

3.6 Multirate Traffic Channel SwitchingThe following figure shows the main signaling data and control paths for themultirate traffic switching function on the TCUC PBA.

Abis LCA

SLM and PADR SLM

BSI−A

BSI−B

Multirate Switch

BSIRegisters

BSI Buffers

Internal Loopback

OBCI

DSNInterface

Traffic Data

Control Data

Alternative Paths

OBC

Figure 15: Multirate Traffic Switching - Data and Control Paths

The multirate switch performs switching of the different rate TCHs under thecontrol of the BSI registers. At the L port of the OBCI, each TCH is containedin one complete TS.

3BK 21239 AAAA TQZZA Ed.04 57 / 142

3 TCUC

3.7 Data FlowThe following figure shows the main data flow paths for the TCUC PBA.

DSN Interfaces

OBC

Broadcast Interface BCU

A B A B

ILC2 ILC1

Multirate Switch

BSI−A

BSI−B

A B

ILC0

OBCI DMA

ILC DMA

BCU DMA

OBC Memory

A

B

OBCI

L port

Abis LCA

ILC1 Switch

Figure 16: TCUC PBA - Main Data Flow Paths

3.8 O&MThis section describes the O&M facilities provided on the TCUC.

It comprises:

LEDs

Push button

Replacement.

58 / 142 3BK 21239 AAAA TQZZA Ed.04

3 TCUC

3.8.1 LEDs

There are four LEDs mounted on the front panel. The following table describesthe functions of the LEDs.

LED Description

4 Indicates a Prompt Maintenance Alarm and is litwhen:

A non-maskable interrupt is generated


A PMA is generated.


1 and 2 When flashing (normal condition) indicate that theOBC is active.

Table 11: TCUC LED Description

3.8.2 Push Button

When the push button is pressed, the top LED (LED 4) toggles to the oppositestate, e.g., if it was off, it is lit. After two seconds, the LED toggles again. Whenthe push button is released, a reset or an NMI is generated.

3.8.3 Replacement





3BK 21239 AAAA TQZZA Ed.04 59 / 142

3 TCUC


Refer to Common Information (Section 1.2) .

Power Supply

The TCUC operates from a +5 V +/-5% supply.

Front Panel


Turn−button Latch

Turn−button Latch

LED 1 (Red)

LED 2 (Red)

LED 3 (Red)

LED 4 (Red)

Push Button


Figure 17: TCUC Front Panel

60 / 142 3BK 21239 AAAA TQZZA Ed.04

4 DTCC

4 DTCC

This section describes the hardware architecture of the DTCC PBA.

3BK 21239 AAAA TQZZA Ed.04 61 / 142

4 DTCC

4.1 IntroductionThe following figure shows a simplified diagram of the hardware architecture ofthe DTCC PBA. The CEPK, CENK and CEBK are similar to those of the CPRC.For more information about their functions, refer to CPRC (Section 2)).


External Alarms

Remote Inventory

Light Emitting Diodes

Push ButtonBroadcast Bus

DTCC PBA



2 Mbit/s PCM Link To/From the Ater Interface

To/From BCL PBA


Control Element

Processor Kernel

Ater Logic Cell Array

ILC Signalling Handling

Trunk Access Circuit

BSC Clock Interface

Control Element

Broadcast Kernel

*

*

* *

Figure 18: DTCC PBA Simplified Hardware Architecture

4.2 Trunk Access Circuit

4.2.1 Signal Processing

The TRAC is an LSI (Large Scale Integration) device which performs all thesignal processing functions necessary to:

Control one 2 048 kbit/s duplex PCM trunk (the Ater Interface)

Control one 4 096 kbit/s PCM link to the OBCI

Supply a regenerated clock signal for use by the BSC clock system

Perform signaling functions

Connect to an ILC to terminate signaling channels

Provide a multislot connection service.

62 / 142 3BK 21239 AAAA TQZZA Ed.04

4 DTCC

4.2.2 2048 kbit/s PCM Trunk Control

The TRAC performs the following functions to control the 2 048 kbit/s PCMtrunk:

Digital clock recovery, i.e., the extraction of the clock signal from theincoming bit stream for re-timing and clock generation purposes

Conversion of the High Density Bipolar of order 3 (HDB3) or Alternate

Mark Inversion (AMI) coded signals, received on the Ater Interface, to thebinary-coded signals used in the DTCC

Conversion of binary-coded signals, used in the DTTC, to the HDB3 orAMI-coded signals used on the Ater Interface

Frame, multiframe and CRC4 synchronization

Spare bit decoding

Generation of the Alarm Indication Signal

CRC4 generation and monitoring

Re-timing to allow for frequency differences, jitter and wander

Alarm monitoring for transmission errors as follows:

Loss of Signal

Loss of Frame Alignment

RAI (Remote Alarm Indication (A-Alarm))

AIS (Alarm Indication Signal)

Loss of Multiframe Alignment

Remote Signaling Alarm

Slip

Loss of CRC4 Alignment

Auxiliary Pattern.

Error counting for CRC4, Channel 0 (CH0), and HDB3

Channel Associated Signaling extraction and insertion

Insertion of a fixed pattern into idle channels

Automatic A-bit generation

Automatic E-bit insertion.

3BK 21239 AAAA TQZZA Ed.04 63 / 142

4 DTCC

4.2.3 4096 kbit/s PCM Link Control

The TRAC performs the following functions to control the 4 096 kbit/s PCMlink to the OBCI:

PCM link synchronization

Conversion from the 2.048 Mbit/s 8-bit signals received on the Ater Interface

to the 4.096 Mbit/s 16-bit format used in the BSC

Conversion from the 4.096 Mbit/s 16-bit signals received from the OBCI tothe 2.048 Mbit/s 8-bit format used on the Ater Interface

Insertion of frame count bits for multislot connection service.

4.2.4 Clock Functions

The TRAC supplies the BSC clock system with:

The extracted (regenerated) 2.048 MHz clock signal for possible use in thegeneration of the BSC system clock

An Alarm To Clock qualifying signal.

4.2.5 OBC Control

The OBC controls some functions by writing to, and reading from, the TRACinternal registers and RAM.

4.2.6 Diagnostic Test Functions

For diagnostic test purposes, the TRAC can perform two loop tests:

An inner loop, which loops back the transmit bit stream to the receivedbit stream

An outer loop, which loops back the AIS bit stream into the receive bit

stream.

The OBC control the loops by writing to the TRAC command register.

64 / 142 3BK 21239 AAAA TQZZA Ed.04

4 DTCC

4.3 ILC Signaling HandlingThe ILC terminates two signaling channels mapped into any TS of the AterInterface (except TS0). The following figure shows a simplified functionaldiagram of the signaling link handling.

AterInterface

Signalling Data

Control Data OBCISRAM

ILC

OBC

TRAC Ater LCA

Figure 19: Signaling Link Handling - Data and Control Paths

4.3.1 HDLC Formatters

The ILC, which has two HDLC formatters, is configured in the 2 Mbit/s mode.

Each formatter handles a serial full duplex channel from a 2 Mbit/s PCMlink and performs:

Generation of HDLC flags

Automatic zero insertion and deletion

Abort generation and detection

Generation of inter-frame fill characters

Frame check sequence.

4.3.2 Signaling Link Speeds

The ILC can terminate either 64 kbit/s or 16 kbit/s signaling links. If a 16 kbit/slink is terminated, the ILC sends all 1s in the unused TSs.

4.3.3 Transmit Messages

The OBC places messages to be sent to the ILC in the OBCI SRAM. It thensends an appropriate command to the ILC. The ILC gets the message packetfrom the SRAM using a DMA access.

4.3.4 Receive Messages

The ILC places received messages in the SRAM using a DMA access. After acomplete packet has been received, the OBC can access it in the SRAM.

3BK 21239 AAAA TQZZA Ed.04 65 / 142

4 DTCC

4.4 Ater Logic Cell ArrayThe following figure shows a simplified functional diagram of the Ater LCA. TheLCA is an FPGA which performs switching of the traffic channels.

As shown in the following figure, the Ater LCA comprises:

A Multirate Switch, which performs the switching of the traffic channels andprovides frame re-timing and resynchronization of the clock signals

ATMRs (Ater Multirate Registers) 0, 1 and 2, which allow the OBC to

control the Ater LCA.

Ater LCA

2 Mbit/s Ater Interface

From OBC

Multirate Switch

Ater MultirateRegisters

TRAC

4 Mbit/s TRAC Interface

4 Mbit/s OBCI Interface

OBCI

4 Mbit/s DSNInterface

Figure 20: Ater LCA Functional Diagram

The ATMRs are 16-bit registers, the bits of which are all read/write. Write andread access to the registers is by word access or byte access (with separatelow and high byte access). Ater Multirate Register 0 (Section 4.4.1) to AterMultirate Register 2 (Section 4.4.3) describe the bits.

4.4.1 Ater Multirate Register 0

The used bits of the ATMR0 are as follows:




Channel block 2 - quadruple-rate TCH 1.

Quadruple-rate TCH These bits allocate the 64 kbit/s TCH to the appropriatechannel block. The bits are only used in switching mode 1.

66 / 142 3BK 21239 AAAA TQZZA Ed.04

4 DTCC











Mode select bit.

Double-rate TCH

The channel block n - double-rate TCH n bits allocate the 32 kbit/s TCH tothe appropriate channel block. The channel block n - double-rate TCH n bitsare only used in switching mode 1.

Mode Select

The mode select bit configures the operating mode of the multirate switch, i.e.,mode0 or mode1. In mode0, the multirate switch operates transparently.In mode1, the multirate switch operates according to the channel block n- double-rate TCH n bits.

3BK 21239 AAAA TQZZA Ed.04 67 / 142

4 DTCC


















Channel block 2 - full-rate TCH 7.

Full-rate TCHs These bits allocate a full-rate TCH to channel block 1 or 2. Ifthis bit is zero, two bits of channel 1 are used for separate half-rate TCHs. Thechannel block n - full-rate TCH n bits are only used in switching mode1.

4.5 BSC Clock A InterfaceThe BSC Clock A Interface allows communication between the DTCC PBA anda BCLA PBA for control purposes. This interface is an address-data multiplexed8-bit parallel bus. It performs parity checks on the data signals. In addition to thedata signals, there are four control signals, an error signal and a parity signal.

A set of registers on the BCLA PBA allows the DTCC to control this PBA. Whenthe software on the DTCC PBA accesses one of the registers, the interfacesequence is started. Only a reset of the DTCC PBA can interrupt this sequence.

If a parity error occurs, the interface generates an interrupt and the BPE bit is setin the MREG. A new interrupt can only be generated if the bit has been cleared.

68 / 142 3BK 21239 AAAA TQZZA Ed.04

4 DTCC

4.6 Signaling Link TerminationThe ILC can terminate two signaling links on any TS of the Ater Interface(except TS0).

The ILC receives the complete bit stream from the 2 Mbit/s link to which it isconnected. The ICL receives data in either one or two TSs of the bit stream.

The 2 Mbit/s stream from an ILC is ANDed on the appropriate 2 Mbit/s link in theTRAC. An ILC can send data in one or two separate TSs of this bit stream (thesame TSs as in the receive bit stream). A 1 is transmitted in all the other TSs.

4.7 Multirate Traffic Channel SwitchingThe following figure shows the main signaling data and control paths for thetraffic switching function on the DTCC PBA.

4 Mbit/s DSNInterface

Ater LCA

Ater−Interface

Traffic Data

Control Data

Multirate Switch

Ater InterfaceRegisters

TRAC

OBC

OBCI

Figure 21: Multirate Traffic Switching - Data and Control Paths

The multirate switch performs switching of the different rate TCHs under thecontrol of the BSI registers. At the L port of the OBCI, each TCH is containedin one complete TS.

3BK 21239 AAAA TQZZA Ed.04 69 / 142

4 DTCC

4.8 Data FlowThe following figure shows the main data flow path for the DTCC PBA.

A

B

DSN Interface

OBC

Broadcast Interface

BCU

OBCI

L port

2 MHz Ater

Interface

A B

ILC

Ater LCA

OBC Memory

Test Loop

G.703 Interface

TRAC

ILC DMA

BCU DMA

OBCI DMA

Figure 22: DTCC PBA - Main Data Flow Paths

4.9 O&MThis section describes the O&M facilities provided on the DTCC.

It comprises:

LEDs

Push Button

Replacement.

70 / 142 3BK 21239 AAAA TQZZA Ed.04

4 DTCC

4.9.1 LEDs

As previously stated, there are four LEDs mounted on the front panel. Thefollowing table describes the functions of the LEDs.

LED Description

4 Indicates a Prompt Maintenance Alarm, and is lit when:



A PMA is generated.


1 and 2 When flashing (normal condition) indicate that the OBC is active.

Table 12: DTCC LED Description

4.9.2 Push Button

When the push button is pressed, the top LED (LED 4) toggles to the oppositestate, e.g., if it was off, it is lit. After two seconds, the LED toggles again. Whenthe push button is released, the reset or an NMI is generated.

4.9.3 Replacement





3BK 21239 AAAA TQZZA Ed.04 71 / 142

4 DTCC


Refer to Common Information (Section 1.2).

Power Supply

The DTCC operates from a +5 V +/-5% supply.

Front Panel


Turn−button Latch

Turn−button Latch

LED 1 (Red)

LED 2 (Red)

LED 3 (Red)

LED 4 (Red)

Push Button


Figure 23: DTCC Front Panel

72 / 142 3BK 21239 AAAA TQZZA Ed.04

5 SWCH

5 SWCH

This section describes the hardware architecture of the SWCH PBA.

3BK 21239 AAAA TQZZA Ed.04 73 / 142

5 SWCH

5.1 Introduction

5.1.1 Functions

The SWCH PBA performs the following functions:

Terminates 16 asynchronous, serial 32-channel PCM duplex transmissionlinks. Each port terminates one PCM link

Synchronizes the received serial bit streams to its own time reference

Stores the current status of each of the 32 channels for each PCM link

Analyzes the protocol bits in each channel and the current status of thechannel. This provides information about the type of data the channel

contains, e.g., a speech sample

Sets up, maintains and releases simplex connections between the inputchannels and the output channels connected to the PBA. This is in

accordance with commands received in the channels of the PCM links

Diagnoses internal malfunctions

Minimizes transmission delays for connections through the DSN by

assigning the first channel available on the chosen output PCM link.

5.1.2 Variants

There are two variants of the SWCH PBA, depending on whether the PBA isused as an Access Switch or as a Group Switch. Unbalanced signals are usedto connect the CEs to the ASs. Balanced signals are used for connectionsbetween the ASs and the GSs, and between the GSs. Figure 24 shows the ASvariant, which has unbalanced signals connected to ports 0 to 7. Figure 25shows the GS variant, which has balanced signals connected to all its ports.Both variants perform the same basic functions:

5.1.3 Functional Areas

The SWCH PBA comprises the following functional areas:

SWEL (Switching Element)

Serial Line Receivers and Line Drivers

Clock Input Circuit

VCO (Voltage Controlled Oscillator) Circuit

Power-on Reset Circuit

Hot Replacement Protection (not shown in the figures)

Odd or Even Port Interchange (SWAP)

Clock Buffers and Frame Delay Circuit (only AS variant).

74 / 142 3BK 21239 AAAA TQZZA Ed.04

5 SWCH

Line Receivers and Line Drivers Line Receivers and Line Drivers

To/From Associated CE

TX8

RX8

TX9

RX9

TXA

RXA

TXB

RXB

TXC

RXC

TXD

RXD

TXE

RXE

Clock A

Clock B

From Clock and Alarm

System

Odd or Even Port Interchange Signal (SWAP) from the backpanel

TXF

RXF

Voltage Controlled Oscillator Circuit

RX0

To/From Associated Switching Stage

Down UpPhase−locked Loop Control

Clock Input Circuit

1

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

Port D

Port E

Port F

SWEL

TX0FRAME04 MHz0

RX1

TX1FRAME14 MHz1

RX2

TX2FRAME24 MHz2

RX3

TX3FRAME34 MHz3

RX4

TX4FRAME44 MHz4

RX5

TX5FRAME54 MHz5

RX6

TX6FRAME64 MHz6

RX7

TX7FRAME74 MHz7

Clock

Frame

Clock

Frame

Power−On Reset Circuit

Clock Buffers and Frame

Delay Circuit

Figure 24: Switch PBA, AS Variant Functional Diagram

3BK 21239 AAAA TQZZA Ed.04 75 / 142

5 SWCH

Line Receivers and Line Drivers

Line Receivers and Line Drivers


TX0 TX8

RX8

TX9

RX9

TXA

RXA

TXB

RXB

TXC

RXC

TXD

RXD

TXE

RXE

Clock A

Clock B

From Clock and Alarm System

Odd or Even Port Interchange Signal (SWAP) from the backpanel

TXF

RXF

Voltage Controlled Oscillator Circuit

RX0

TX1

RX1

TX2

RX2

TX3

RX3

TX4

RX4

TX5

RX5

TX6

RX6

TX7

RX7


Down Up Phase−locked Loop Control

Clock Input Circuit

1FRAMET

1

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

Port D

Port E

Port F

SWEL

Power−On Reset Circuit

Figure 25: Switch PBA, GS Variant Functional Diagram

76 / 142 3BK 21239 AAAA TQZZA Ed.04

5 SWCH

5.2 Switching ElementThe SWEL performs the following main functions:

Switching

Clock Selection

PLL (Phase-locked Loop) Control

Odd or Even Port Interchange (SWAP) mechanism.

Note: The 16 duplex ports in a SWEL are indicated hexadecimally. Ports 8, 9, A andB are sometimes called low-numbered ports. Similarly ports C, D, E and F aresometimes called high-numbered ports.

5.2.1 Switching Function

The SWEL performs time-space switching between 16 incoming, 32-channelPCM links and 16 outgoing, 32-channel PCM links. This allows any channel(time) of any incoming PCM link (space), to be connected any channel(time) of any outgoing PCM link (space). The SWEL is therefore a combinedtime-space-time switch.

The SWEL uses its own path search and path map mechanisms to establishthe connections.

These internal functions include:

Transferring the incoming data to the required outgoing link and channel

Temporarily storing the incoming PCM channel words.

The SWEL performs the following operations to set up paths between thePCM links:

1. The receiver of each port synchronizes its incoming serial PCM bit stream tothe SWEL internal time reference.

2. The receivers store the current status of each of the 32 channels for theconnected PCM link.

3. The receivers analyze the protocol information in each channel word and thecurrent status of the channel. This analysis determines the type of datacontained in the channel, e.g., a Path Select Word or SPATA.

4. Each receiver uses the channel words to set up, maintain and releasesimplex connections between any channel of the receiver to any transmitter.

5. The transmitter assigns the first free channel available on the chosenoutput PCM link.

5.2.2 Clock Selection

When power is applied to the PBA, the SWEL randomly selects one of the two8.192 MHz clock signals. These signals are received from the Clock and AlarmSystem via the Clock Input Circuit (see Clock Input Circuit (Section 5.4) ).

If the selected clock continues as an uninterrupted pulse train, the selectionis maintained. If, however, the selected clock pulses are absent, the otherclock is selected.

3BK 21239 AAAA TQZZA Ed.04 77 / 142

5 SWCH

5.2.3 Phase-locked Loop Control

The SWEL, in conjunction with the external VCO circuit (see Voltage-controlledOscillator Circuit (Section 5.5) ), forms a Phase-locked Loop circuit. The PLLcircuit provides a continuous internal clock signal. This signal is phase andfrequency synchronous with the selected 8.192 MHz source clock. If theselected source clock fails, the source clock is reselected. During this sourceclock reselection, the clock signal produced by the PLL circuit remains stable.

5.3 Serial Line Receivers and Line DriversThe Serial Line Receivers and Line Drivers match the impedance and linecharacteristics for the 16 duplex PCM links. They also isolate the switch portsfrom the external network connections.

Balanced Lines

In the GS variant, all the incoming PCM signals are fed over balanced lines.Line receivers convert the balanced signals to unbalanced (single-ended)signals before applying them to the SWEL.

Line drivers convert the unbalanced outputs from the SWEL into balancedsignals before applying them to balanced lines.

Unbalanced Lines

In the AS variant, eight of the incoming PCM signals (Ports 0 to 7) are fed overunbalanced lines. All 16 of the signals are applied to identical line receivers.Different resistor terminations are used for the balanced and unbalancedsignals.

Eight of the outputs from the SWEL are fed to Ports 0 to 7 as unbalancedsignals. Ports 0 to 7 use different line drivers from those used by the other ports.

5.4 Clock Input CircuitThe clock input circuit receives two external, balanced-line 8.192 MHz clocksignals, from the Clock and Alarm System. It converts the balanced signals intounbalanced signals for the SWEL.

5.5 Voltage-controlled Oscillator CircuitThe VCO circuit forms part of a PLL circuit (the other parts are in the SWEL).The VCO circuit provides a continuous clock signal that is phase and frequencysynchronized with the selected 8.192 MHz clock.

5.6 Power-on Reset CircuitA power-on reset circuit performs an initialization sequence when the SWCHPBA is inserted into the back panel. This sequence ensures that the PBA isinitialized before it handles traffic.

5.7 Clock Buffers and Frame Delay CircuitThe clock buffers and frame delay circuit use the clock and frame signals fromthe SWEL to provide for the timing requirements of the CEs.

78 / 142 3BK 21239 AAAA TQZZA Ed.04

5 SWCH

5.8 O&MThe only O&M facility provided on the SWCH is hot replacement. Hot insertioncircuits allow the PBA to be inserted into, or removed from, the back panelwith the power still on.




3BK 21239 AAAA TQZZA Ed.04 79 / 142

5 SWCH



Power Supply

The SWCH operates from a +5 V +/-5% supply.

Front Panel


Turn−button Latch

Turn−button Latch


Figure 26: SWCH Front Panel

80 / 142 3BK 21239 AAAA TQZZA Ed.04

6 BCLA

6 BCLA

This section describes the BCLA PBA.

3BK 21239 AAAA TQZZA Ed.04 81 / 142

6 BCLA

6.1 IntroductionThere are two variants of the BCLA PBA:

System-BCLA (only in the first cabinet). It provides the Clock Generation

and Distribution Function at the system level

Rack-BCLA (in all cabinets). It distributes the clock signal in the associated

cabinet.

The BCLA PBA performs the following main functions:

Clock Generation

Broadcast Bus Distribution

DTC Interface

Remote Inventory

External Alarm Scanning and Driving (SYS-BCLA only)

LEDs.

The following figures respectively show the functional diagrams of theSYS-BCLA and RACK-BCLA variants.

PLL

Master Selector

Distribution

Reference Selector

Clock Signals from DTCs

Broadcast Bus

ClockGeneration

Broadcast Bus

To Partner SYS−BCLA

From Partner SYS−BCLA

1 2 3

Status Outputs

Control Inputs

Status Outputs

Status Outputs

Control Inputs

Status Information from Partner

Status Information to Partner

(16 MHz)

(8 MHz)

1 2 3 11 12

System Clock to RACK−BCLA

(8 MHz)

10 Input Alarms

6 Output Alarms

1 2 6

DTC Interface

External Alarms

I/O

Buffer

Distribution

Remote Inventory

Information

Local Clock

Figure 27: SYS-BCLA Functional Block Diagram

82 / 142 3BK 21239 AAAA TQZZA Ed.04

6 BCLA

PLL

Reference Selector

Remote Inventory

Information

System Clocks from SYS−BCLA Broadcast Bus

Clock regeneration

Distribution

A 3

Status Outputs

Control Inputs

Status Outputs

Status Information from Partner RACK−BCLA

Status Information to Partner RACK−BCLA

Output Clock Disable

1 2 3 12 13

Distributed Rack Clock

(8 MHz)

DTC Interface

Broadcast Bus1 2 n

n = maximum of 10)

Buffer

Distribution

Figure 28: RACK-BCLA Functional Block Diagram

6.2 Clock GenerationThe Clock Generation function comprises:

Reference Selector

PLL

Master Selector (SYS-BCLA only)

Output Clock Disable (RACK-BCLA only).

3BK 21239 AAAA TQZZA Ed.04 83 / 142

6 BCLA

6.2.1 Reference Selector

6.2.1.1 SYS-BCLAThe reference selector selects one of the input (2 MHz) clocks as the referenceclock for the PLL. The input clocks are:

Three medium-priority clocks from Ater incoming trunks, i.e., from DTC

PBAs

A low-priority local clock derived from an onboard oscillator.

The local clock is used:

For test purposes

During worst case conditions (i.e., the Ater trunks are not working correctly)

During startup and reset.

During normal operations, the onboard logic/micro-controller selects anappropriate clock as the reference. In Test mode, control bits from the DTCcontrol register select the reference clock used.

6.2.1.2 RACK-BCLAThe reference selector selects an 8 MHz clock from the input clocks (clock A orclock B), as the reference for the regeneration PLL.

During normal operations, the onboard logic/micro-controller selects anappropriate clock as the reference. In Test mode, control bits from the DTCcontrol register select the reference clock used.

6.2.2 Phase-locked Loop

6.2.2.1 SYS-BCLAThe PLL generates a jitter-free and wander-free clock signal using the selectedreference signal. In addition, it filters out any phase gaps caused if the selectedreference clock at the input of the PLL is switched.

6.2.2.2 RACK-BCLAThe PLL regenerates the 8 MHz clock using the clock from one of theSYS-BCLA PBAs. This regenerated clock has a duty-cycle of approximately50%.

6.2.3 Master Selector

Although two SYS-BCLA PBAs are used to provide redundancy of the systemclock, only the clock generated by one of them is distributed in the BSC.

Both the SYS-BCLA PBAs exchange their clocks and status with each other.The onboard micro-controller compares the status of its own PBA with that ofthe partner BCLA. It then ensures, if both PBAs are operating correctly, thata clock is selected and distributed.

84 / 142 3BK 21239 AAAA TQZZA Ed.04

6 BCLA

6.2.4 Output Clock Disable

On the RACK-BCLA PBA, this function disables the distribution of the clockby the PBA if both the following conditions apply:

Its own PLL is not operating within the control range

The PLL on the partner PBA is operating correctly.

This is the only time when the output clock is disabled.

6.3 Clock Distribution

6.3.1 SYS-BCLA

Drivers distribute the 8 MHz clock to the RACK-BCLA PBAs in the differentcabinets. There are 12 separate outputs, each of which can distribute the clockto the RACK-BCLA PBAs.

6.3.2 RACK-BCLA

On the RACK-BCLA PBA, drivers distribute the 8 MHz clocks to the users in thecabinet (GS Elements, AS Pairs). It also distributes the clocks to other userssuch as BIUA PBAs. A maximum of 13 separate outputs are provided.

6.4 Broadcast Bus DistributionEach BCLA PBA receives and distributes one broadcast bus, either A or B,depending on its position in the system. The broadcast bus is not duplicated.

6.4.1 SYS-BCLA

There are six drivers on the SYS-BCLA PBA. Each driver distributes thebroadcast bus to one RACK-BCLA PBA.

6.4.2 RACK-BCLA

There are ten drivers on the RACK-BCLA PBA. Each driver distributes thebroadcast bus to a maximum of eight CEs.

6.5 Remote Inventory RegisterThe RINVR stores inventory information. This register can be read by theDTCC which controls the BCLA PBA.

When the power is off, a back panel interface can provide access to theinventory information.

3BK 21239 AAAA TQZZA Ed.04 85 / 142

6 BCLA

6.6 DTCC InterfaceThis parallel bi-directional interface allows a controlling DTCC to access thecontrol inputs and the status outputs of the BCLA PBA.

6.6.1 Clock Control Status Registers

Access is by reading from and writing to a number of registers, the CCSRs.

6.6.2 Alarm Registers

External input alarms are read via two Alarm Input Registers. External outputalarms are written to an Alarm Output Register.

The RINVR transfers inventory commands and information between the DTCCand the BCLA.

All the CCSRs and RINVR are implemented in the memory of the onboardmicro-controller. Access to these registers is relatively slow, since they have anaccess time of approximately 10 micro-seconds.

6.6.3 Status Change Register

The ST-CHNG-R provides fast access to allow changes in the status of theBCLA PBA to be detected quickly. After the register is read, detailed informationabout the current status of the PBA is then obtained by reading the CCSRs.

The Alarm Input Registers and the ST-CHNG-R are fast accessible registers,with an access time of a less than one micro-second. These registers are readby the DTCC software to monitor the BCLA PBA.

6.7 External Alarm Scanning and DrivingThis function is only provided on the SYS-BCLA PBA.

6.7.1 Alarm Inputs

All the input alarm signals are written into the CCSRs where the DTCC canread them.

6.7.2 Alarm Outputs

All the alarm outputs are written to a Control Register by the DTCC.

6.8 O&MThis section describes the O&M facilities provided on the BCLA.

It comprises:

LEDs

Push Button

Replacement.

86 / 142 3BK 21239 AAAA TQZZA Ed.04

6 BCLA

6.8.1 LEDs

6.8.1.1 SYS-BCLAFive LEDs are provided on the SYS-BCLA PBA.

The functions of the LEDs are as follows:

LED 1, LED 2 and LED 3 indicate which clock is selected on the BCLA (1 = on,0 = off) as follows:

LED 1 LED 2 LED 3 Reference clock

0 0 0 No reference

0 0 1 Local

1 0 0 Ater 1

1 0 1 Ater 2

1 1 0 Ater 3

Table 13: DTCC LED Description

LED 4 is:

Off in normal conditions

On in the case of an error (PLL out of range, broadcast bus failure, etc.)

Flashing (see following table).

LED 5 indicates the status of the master selector and is:

On when the BCLA uses one of its own reference(s) for clock distribution

Off when the BCLA uses a reference from the partner BCLA.

Flashing rate Meaning Explanation

1s On/1s Off Power-on The PBA is initialized and a time out is started to get the PLL locked onto the local oscillator.

150ms On/150msOff

Errorafterpower-on

The PLL locked on time out has expired. Either the PLL Out of Range(POOR) still exists or a reference failure has been detected. The PBAdoes not start the normal function and waits until the POOR and, or, thereference failure clears. Normally, the PBA must be repaired.

300ms On/300msOff

TestMode

The PBA is in Test Mode.

600ms On/600msOff (SYS-BCLAonly)

LocalOscillator

The PBA is forced to the local oscillator state by means of a plug onthe back panel.

Table 14: BCLA PBA - LED 4 Flashing Indications

3BK 21239 AAAA TQZZA Ed.04 87 / 142

6 BCLA

6.8.1.2 RACK-BCLAThree LEDs are provided on RACK-BCLA:

LED 1 is On if System Clock A is selected

LED 2 is On if System Clock B is selected

LED 3 is not equipped

LED 4 is:

Off in normal conditions

On in case of an error (PLL out of range, broadcast bus failure, etc.)

Flashing (see the table below).

LED 5 is not equipped.

6.8.2 Replacement

Hot insertion circuits allow the PBA to be inserted into, or removed from, theback panel with the power still applied.




88 / 142 3BK 21239 AAAA TQZZA Ed.04

6 BCLA



Power Supply

The BCL operates from the following supplies:

+5 V +/-5%

+12 V +/-5%

-12 V +/-5%

Front Panel

Turn−button Latch

Turn−button Latch

LED 1 (Red)

LED 2 (Red)

LED 3 (Red)

LED 4 (Red)

Push Button


LED 5 (Red)

Figure 29: BCLA Front Panel

3BK 21239 AAAA TQZZA Ed.04 89 / 142

6 BCLA

90 / 142 3BK 21239 AAAA TQZZA Ed.04

7 DC/DC Converter

7 DC/DC Converter

This section describes the DC/DC converter used in the BSC.

3BK 21239 AAAA TQZZA Ed.04 91 / 142

7 DC/DC Converter

7.1 IntroductionThe DC/DC converter is a switching type. It has a separate output transformerfor each supply it generates. Each transformer drive circuit uses a common160 kHz oscillator. This provides two phases of output drive, each at 80 kHz.Full DC isolation between the input and output is provided. All the outputvoltages are independently regulated and protected against out-of-tolerancevoltages and currents.

7.1.1 Output Diodes

All the outputs have diodes that allow the converters to operate in the N + 1configuration. This means that each output is doubled and separated by thediodes. The outputs are called A and B.

7.1.2 Modes of Operation

The converter has two modes of operation:

Run, in which it is operating correctly and all the output voltages are within

the specified ranges.

Alarm, in which an overvoltage or undervoltage has occurred on one ormore of the outputs and the converter has shut off. The converter cannot be

restarted from alarm mode unless the input supply is interrupted.

7.1.3 Automatic Start

The converter automatically starts when the input voltage reaches 38.4 V.

7.2 CharacteristicsThis section describes the electrical characteristics of the DC/DC Converter.

7.2.1 Input Characteristics

The DC/DC Converter meets all the output requirements specified in OutputCharacteristics (Section 7.2.2) for the input voltage conditions specifiedin this section.

7.2.1.1 Static Input VoltageThe input voltage range is 34.4 V DC to 74 V DC.

At input voltages below the above-specified minimum, regulation may not beprovided but the unit will not be damaged.

92 / 142 3BK 21239 AAAA TQZZA Ed.04

7 DC/DC Converter

7.2.1.2 Transient VariationsThe input can rise to 80 V for one second at a maximum rate of 10 V/ms,starting from any voltage within the static input range.

The input voltage can change by up to +/-8 V within the static input rangeat a maximum range of 50 V/ms. The output(s) must stay within the staticregulation limits.

The input is protected against a surge wave with a peak of 150 V and a pulseshape of 0.3/0.6[thinsp]ms.

The input voltage can drop from the maximum to zero for 100[thinsp]ms, andthen increase to the maximum at a rate of 50 V/ms +/-20%. During the voltagedrop, the unit must stay in RUN-mode and the output(s) must stay withinthe static regulation limits.

7.2.1.3 Electrical Noise Feedback to SourceWithin the frequency range 160[thinsp]Hz to 5[thinsp]kHz, noise must notexceed the psophometric value A-filter weighted at 0.1 mV rms.

7.2.2 Output Characteristics

This section describes the output voltage and current characteristics of theDC/DC Converter.

7.2.2.1 Output CurrentThe outputs can continuously provide the maximum current at the A and Boutput, or a combination of both, as listed in the following table.

Output Voltage Maximum Current

+5 V 22 A

+5 VM 1 A

+12 V 0.6 A

-12 V 0.1 A

Table 15: Maximum Output Currents

7.2.2.2 Output PowerThe maximum output power is 120 W.

3BK 21239 AAAA TQZZA Ed.04 93 / 142

7 DC/DC Converter

7.2.2.3 Static RegulationThe following table lists the static regulation parameters.

With no load on any of the outputs, none of the outputs must:

Exceed the overvoltage limit

Decrease below the undervoltage limit.

Output Output Voltage Range Load Current Range

+5 V 4.97 V - 5.25 V 1 A - 22 A

+5 VM 4.99 V - 5.25 V 0.05 A - 1 A

+12 V 11.76 V - 12.36 V 0.05 A - 0.6 A

-12 V 11.76 V - 12.36 V 0.002 A - 0.1 A

Table 16: Static Regulation Parameters

7.2.2.4 Dynamic Load RegulationFor dynamic load changes of up to 50% of the full load, in 100 ms:

The percentage change of the original static output voltage must not exceed0.15[thinsp] times the percentage load change

The output must return to the static regulation limits within 5[thinsp]ms.

This means, for example, that if a 20% change occurs in the load, the voltagemust not change by more than 3%.

7.2.2.5 Dynamic Load InteractionThe percentage deviation for any one output must be less than 0.05[thinsp]timesthe percentage load change on any other output. The output must return tothe static regulation limits within 5 [thinsp]ms. For a 20% load change on oneoutput, the other outputs must not deviate by more than 1%. The load changemust be 50% of the full load within the specified load range in 100[thinsp]ms.

94 / 142 3BK 21239 AAAA TQZZA Ed.04

7 DC/DC Converter

7.2.2.6 Ripple and NoiseThe output ripple and noise peak in the frequency range DC to 20[thinsp]MHzmust not exceed the values given in the following table. The values apply to allload conditions between the minimum and maximum.

Output Output Ripple and Noise Peak

+5 V/+ 5 VM 50 mV

+12 V/- 12 V 120 mV

Table 17: Output Ripple and Noise Peak

7.2.2.7 Output Voltage Rise TimeThe rise time of the +5 V output must be less than 50[thinsp]ms (from 10% to90%) with an input of 50[thinsp]V.

7.3 Voltage and Current ProtectionThe DC/DC Converter provides both input and output protection.

7.3.1 Input Protection

The input protection features of the DC/DC Converter are as follows:

An internal 10 A fuse protects the input circuit from over-current

Diodes provide protection against accidental reversal of the input voltage

The inrush current during the application of power is limited to 1.5 A for

between 100 [mu ]s and 100 ms.

3BK 21239 AAAA TQZZA Ed.04 95 / 142

7 DC/DC Converter

7.3.2 Output Protection

Output over-current protection is as follows:

All the outputs are protected if a short-circuit is applied to the output

terminals

The output current with a short-circuit applied does not exceed the limits

specified in the following table

The converter is not damaged if continuous overloads or short-circuitsoccur on any or all the outputs. The undervoltage shutdown circuit can set

the converter to the alarm mode.

All the outputs return to normal when an overload or short-circuit is removed,provided the converter is not in the alarm mode.

Output Maximum Current

+5 V < 37.5 A, with all other outputs at zero

> 25 A, with all other outputs at full load

+5 VM 2.9 A

+12 V 2.9 A

-12 V 2.9 A

Table 18: Maximum Output Current - Short-Circuit Applied

Each output has undervoltage and overvoltage protection. If the voltage driftsbeyond the limits shown below, the undervoltage or overvoltage supervisioncircuits operate.

The overvoltage trip range for each voltage is as follows:

+5 V, +5.5 V to +6 V

+5 VM, +5.5 V to +6 V

+12 V, +13.0 V to +13.8 V

-12 V, -13.0 V to -13.8 V.

The undervoltage trip range for each voltage is as follows:

+5 V, +4.175 V to +4.450 V

+5 VM, +4.175 V to +4.450 V

+12 V, +10.125 V to +10.750 V

-12 V, -10.125 V to -10.750 V.

If an output voltage decreases below the undervoltage set point for more than 1s, the converter switches to the alarm mode. If the voltage remains low for lessthan 500 ms, the converter remains in the run mode.

96 / 142 3BK 21239 AAAA TQZZA Ed.04

7 DC/DC Converter

7.4 O&MThe only O&M facilities provided on the DC/DC Converter are the LEDs.

There are two LEDs mounted on the front panel. The following table describesthe functions of the LEDs.

LED Description

Green (RUN) Indicates that the converter outputs are presentand within the normal limits.

Red (ALARM) Indicates that one or more of the converter outputsare not within the preset limits. All the outputs areinhibited and an external alarm signal is activated.

Table 19: DC/DC Converter LED Description

3BK 21239 AAAA TQZZA Ed.04 97 / 142

7 DC/DC Converter



Power Supply

Refer to Input Characteristics (Section 7.2.1).

Front Panel

Identifying Label

LED (Red)

LED (Green)

Hot to Touch Warning Label

Turn−button Latch

Turn−button Latch

Figure 30: DC/DC Converter Front Panel

98 / 142 3BK 21239 AAAA TQZZA Ed.04

8 ASMB

8 ASMB

This section describes the hardware architecture of the ASMB PBA.

3BK 21239 AAAA TQZZA Ed.04 99 / 142

8 ASMB

8.1 IntroductionThe following figure shows a simplified diagram of the hardware architectureof the ASMB PBA.

Local Qmux

Ater 1

Remote Qmux

Ater Mux

LEDs

RS−232 Interface

Ater 2

Ater 3

Ater 4 TS0 Logic

Ater Mux Interface

Ater Interface

Time Space Switch 1

Time Space Switch 2


Control and Status Registers

Sub−rate Switch 2


Controller

Sub−rate Switch 1

Ater Interface

Ater Interface

Ater Interface

Remote Inventory EEPROM

Remote Inventory

Clock Circuits

Qmux Interface

Local Qmux Interface


Watchdog Reset

Switch

Memory

Figure 31: ASMB PBA Simplified Hardware Architecture

100 / 142 3BK 21239 AAAA TQZZA Ed.04

8 ASMB

8.2 Onboard ControllerThe OBC manages the local operations and maintenance of the ASMB PBA.

The OBC:

Configures and reconfigures the ASMB PBA

Monitors the alarms and status of the PBA

Sets up the mapping of the multiplex/demultiplex function

Monitors the performance of the Ater and Ater Mux Interfaces

Controls and monitors the insertion of the tributary (Ater Interface)

information

Controls the insertion and extraction of the embedded Qmux information

Runs self-tests

Controls the PBA alarm LEDs.

8.3 Ater InterfaceThe ASMB has four Ater Interfaces. An Ater Interface link is a G.703 and G.704compatible 2 048 kbit/s PCM link.

The input and output ports provide either 75 coaxial or 120 balanced-pairtermination. The type of termination depends on the PBA variant.

Each Ater Interface comprises a G.703 Clock Extraction circuit and a TTC(Trunk Controller Chip). These two circuits operate in conjunction to performthe Ater Interface functions.

Ater Interface

TCCG.703 Clock

Extraction

To/from Time Space Switch

To/From Sub−rate Switch

HDB3NRZ

Figure 32: Ater Interface

8.3.1 Clock Extraction

The G.703 Clock Extraction circuit extracts a 2.048 Mhz clock signal from thereceived PCM signal data marks for clock regeneration purposes. This localclock signal is used to re-time the incoming PCM signals.

8.3.2 HDB3 to NRZ Conversion

The Ater Interface converts the received HDB3 signal to a binary NRZ(Non-Return to Zero) signal. Conversely, the interface converts the NRZsignals from the Switch to HDB3.

8.3.3 Re-timing

The Ater Interface adapts the frequency and bit alignment of the incomingPCM data stream to the local clock signal. The G.703 Clock Extraction circuitgenerates the clock signal. The frame alignment circuit tolerates jitter andwander in the incoming data without loss of data, as specified in CCITT G.823.

3BK 21239 AAAA TQZZA Ed.04 101 / 142

8 ASMB

8.3.4 Frame Alignment Supervision

Using the data received in TS0, the Ater Interface checks the frame alignment.It performs frame realignment if a loss of frame alignment occurs.

8.3.5 CRC4 Monitoring and Generation

The Ater Interface checks for correct synchronization. It also counts the CRC4errors in the received signal (according to G.704 and G.706). The firmwareuses the CRC4 error count to calculate the performance parameters asspecified in G.821.

8.3.6 Fault Detection

The Ater Interface monitors the incoming 2 048 kbit/s signal to detect faultsand generate error signals.

The following error signals can be detected or generated:

LFA (Loss of Frame Alignment)

Remote Alarm Indication

Bit Error Ratio

LIS (Loss of Incoming Signal)

2 048 kbit/s AIS Detection

LMFA (Loss of CRC4 Multiframe Alignment)

Slip Detection.

8.3.7 Fault Indications Sent to Remote End

The Ater Interface sends AIS and RAI to the remote end according to G.732.

8.3.8 TCC Configuration

As the TCCs do not have a direct interface with the OBC, they are configuredby Time Space Switch 2 of the Switch.

102 / 142 3BK 21239 AAAA TQZZA Ed.04

8 ASMB

8.4 Ater Mux InterfaceThe Ater Mux Interface is similar to the Ater Interface. It performs similarfunctions for the Ater Mux link. An Ater Mux Interface link is a G.703 and G.704compatible 2 048 kbit/s PCM link.

Microbreaks on the Ater Mux Interface do not result in the release of calls.

Microbreaks are short disturbances which can result in the generation of:

LIS

LFA

AIS

LMFA (if CRC4 is active).

Microbreak detection is initiated if there is no valid input data signal. Microbreakcontrol is enabled and disabled by the OBC writing to the RINVR, see OnboardRegisters (Section 8.15.1) .

8.5 SwitchThe Switch performs the multiplexing and demultiplexing, and switchingfunctions. The Switch comprises two Sub-rate Switches and two TSSWs(Time Space Switches).

The Switch also sends and detects redundant AISs in the TS which carriesthe information from the Ater Interfaces. This is done when 1:4 multiplexing isperformed. The OBC software controls this function.

8.5.1 Sub-rate Switch

The SRSs perform the multiplexing and demultiplexing of channels betweenthe four Ater Interface links to/from the Ater Mux link. They also perform theinsertion/extraction of the embedded Qmux channels. This switching function isperformed at the bit level.

At the bit level, the SRSs provide:

Mapping, on a bit basis, of the multiplexing/demultiplexing function

performed, i.e., 1:4 or 1:3

A non-blocking cross-connection between the Ater Interfaces and theAter Mux Interface

A synchronous sub-rate matrix

Software transparency for the hardware relationship of TS0 with respectto the frame pulse

The addition and dropping of the Qmux channels (in 16 kbit/s by over

sampling) via a matrix function

Insertion of tributary information bits to the outgoing Ater Mux signal.

3BK 21239 AAAA TQZZA Ed.04 103 / 142

8 ASMB

SRS1 also performs some clock selection functions.

Clock Selection and Detection

Ater Mux ClockAter 1 ClockAter 2 ClockAter 3 ClockAter 4 Clock

On−board Oscillator

Phase Comparator

Filter16.384 MHz Voltage Controlled Oscillator

Divider 1/2

DividerTiming Generator

Timing to PBA circuits

8.192 MHz

SRS1 PLL

Divider

Figure 33: Clock Selection and Synchronization Circuits

All the extracted clocks are applied to the clock selection and detection circuit inSRS1. A clock signal generated by a Crystal Oscillator is also applied to theclock selection and detection circuit.

The clock selection and detection circuit selects one of the inputs on a prioritybasis as follows:

Ater Mux clock (highest priority)

Ater 1 clock

Ater 2 clock

Ater 3 clock

Ater 4 clock

Onboard Oscillator clock (lowest priority).

The selected clock is applied to a phase comparator. The other input to thephase comparator is the output from the 16 MHz VCO applied via a DividerCircuit. The phase comparator output controls the VCO.

The 8.192 MHz synchronized clock is applied to the Timing Generator. Thisgenerates a 2.048 MHz clock signal, which synchronizes the timing of the PBA.

104 / 142 3BK 21239 AAAA TQZZA Ed.04

8 ASMB

8.5.2 Time Space Switch

The TSSWs perform 2 Mbit/s frame or TS-based switching. This providessimultaneous connections for up to 256 x 64 kbit/s channels.

The switch:

Routes the TSs between the Ater Mux Interface and SRS2

Provides the OBC with read and write access to the TSs

Scans the tributary information bits, AIS, and RAI

Configures the TCCs (part of the Ater and Ater Mux Interfaces) to performthe required functions.

8.6 TS0 LogicThe TS0 Logic inserts and extracts the Qmux information and the FEA (FarEnd Alarm) information. It does this by writing to, or reading from, the spare bitsof the TS0 NFAS (Non Frame Alignment Signal) of the Ater Mux Interface. TheOBC writes the FEA bit into a register which the TS0 Logic accesses.

On the transmit side, the TS0 Logic receives the Qmux information from SRS2.If necessary, it adapts the speed of the signal. Then the TS0 logic combinesthe Qmux information with the FEA bit. It sends the combined signal to TSSW1for onward transmission on the Ater Mux link.

On the receive side, the TS0 Logic receives the TS0 NFAS from the TCC of theAter Mux Interface. It extracts the Qmux information and sends it to SRS2.

The TS0 Logic ensures compatibility with Nokia Network Elements whichuse TS0 for the Qmux information.

3BK 21239 AAAA TQZZA Ed.04 105 / 142

8 ASMB

Modes of Operation

The TS0 Logic operates in one of four modes, as described in the followingtable.

Mode Description

0 No insertion/extraction of the Qmux information in TS0.The output of the TS0 logic is set to the tri-state (highimpedance).

1 Qmux sampling rate is 4 kHz. Bit 8 corresponds to theQmux data.

2 Qmux sampling rate is 8 kHz. Bits 7 and 8 correspond tothe Qmux data.

3 Qmux sampling rate is 16 kHz. Bits 5 to 8 correspond tothe Qmux data.

Table 20: TS0 Logic - Modes of Operation

Mode 0:

No Qmux insertion/extraction in TS0

Mode 1:

Qmux sampling rate = 4 kHz

Mode 2:


Mode 3:


TS0 NFAS

TS0 NFAS 1 1 A 1 1 1 1 Q0

1 1 1 1 1 1 1 1

TS0 NFAS 1 1 A 1 1 1 Q1 Q0

TS0 NFAS 1 1 A 1 Q3 Q2 Q1 Q0

1 2 3 4 5 6 7 8

Figure 34: TS0 Logic - Operating Modes

Bit 3 (A) is the RAI, which is set to 0 during error-free operations. It is set to 1when an RAI is sent to the remote end. The unused national bits are set to 1.

8.7 Serial Communication ControllerThe SCC is a dual channel, multi-protocol communication controller. Itfunctions as a serial-to-parallel and as a parallel-to-serial converter/controller.Two independent full-duplex channels are programmed for asynchronousdata communication.

Channels The two channels are:

Channel A, which provides the local Qmux Interface link

Channel B, which provides the MMI link.

106 / 142 3BK 21239 AAAA TQZZA Ed.04

8 ASMB

8.8 Clock CircuitsThe clock circuits, together with the PLL and SRS1, generate the timing signalsfor the PBA. The following table describes the clock circuits.

Circuit Description

VCO Generates the 16 MHz clock signal which drives the PLL.

Out of RangeDetector

Sends an alarm to the OBC if the control voltage of theVCO exceeds a predefined high or low limit.

CrystalOscillator

Generates an 8 MHz clock signal. This signal is appliedto SRS1.

Table 21: ASMB Clock Circuits

8.9 MemoryThe following table describes the three types of memory on the ASMB PBA.

Circuit Description

EPROM The 512 kbytes EPROM stores all the software requiredfor operational and test tasks.

RAM The OBC stores volatile information in the RAM duringnormal operations. The static RAM has 256 kbytes ofmemory.

EEPROM The EEPROM stores PBA settings such as systemconfiguration and error counters. It provides 64 kbytesof non-volatile memory. Write protection prevents theinformation in the EEPROM being overwritten if an OBCmalfunction occurs.

Table 22: ASMB Memories

8.10 Remote Inventory EEPROMThe Remote Inventory EEPROM stores PBA inventory information. The PBAinventory information includes items such as PBA manufacturing information,PBA identification and PBA history. Access to the Remote Inventory EEPROMis via the Remote Inventory Register (see Onboard Registers (Section 8.15.1)).

8.11 Local Qmux InterfaceThe local Qmux Interface provides local communication with the TSC. Itcomprises a number of buffers and drivers. The interface conforms to therequirements of RS-485. The local Qmux Interface is connected to ChannelA of the SCC.

3BK 21239 AAAA TQZZA Ed.04 107 / 142

8 ASMB

8.12 Remote Qmux InterfaceThe remote Qmux Interface provides point-to-point communication with theTSCA PBA. The interface conforms to the requirements of RS-485. Themaximum operating speed is 2400 baud.

The remote Qmux information is inserted into, and extracted from, the AterMux data stream. The SRS performs this function. This mechanism providescommunication with a remote submultiplexer at the Transcoder site for thetransfer of Qmux information.

8.13 Qmux Address InterfaceThis interface determines the address of the ASMB on the local Qmux busvia a plug on the BPA. The software can reprogram this address to match thenetwork configuration requirements.

8.14 Man-Machine InterfaceThe MMI provides communication with a local maintenance device such as aPC (TSC Terminal). The MMI is connected to one channel of the SCC.

The MMI provides serial asynchronous communication at a speed of up to19200 baud. The baud rate is programmable from 50 to 19200 baud. AnI/O port bit detects the presence of TSC terminal. The interface conformsto RS-232.


8.15 Control and Status RegistersThe control and status registers comprise:

Onboard Registers

TS0 Logic Registers

SCC Registers

TSSW Registers

SRS Registers.

8.15.1 Onboard Registers

There are three onboard registers:

GPR (General Purpose Register)

RINVR

QAR (Qmux Address Register).

108 / 142 3BK 21239 AAAA TQZZA Ed.04

8 ASMB

8.15.1.1 GPRThe GPR is an 8-bit register that allows software control of the local QmuxInterface and the LEDs. It also allows the software to reset the ASMB PBA.

The used read/write bits of the GPR are:

LEDs 1 to 4, which each control one of the four LEDs mounted on thefront of the PBA

SW-Reset, which allows the software to reset the PBA

LQmux-EN, which disables or enables the local Qmux Interface

PITMSK, which is the enable signal for the watchdog timer.

8.15.1.2 RINVRThe RINVR is an 8-bit register that controls access to the Remote InventoryEEPROM. The following table describes the used bits of the RINVR.


OBC-SK RW Drives the clock signal of the Remote Inventory EEPROM.

OBC-CS RW Enables the Remote Inventory EEPROM when set (1).

OBC-PRE RW Enables the protected register when it is set (1).

OBC-DO RO Enables the Remote Inventory EEPROM data outputs.

OBC-IAE RO Indicates whether the Remote Inventory EEPROM can be accessed by the OBC.

MBE RO Enables and disables the microbreak control of the Ater Mux Interface.

REEN RW Controls the remote Qmux Interface transmitter.

TIMEN RW Enables the long range timer.

Table 23: RINVR Bits

3BK 21239 AAAA TQZZA Ed.04 109 / 142

8 ASMB

8.15.1.3 QARThe QAR is an 8-bit register that indicates the Qmux address and the statusof a number of alarms and signals. The following table describes the usedbits of the QAR.


QMA0 - 4 RO Indicate the local Qmux address.

MTPR RO Indicates the status of the PBA, i.e., Test Mode or operational.

OUTRNG RO Indicates that a synchronization alarm (out of range detected) has occurred.

DSR RO Indicates the status of the MMI, i.e., terminal connected/not connected to the PBA.

Table 24: QAR Bits

8.15.2 TS0 Logic Registers

The TS0 Logic Registers control the operations of the TS0 Logic.

They comprise the:

Link Register, which indicates the FEA bit corresponding to the Ater MuxInterface to the TS0 Logic

Mode Register, which indicates the rate at which the Qmux information is

sampled:

No sampling

4 kHz sampling

8 kHz sampling

16 kHz sampling.

8.15.3 SCC Registers

There are four registers via which the OBC controls the SCC:

B Channel Control

A Channel Control

B Channel Data

A Channel Data.

Each register controls the associated channel or data.

110 / 142 3BK 21239 AAAA TQZZA Ed.04

8 ASMB

8.15.4 TSSW Registers

There are four registers via which the OBC controls the TSSWs:

TSSW1 Control Register

TSSW1 Channel Register

TSSW2 Control Register

TSSW2 Channel Register.

Each registers controls the associated TSSW.

8.15.5 SRS Registers

There are two groups of registers via which the OBC controls the SRSs, SRS1registers and SRS2 registers. Each group of registers controls the operation ofthe associated SRS and the functions it performs.

8.16 Watchdog Reset CircuitA reset signal is generated:

If the voltage decreases below +4.75 V

At power-on

Whenever the watchdog timer expires

When the reset button on the front of the PBA is pressed

When a reset signal is applied to the reset pin on the BPA

By a reset command given by software.

The reset is a general PBA reset, including the OBC.

Timer 0 of a Programmable Internal Timer provides the Watchdog function.The Watchdog timeout can be programmed from 4.096 ms to approximately4.5 minutes in steps of 4.096 ms.

8.17 Long Range TimerTimers 1 and 2 of the timer circuit are connected in cascade to provide a longrange timer. When this timer expires, it generates an OBC interrupt.

8.18 O&MThis section describes the O&M facilities provided on the ASMB.

It comprises:

LEDs

Push Button

Replacement.

3BK 21239 AAAA TQZZA Ed.04 111 / 142

8 ASMB

8.18.1 LEDs


LED Description

4 Indicates a Prompt Maintenance Alarm, and is lit when:



A PMA is generated.


1 and 2 When flashing (normal condition), indicate that the OBCis active.

Table 25: ASMB LED Description

8.18.2 Push Button

The push button on the front edge of the PBA generates a reset when it ispressed.

8.18.3 Replacement





112 / 142 3BK 21239 AAAA TQZZA Ed.04

8 ASMB



Power Supply

The ASMB operates from a +5 V +/-5% supply.

Front Panel


Turn−button Latch

Turn−button Latch

LED 1 (Red)

LED 2 (Red)

LED 3 (Red)

LED 4 (Red)

Push−button

9−pin Connector


Figure 35: ASMB Front Panel

3BK 21239 AAAA TQZZA Ed.04 113 / 142

8 ASMB

114 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA

9 BIUA

This section describes the hardware architecture of the BIUA PBA.

3BK 21239 AAAA TQZZA Ed.04 115 / 142

9 BIUA

9.1 IntroductionThe following figure shows a simplified diagram of the hardware architecture ofthe BIU PBA.

Local Qmux

Abis 1

Remote Qmux

BSI 1

LEDs

RS−232 Interface

Abis 2

Abis 3

Abis 4

BSIAbis Interface

On−board Controller

Control and Status Registers


Controller

Sub−rate Switch 1

Abis Interface

Abis Interface

Abis Interface


Remote Inventory

Clock Circuits

Remote Qmux Interface

Local Qmux

Interface


Watchdog Reset

Memory

Clock A

Clock B

LAPD Interface

LAPD

BSI 2BSI

BSI 3BSI

BSI 4BSI

BSI 5

BSI

BSI 6

BSI

BSI 7BSI

Sub−rate Switch 4 BSI 8

BSI

Time Space Switch 1

Sub−rate Switch 2

Sub−rate Switch 3

Time Space Switch 4

Abis 5

Abis 6

Abis Interface

Abis Interface

Selected Clock

AlarmsAlarm Interface

Time Space Switch 2

Time Space Switch 3

TS0 Logic

BIUA

Figure 36: BIUA PBA Simplified Hardware Architecture

116 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA

9.2 Onboard ControllerThe OBC manages the local operations and maintenance of the BIUA PBA.

The OBC:

Configures and reconfigures the BIUA PBA

Monitors the alarms and status of the BIUA PBA

Sets up the mapping of the multiplex/demultiplex function

Monitors the performance of the Ater and Ater Mux Interfaces

Controls the insertion and extraction of the embedded Qmux information

Runs self-tests

Controls the BIUA PBA alarm LEDs.

9.3 Abis InterfaceThe BIUA has six Abis Interfaces. An Abis Interface link is a G.703 and G.704compatible 2 048 kbit/s PCM link.

The input and output ports provide either 75 coaxial or 120 balanced-pairtermination. The type of termination depends on the PBA variant.

Each Abis Interface comprises a G.703 Clock Extraction circuit and a TCC.These two circuits operate in conjunction to perform the Abis Interface functions.

Abis Interface

TCCG.703 Clock Extraction

To/from Time Space Switch

To/From Sub−rate SwitchHDB3

Figure 37: Abis Interface

9.3.1 Clock Extraction

The G.703 Clock Extraction circuit extracts a 2.048 Mhz clock signal fromthe received PCM signal data marks for clock regeneration purposes. Thislocal clock signal is used by the TCC.

9.3.2 HDB3 to NRZ Conversion

The Abis Interface converts the received HDB3 signal to a binary NRZ signal.Conversely, the interface converts the NRZ signals from the Switch to HDB3.

9.3.3 Re-timing

The Abis Interface adapts the frequency and bit alignment of the incoming PCMdata stream to the local clock signal. This signal is generated by the G.703Clock Extraction circuit. The frame alignment circuit tolerates jitter and wanderin the incoming data without loss of data, as specified in CCITT G.823.

9.3.4 Frame Alignment Supervision

Using the data received in TS0, the Abis Interface checks the frame alignment.It performs frame realignment if a loss of frame alignment occurs.

3BK 21239 AAAA TQZZA Ed.04 117 / 142

9 BIUA

9.3.5 CRC4 Monitoring and Generation

The Abis Interface checks for correct synchronization. It also counts theCRC4 errors in the received signal (according to G.704 and G.706). Thefirmware uses the CRC4 error count to calculate the performance parametersas specified in G.821.

9.3.6 Fault Detection

The Abis Interface monitors the incoming 2 048 kbit/s signal to detect faultsand generate error signals.

The following error signals can be detected or generated:

LFA

RAI

BER

LIS

AIS Detection

LCRCMFA

Slip Detection.

9.3.7 Fault Indications Sent to Remote End

The Abis Interface sends AIS and RAI to the remote end according to G.732.

9.3.8 TCC Configuration

As the TCCs do not have a direct interface with the OBC, they are configuredby TSSWs.

9.4 BSIAs shown in the following figure, the BIUA has eight BSIs. Each BSI is a localV.11 type interface. The drivers and receivers of these interfaces conform to theRS-422 standard. The receivers have onboard polarization and terminationresistors.

Receive data trueReceive data falseReceive data

ClockClock true

Clock false

FrameFrame true

Frame false

Transmit dataTransmit data true

Transmit data false

Figure 38: BSI Drivers and Receivers

118 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA

9.5 Sub-rate SwitchThere are four SRSs. These perform the multiplexing and demultiplexing ofchannels between the Abis Interface links to/from the BSI links.

They also perform the insertion/extraction of the:

Embedded Qmux channels

LAPD channels.

This switching function is performed at the bit level.

At the bit level, the SRSs provide:

A non-blocking cross connection between the Abis Interfaces and the BSIs

A synchronous sub-rate matrix

Software transparency for the hardware relationship of TS0 with respect

to the frame pulse

The addition and dropping of the Qmux channels (in 16 kbit/s by over

sampling) via a matrix function

The addition and dropping of LAPD channels (64 kbit/s) via a matrix function

Activity failure detection on the BSIs

The addition of the:

Two-bit channels

Backward Ring Control channel

Ring Control channel.

The insertion, in any TS except TS0, of:

FEA

LCB (Local Clock Bit)

Master Clock Bit.

The SRSs perform mapping on a bit basis from point-to-multipoint and viceversa.

Each SRS is divided into two main functional blocks:

Multiplexer part

Demultiplexer part.

The multiplexer part has 12 inputs, only two of which are used. These inputscan be mapped onto one output. In the demultiplexer part, one input can bemapped onto 12 outputs. Only two outputs of each SRS are used.

3BK 21239 AAAA TQZZA Ed.04 119 / 142

9 BIUA

SRS1 also performs some clock synchronization functions.

Clock Selection and Detection

8 MHz Clock A8 MHz Clock B

On−board Oscillator

Phase Comparator

Filter16 MHz Voltage Controlled Oscillator

1/2

DividerTiming Generator

Timing to PBA circuits

8 MHz

SRS1 PLL

Divider

Figure 39: Clock Synchronization Circuits

Two clock signals from the BSC Clock and Alarm System (BCLA PBAs) areapplied to the clock selection and detection circuit in SRS1. A clock signalgenerated by a Crystal Oscillator is also applied to the clock selection anddetection circuit.

The clock selection and detection circuit selects one of the inputs on a prioritybasis as follows:

8 MHz clock A (highest priority)

8 MHz clock B

Onboard Oscillator clock (lowest priority).

The selected clock is applied to a phase comparator. The other input to thephase comparator is the output from the 16 MHz VCO applied via a DividerCircuit. The phase comparator output controls the VCO.

The output of the Divider Circuit is applied to the Timing Generator. Thisgenerates a 2.048 Mhz clock signal, which synchronizes the timing of the PBA.

120 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA

9.6 Time Space SwitchThe TSSWs perform 2 Mbit/s frame or TS-based switching. This providessimultaneous connections for up to 256, 64 kbit/s channels.

The TSSWs:

Switch the dedicated Traffic Channels (TCHs) in any TS of the Abis Interfaceto the SRSs. TSSW2 performs this function

Switch the dedicated TCHs in any TS of the SRS to the Abis Interfaces.

TSSW3 performs this function

Provide the OBC with read and write access to the TSs. TSSW3 performsthis function

Scan the TB, BRC and RNGC bits received from the TCCs (part of the AbisInterfaces). TSSW2 performs this function

Scan the FEA, MCB and LCB bits. TSSW2 performs this function

Configure the TCCs to perform the required functions. TSSW1 and TSSW4

perform this function.

9.7 TS0 LogicThe TS0 Logic inserts and extracts the:

Qmux information

FEA information

MCB

LCB.

The TS0 Logic does this is by writing to, or reading from, the spare bits of theTS0 NFAS of each Abis Interface. The OBC writes the FEA, MCB and LCB bitsinto a register (one for each Abis Interface) which is accessed by the TS0 Logic.

On the transmit side, the TS0 Logic receives the Qmux information from SRS2.If necessary, it adapts the speed of the signal. Then the TS0 logic combinesthe Qmux information with the FEA, MCB and LCB bits. It sends the combinedsignal to TSSW1 and TSSW4 for onward transmission on the Abis link.

On the receive side, the TS0 Logic receives the TS0 NFAS from the TCC of theAter Mux Interface. It extracts the Qmux information and sends it to SRS2.

The TS0 Logic ensures compatibility with Nokia Network Elements whichuse TS0 for the Qmux information.

3BK 21239 AAAA TQZZA Ed.04 121 / 142

9 BIUA

Modes of Operation

The TS0 Logic operates in one of four modes, as described in the followingtable.

Mode Description

0 No insertion/extraction of the Qmux information or MCBand LCB bits in TS0. The output of the TS0 logic is set tothe tri-state (high impedance).

1 Qmux sampling rate is set at 4 kHz. Bits 4 and 5respectively correspond to the MCB and LCB bits(multidrop ring configuration). Bits 6 and 7 are set to 1. Bit8 corresponds to the Qmux data.

2 Qmux sampling rate is set to 8 kHz. Bits 4 and 5respectively correspond to the MCB and LCB bits(multidrop ring configuration). Bit 6 is set to 1. Bit 7 andBit 8 correspond to the Qmux data.

3 Qmux sampling rate is set to 16 kHz. Bit 4 is set to 1. Bits5 to 8 correspond to the Qmux data.

Table 26: TS0 Logic - Modes of Operation

Mode 0:

No Qmux insertion/extraction in TS0

Mode 1:


Mode 2:


Mode 3:


TS0 NFAS

TS0 NFAS 1 1 A 1 1 Q0

1 1 A MCB LCB 1 1 1

TS0 NFAS 1 1 A 1 Q1 Q0

TS0 NFAS 1 1 A 1 Q3 Q2 Q1 Q0

1 2 3 4 5 6 7 8

MCB LCB

MCB LCB

Figure 40: TS0 Logic - Operating Modes

Bit 3 (A) is the RAI, which is set to 0 during error free operations. It is set to 1when an RAI is sent to the remote end. The unused national bits are set to 1.

122 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA

9.8 Serial Communication ControllerThe SCC is a dual channel, multi-protocol communication controller. Itfunctions as a serial-to-parallel and as a parallel-to-serial converter/controller.Two independent full-duplex channels are programmed for asynchronousdata communication.

Channels

The two channels are:

Channel A, which provides the Local Qmux Interface link


9.9 Clock CircuitsThe clock circuits, together with the PLL of SRS1 generate the timing signalsfor the PBA. The following table describes the clock circuits.

Circuit Description

VCO Generates the 16 MHz clock signal which drives the PLL.

Out of RangeDetector

Sends an alarm to the OBC, if the control voltage of theVCO exceeds a predefined high or low limit.

CrystalOscillator

Generates an 8 MHz clock signal. This signal is appliedto SRS1.

Table 27: BIUA Clock Circuits

3BK 21239 AAAA TQZZA Ed.04 123 / 142

9 BIUA

9.10 MemoryThe following table describes the three types of memory on the BIUA PBA.

Circuit Description

EPROM The 512 kbytes EPROM stores all the software requiredfor operational and test tasks.

RAM The OBC stores volatile information in the RAM duringnormal operations. The static RAM has 256 kbytes ofmemory.

EEPROM The EEPROM stores PBA settings such as systemconfiguration and error counters. It provides 64 kbytesof non-volatile memory. Write protection prevents theinformation in the EEPROM being overwritten if an OBCmalfunction occurs.

Table 28: BIUA Memories

9.11 Remote Inventory EEPROMThe Remote Inventory EEPROM stores PBA inventory information. The PBAinventory information includes items such as PBA manufacturing information,PBA identification and PBA history. Access to the Remote Inventory EEPROMis via the Remote Inventory Register (see Onboard Registers (Section 9.18.1)).

9.12 Local Qmux InterfaceThe local Qmux Interface provides local communication with the TSC. Itcomprises a number of buffers and drivers. The interface conforms to therequirements of RS-485. The local Qmux Interface is connected to channelA of the SCC.

9.13 Remote Qmux InterfaceThe remote Qmux Interface provides point-to-point communication with theTSCA PBA. The interface conforms to the requirements of RS-485. Themaximum operating speed is 2400 baud.

The remote Qmux information is inserted into, and extracted from, the Abisdata stream. The SRS performs this function. This mechanism providescommunication with a remote submultiplexer at the BTS site for the transfer ofQmux information.

9.14 Qmux Address InterfaceThis interface determines the address of the BIUA on the local Qmux bus via aplug on the BPA. The software can reprogram this address to match thenetwork configuration requirements.

124 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA

9.15 Man-Machine InterfaceThe MMI provides communication with a local maintenance device such as aPC (TSC Terminal). The MMI is connected to one channel of the SCC.

The MMI provides serial asynchronous communication at a speed of up to19200 baud. The baud rate is programmable from 50 to 19200 baud. AnI/O port bit detects the presence of TSC terminal. The interface conformsto RS-232.


9.16 LAPD InterfaceThe LAPD Interface provides O&M communication between the BIUA PBAand the TSCA PBA. The interface comprises a line driver and line receiverswhich connect the LAPD signal to and from SRS1.

The BIUA PBA inserts, and extracts, the LAPD information from one of theBSIs with a TCUC PBA.

9.17 Alarm InterfaceThe Alarm Interface provides for the connection of four external alarm signals.Each alarm input is connected to a local V.11 receiver. The receivers haveonboard polarization and termination resistors.

9.18 Control and Status RegistersThe control and status registers comprise:

Onboard Registers

TS0 Logic Registers

SCC Registers

TSSW Registers

SRS Registers.

9.18.1 Onboard Registers

There are five onboard registers:

GPR

ALR (Alarm Register)

RINVR

QAR

LAPD Register.

3BK 21239 AAAA TQZZA Ed.04 125 / 142

9 BIUA

9.18.1.1 GPRThe GPR is an 8-bit register that allows software control of the local QmuxInterface and the LEDs. It also allows the software to reset the BIUA PBA. Theused read/write bits of the GPR are:

LEDs 1 to 4, which each control one of the four LEDs mounted on the

front of the PBA

SW-Reset, which allows the software to reset the PBA

LQmux-EN, which disables or enables the local Qmux Interface.

9.18.1.2 ALRThe 8-bit ALR indicates the status of the external alarms.

9.18.1.3 RINVRThe RINVR is an 8-bit register that controls access to the Remote InventoryEEPROM. The following table describes the used bits of the RINVR.


OBC-SK RW Drives the clock signal of the Remote Inventory EEPROM.

OBC-CS RW Enables the Remote Inventory EEPROM when set (1).

OBC-PRE RW Enables the protected register when it is set (1).

OBC-DO RO Enables the Remote Inventory EEPROM data outputs.

OBC-IAE RO Indicates whether the Remote Inventory EEPROM can be accessed by the OBC.

CLKS2andCLKS1

RO Indicate the status of the selected clock.

Table 29: RINVR Bits BIUA PBA

126 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA

9.18.1.4 QARThe QAR is an 8-bit register that indicates the Qmux address and the statusof a number of alarms and signals. The following table describes the usedbits of the QAR.


QMA0 - 4 RO Indicate the local Qmux address.

MTPR RO Indicates whether the status of the PBA, i.e., test mode or operational.

OUTRNG RO Indicates that a synchronization alarm (out-of-range detected) has occurred.

DSR RO Indicates the status of the MMI, i.e., terminal connected/not connected to the PBA.

Table 30: QAR Bits

9.18.1.5 LAPD RegisterThe LAPD Register controls the LAPD information flow and some local PBAfunctions. The following table describes the used bits of the LAPD register.


LAPDC0,LAPDC1

RW Controls the LAPD data extraction and insertion functions performed by the SRSs.

REEN RW Controls the remote Qmux interface transmitter.

TEEN RW Enables the long range timer.

PITMSK RW Enables the watchdog timer.

Table 31: LAPD Register Bits

3BK 21239 AAAA TQZZA Ed.04 127 / 142

9 BIUA

9.18.2 TS0 Logic Registers

The TS0 Logic Registers control the operations of the TS0 Logic.

They comprise:

Link Register, which indicates the FEA bit corresponding to the Ater MuxInterface to the TS0 Logic.

Mode Register, which indicates the rate at which the Qmux information is

sampled:

No sampling

4 kHz sampling

8 kHz sampling

16 kHz sampling.

Selection Register, which indicates the SRS that is connected to TSSW3 toallow switching of the TCHs

Mask Register, which selects the TCC output that is connected to the

TSSWs.


There are four registers via which the OBC controls the SCC:

B Channel Control

A Channel Control

B Channel Data

A Channel Data.

Each register controls the associated channel or data.

9.18.4 TSSW Registers

There are eight registers via which the OBC controls the TSSWs:

TSSWx Control Register (x = 1 to 4)

TSSWx Channel Register.

9.18.5 SRS Registers

There are four groups of registers via which the OBC controls the SRSs.Each group of registers controls the operation of the associated SRS andthe functions it performs.

128 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA



At power-on






Timer 0 of a PIT provides the Watchdog function. The Watchdog timeout can beprogrammed from 4.096 ms to approximately 4.5 minutes in steps of 4.096 ms.

9.20 Long Range TimerTimers 1 and 2 of the timer circuit, connected in cascade, provide a long rangetimer. When this timer expires, it generates an OBC interrupt.

9.21 O&MThis section describes the O&M facilities provided on the BIUA.

It comprises:

LEDs

Push Button

Replacement.

3BK 21239 AAAA TQZZA Ed.04 129 / 142

9 BIUA

9.21.1 LEDs


LED Description

4 Indicates a Prompt Maintenance Alarm, and is litwhen:



A PMA is generated.


1 and 2 When flashing (normal condition), indicate that theOBC is active.

Table 32: BIUA LED Description

9.21.2 Push Button


9.21.3 Replacement





130 / 142 3BK 21239 AAAA TQZZA Ed.04

9 BIUA



Power Supply

The BIUA operates from a +5 V +/-5% supply.

Front Panel

Turn−button Latch

Turn−button Latch

LED 1 (Red)

LED 2 (Red)

LED 3 (Red)

LED 4 (Red)

Push Button

9−pin Connector


Figure 41: BIUA Front Panel

3BK 21239 AAAA TQZZA Ed.04 131 / 142

9 BIUA

132 / 142 3BK 21239 AAAA TQZZA Ed.04

10 TSCA

10 TSCA

This section describes the hardware architecture of the TSCA PBA.

3BK 21239 AAAA TQZZA Ed.04 133 / 142

10 TSCA

10.1 IntroductionThe following figure shows a simplified diagram of the hardware architectureof the TSCA PBA.

Local Qmux Interface 4B

MMI

LAPD Interface

ChB

ChA

SCC1

LEDs

ChB

ChA

SCC2


Memory

MemoryMemory

Controller and Register Unit

Remote Qmux

RS−232 Interface

Local Qmux

LAPD Interface

Remote Inventory

Local Qmux Interface 4A

Remote Qmux Interface 3A

Remote Qmux Interface 3B



ChB

ChA

SCC3




Watchdog Reset Unit

Watchdog Reset

TSCA

Figure 42: TSCA PBA Simplified Hardware Architecture

10.2 Onboard ControllerThe OBC manages the local operation and maintenance of the TSCA PBA.

The OBC:

Provides local control of the TSCA PBA

Initializes the PBA

Runs the self-test.

134 / 142 3BK 21239 AAAA TQZZA Ed.04

10 TSCA

10.3 MemoryThe following table describes the four types of memory on the TSCA PBA.

Circuit Description

FLASH EPROM The FLASH EPROM comprises 2.048 Mbytes organizedinto 32 pages, each of 64 kbytes. An FEPROM, known asthe Boot FEPROM, stores:

Booting routines

Elementary routines to provide communication with the

TSC Terminal

Programming routines to reprogram the FLASH

EPROMs of the TSCA PBA.

All the operational software can be download and storedin the FEPROMs

DRAM The 2 Mbytes DRAM stores volatile information such asvariables and buffers used in the firmware. The DRAM isorganized into 32 x 64 kbytes banks.

SRAM The 128 kbytes SRAM stores the interrupt vectors.

EEPROM The EEPROM stores PBA settings such as systemconfiguration and error counters. It provides 32 kbytes ofnon-volatile memory.

Table 33: TSCA Memories

10.4 Memory Controller and Register UnitThe Memory Controller and Register Unit is an Erasable ProgrammableLogic Device.

This device performs:

DRAM control functions

Parity checks on the DRAM

Selects the FLASH EPROM and DRAM banks.

In addition, the device provides the onboard registers. Onboard Registers(Section 10.14) describes these registers.

3BK 21239 AAAA TQZZA Ed.04 135 / 142

10 TSCA

10.5 Serial Communication ControllersThere are three SCCs on the TSCA PBA. The SCC is a dual channel,multi-protocol communication controller. It functions as a serial-to-paralleland as a parallel-to-serial converter/controller. Two independent full-duplexchannels (A and B) are programmed for asynchronous data communication.

10.5.1 SCC1

The two channels of SCC1 are:

Channel A, which provides the Local Qmux Interface links

Channel B, which provides connections to Remote Qmux Interfaces 3Aand 3B.

10.5.2 SCC2


Channel A, which provides the LAPD link


10.5.3 SCC3


Channel A, which provides connection to Remote Qmux Interfaces 2Aand 2B

Channel B, which provides connections to Remote Qmux Interfaces 1A

and 1B.

10.6 Local Qmux InterfacesThere are two local Qmux Interfaces. These interfaces provide localcommunication with the transmission elements on the same site. Eachinterface comprises a number of buffers and drivers. The interfaces conform tothe requirements of RS-485. Each interface is polled alternately.

The local Qmux Interfaces are connected to channel A of SCC1. The baud rateis programmable at 1 200 or 2 400 bauds.

136 / 142 3BK 21239 AAAA TQZZA Ed.04

10 TSCA

10.7 Remote Qmux InterfacesThere are six remote Qmux Interfaces. These interfaces provide communicationwith the transmission elements at remote sites. Each Interface comprises anumber of buffers and drivers. The interfaces conform to the requirements ofRS-485. Only three interfaces are active at a time.

Remote Qmux Interfaces 3A and 3B are connected to channel B of SCC1.

The other Remote Qmux Interfaces are connected to SCC3 as follows:

2A and 2B are connected to channel A

1A and 1B are connected to channel B.

The baud rate is programmable at 1 200 or 2 400 bauds.

10.8 Man-Machine InterfaceThe MMI provides communication with a local maintenance device such as aPC (TSC Terminal). The MMI is connected to channel B of SCC2.

The MMI provides serial asynchronous communication at a speed of up to19 200 bauds. The baud rate is programmable from 50 to 19 200 bauds. AnI/O port bit detects the presence of TSC terminal. The interface conformsto RS-232.


10.9 LAPD InterfaceThe LAPD interface provides O&M communication between the TSCA PBAand the TCUC PBAs. This communication is via the BIUA PBA. The LAPDinterface comprises a line driver and line receivers which connect the LAPDsignal to and from channel A of SCC2. Channel A of SCC2 operates in theHDLC-oriented synchronous mode.

Data is transferred between channel A of SCC2 and the memory by two DMAchannels. These channels are an integral part of the OBC. DMA channel 1transfers transmit data. DMA channel 0 transfers receive data. The receivedLAPD signal is monitored to detect the presence of the LAPD clock.

10.10 Remote Inventory EEPROMThe Remote Inventory EEPROM stores PBA inventory information. ThePBA inventory information includes items such as PBA manufacturing, PBAidentification and PBA history. Access to the Remote Inventory EEPROM isvia the Remote Inventory Register (see Remote Inventory Register (Section10.14.7)).

3BK 21239 AAAA TQZZA Ed.04 137 / 142

10 TSCA



At power-on






Timer 0 of a PIT provides the Watchdog function. The Watchdog timeout can beprogrammed from 4.096 ms to approximately 4.5 minutes in steps of 4.096 ms.

10.12 Long Range TimerTimers 1 and 2 of the timer circuit, connected in cascade, provide a long rangetimer. When this timer expires, it generates an OBC interrupt.

10.13 Test LoopsTwo test loops are provided to allow the PBA to be tested in the system:

Self-test

Extended Test.

10.13.1 Self-test

The self-test allows testing of the PBA without the external interfaces, e.g.,memory testing and SCC testing.

Disabling the drivers of the external interfaces during testing prevents databeing transmitted on these interfaces. Individual serial channels of each SCCcan be disabled. All the serial channels can be looped back internally on thePBA by activating the internal loopback of the SCCs.

10.13.2 Extended Test

The extended test provides testing of the external interfaces. Loop cables mustbe connected to the external interfaces before the extended test is performed.

138 / 142 3BK 21239 AAAA TQZZA Ed.04

10 TSCA

10.14 Onboard RegistersThe onboard registers comprise:

SCC Registers

DRAM Bank Select Register

FLASH EPROM Bank Select Register

Control and Status Register

Wait State Register

Parity Location Registers

Remote Inventory Register

LED Register.


There are three groups of registers via which the OBC controls the SCCs. Eachgroup controls the operations of an associated SCC.

Each group comprises:

B Channel Control

A Channel Control

B Channel Data

A Channel Data.

10.14.2 DRAM Bank Select Register

Six read/write bits of the 8-bit DRAM Bank Select Register determine which ofthe DRAM banks is selected.

10.14.3 FLASH EPROM Bank Select Register

Five read/write bits of the 8-bit FLASH EPROM Bank Select Register determinewhich of the FLASH EPROM banks is selected.

3BK 21239 AAAA TQZZA Ed.04 139 / 142

10 TSCA

10.14.4 Control and Status Register

The Control and Status Register allows the OBC to:

Read the status of the LAPD signal

Read the status of the MMI, i.e., terminal connected/not connected tothe PBA

Read the status of the PBA, i.e., test mode or operational

Reset the PBA

Control access to the FLASH EPROM banks

Enable and disable parity checking during memory accesses

Enable and disable the LAPD link

Read the status of the DRAM during an access, i.e., parity error or parity OK.

10.14.5 Wait State Register

The Wait State Register allows the OBC to:

Control the number of DRAM wait states

Control the number of FEPROM wait states.

10.14.6 Parity Location Registers

The Parity Location Registers store the address where a parity error hasbeen detected.

10.14.7 Remote Inventory Register

The RINVR:

Drives the clock signal of the Remote Inventory EEPROM

Enables and disables the Remote Inventory EEPROM

Enables and disables the protected register

Enables and disables the Remote Inventory EEPROM data outputs

Indicates whether the Remote Inventory EEPROM can be accessed by

the OBC

Enables and disables the OBC Interface.

10.14.8 LED Register

The LED Register controls the four LEDs on the front panel. In addition,it indicates the highest nibble of the address where a parity error has beendetected.

140 / 142 3BK 21239 AAAA TQZZA Ed.04

10 TSCA

10.15 O&MThis section describes the O&M facilities provided on the TSCA.

It comprises:

LEDs

Push Button

Replacement.

10.15.1 LEDs


LED Description

4 Indicates a Prompt Maintenance Alarm, and is litwhen:



A PMA is generated.


1 and 2 When flashing (normal condition), indicate that theOBC is active.

Table 34: TSCA LED Description

10.15.2 Push Button


10.15.3 Replacement





3BK 21239 AAAA TQZZA Ed.04 141 / 142

10 TSCA

10.16 Physical DescriptionDimensions Refer to Common Information (Section 1.2) .

Power Supply The TSCA operates from a +5 V +/-5% supply.

Front Panel

Turn−button Latch

Turn−button Latch

LED 1 (Red)

LED 2 (Red)

LED 3 (Red)

LED 4 (Red)

Push Button

9−pin Connector


Figure 43: TSCA Front Panel

142 / 142 3BK 21239 AAAA TQZZA Ed.04

Evolium BSC Hardware Description

Documents

Transcript of Evolium BSC Hardware Description