EVB-LAN9252-HBI+ EtherCAT Evaluation Board User's GuideEVB-LAN9252-HBI+ ETHERCAT® EVALUATION BOARD...

2015-2016 Microchip Technology Inc. DS50002333C

EVB-LAN9252-HBI+

EtherCAT® Evaluation BoardUser’s Guide

DS50002333C-page 2 2015-2016 Microchip Technology Inc.

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ISBN: 9781522406839

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2015-2016 Microchip Technology Inc. DS50002333C-page 3

EVB-LAN9252-HBI+ EtherCAT® Evaluation Board User’s Guide

NOTES:


EVB-LAN9252-HBI+ETHERCAT® EVALUATION BOARD

USER’S GUIDE

Table of Contents

Preface ........................................................................................................................... 7Introduction............................................................................................................ 7

Document Layout .................................................................................................. 7

Conventions Used in this Guide ............................................................................ 8

The Microchip Web Site ........................................................................................ 9

Development Systems Customer Change Notification Service ............................ 9

Customer Support ................................................................................................. 9

Document Revision History ................................................................................. 10

Chapter 1. Overview1.1 Introduction ................................................................................................... 111.2 References ................................................................................................... 131.3 Terms and Abbreviations ............................................................................. 13

Chapter 2. Board Details & Configuration2.1 Power ........................................................................................................... 14

2.1.1 +5V Power ................................................................................................. 14

2.2 Resets .......................................................................................................... 142.2.1 Power-on Reset ......................................................................................... 142.2.2 Reset Out .................................................................................................. 142.2.3 GPIO Reset ............................................................................................... 14

2.3 Clock ............................................................................................................ 152.4 Configuration ................................................................................................ 15

2.4.1 Strap Options ............................................................................................ 162.4.2 LED Indicators ........................................................................................... 182.4.3 EEPROM Switch ....................................................................................... 192.4.4 DIGIO/HBI/SPI+GPIO Selection ................................................................ 192.4.5 SoC ........................................................................................................... 23

2.5 DIGIO & SPI+16GPIO Signals on P1 and P2 Headers ................................ 252.5.1 DIGIO on P1 and P2 Headers (up to 16 bits supported) ........................... 252.5.2 SPI+GPIO on P1 and P2 Headers (up to 16 bits supported) .................... 26

2.6 Additional Features ...................................................................................... 272.6.1 Potentiometer ............................................................................................ 272.6.2 Temperature Sensor ................................................................................. 272.6.3 UART RS-232 ........................................................................................... 272.6.4 DAC ........................................................................................................... 27

2.7 Limitations .................................................................................................... 272.8 Mechanicals ................................................................................................. 28

Chapter 3. Software Development Kit3.1 Prerequisites ................................................................................................ 29



3.1.1 Hardware Requirements ............................................................................293.1.2 Software Requirements .............................................................................29

3.2 ESC SDK Sample Overview ........................................................................ 293.2.1 User Module ...............................................................................................303.2.2 EtherCAT® Slave Stack .............................................................................303.2.3 Hardware Abstraction Layer (HAL) ............................................................30

3.3 Using the Sample Project ............................................................................. 313.3.1 MPLAB IDE Project Settings & Firmware Download .................................313.3.2 Compiling and Programming SoC Firmware .............................................33

3.4 Programming the LAN9252 EEPROM ......................................................... 343.4.1 Programming LAN9252 EEPROM using the TwinCAT Master Tool .........34

Appendix A. Evaluation Board PhotoA.1 Introduction .................................................................................................. 37

Appendix B. Evaluation Board SchematicsB.1 Introduction .................................................................................................. 38

Appendix C. Bill of Materials (BOM)C.1 Introduction .................................................................................................. 49

Worldwide Sales and Service .....................................................................................54



USER’S GUIDE

Preface

INTRODUCTION

This chapter contains general information that will be useful to know before using the EVB-LAN9252-HBI+. Items discussed in this chapter include:

• Document Layout

• Conventions Used in this Guide

• The Microchip Web Site

• Development Systems Customer Change Notification Service

• Customer Support

• Document Revision History

DOCUMENT LAYOUT

This document describes how to use the EVB-LAN9252-HBI+ as a development tool for the Microchip LAN9252 EtherCAT® slave controller. The manual layout is as follows:

• Chapter 1. “Overview” – Shows a brief description of the EVB-LAN9252-HBI+.

• Chapter 2. “Board Details & Configuration” – Includes details and instructions for using the EVB-LAN9252-HBI+.

• Chapter 3. “Software Development Kit” – Includes details and instructions for using the LAN9252 EtherCAT® slave stack firmware and SDK framework.

• Appendix A. “Evaluation Board Photo” – This appendix shows the EVB-LAN9252-HBI+.

• Appendix B. “Evaluation Board Schematics” – This appendix shows the EVB-LAN9252-HBI+ schematics.

• Appendix C. “Bill of Materials (BOM)” – This appendix includes the EVB-LAN9252-HBI+ Bill of Materials (BOM).

NOTICE TO CUSTOMERS

All documentation becomes dated, and this manual is no exception. Microchip tools and documentation are constantly evolving to meet customer needs, so some actual dialogs and/or tool descriptions may differ from those in this document. Please refer to our web site (www.microchip.com) to obtain the latest documentation available.

Documents are identified with a “DS” number. This number is located on the bottom of each page, in front of the page number. The numbering convention for the DS number is “DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the document.

For the most up-to-date information on development tools, see the MPLAB® IDE online help. Select the Help menu, and then Topics to open a list of available online help files.



CONVENTIONS USED IN THIS GUIDE

This manual uses the following documentation conventions:

DOCUMENTATION CONVENTIONS

Description Represents Examples

Arial font:

Italic characters Referenced books MPLAB® IDE User’s Guide

Emphasized text ...is the only compiler...

Initial caps A window the Output window

A dialog the Settings dialog

A menu selection select Enable Programmer

Quotes A field name in a window or dialog

“Save project before build”

Underlined, italic text with right angle bracket

A menu path File>Save

Bold characters A dialog button Click OK

A tab Click the Power tab

N‘Rnnnn A number in verilog format, where N is the total number of digits, R is the radix and n is a digit.

4‘b0010, 2‘hF1

Text in angle brackets < > A key on the keyboard Press <Enter>, <F1>

Courier New font:

Plain Courier New Sample source code #define START

Filenames autoexec.bat

File paths c:\mcc18\h

Keywords _asm, _endasm, static

Command-line options -Opa+, -Opa-

Bit values 0, 1

Constants 0xFF, ‘A’

Italic Courier New A variable argument file.o, where file can be any valid filename

Square brackets [ ] Optional arguments mcc18 [options] file [options]

Curly brackets and pipe character: { | }

Choice of mutually exclusive arguments; an OR selection

errorlevel {0|1}

Ellipses... Replaces repeated text var_name [, var_name...]

Represents code supplied by user

void main (void){ ...}


Preface

THE MICROCHIP WEB SITE

Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.

To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.

The Development Systems product group categories are:• Compilers – The latest information on Microchip C compilers, assemblers, linkers

and other language tools. These include all MPLAB C compilers; all MPLAB assemblers (including MPASM assembler); all MPLAB linkers (including MPLINK object linker); and all MPLAB librarians (including MPLIB object librarian).

• Emulators – The latest information on Microchip in-circuit emulators.This includes the MPLAB REAL ICE and MPLAB ICE 2000 in-circuit emulators.

• In-Circuit Debuggers – The latest information on the Microchip in-circuit debuggers. This includes MPLAB ICD 3 in-circuit debuggers and PICkit 3 debug express.

• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows Integrated Development Environment for development systems tools. This list is focused on the MPLAB IDE, MPLAB IDE Project Manager, MPLAB Editor and MPLAB SIM simulator, as well as general editing and debugging features.

• Programmers – The latest information on Microchip programmers. These include production programmers such as MPLAB REAL ICE in-circuit emulator, MPLAB ICD 3 in-circuit debugger and MPLAB PM3 device programmers. Also included are nonproduction development programmers such as PICSTART Plus and PIC-kit 2 and 3.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support


www.microchip.com

http://www.microchip.com


Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at: http://www.microchip.com/support

DOCUMENT REVISION HISTORY

Revision Section/Figure/Entry Correction

DS50002333C (06-17-16) All Updated board name to “EVB-LAN9252-HBI+” throughout document.

Figure 1-1 Updated figure to include UART, Temp. Sensor, DAC, and ADC.

Chapter 2. “Board Details & Configuration”

Updated Figures 1, 5, 6, 7, and 10. Added new Fig-ure 2.

Updated Tables 13, 14, 15, 21.

2.1.1 “+5V Power” Removed power supply manufacturer and part num-ber.

2.6 “Additional Features” Added new section with new features.

Chapter 3. “Software Development Kit”

Updated figures throughout chapter.

Appendix A. “Evaluation Board Photo”

Updated appendix with new photos.

Appendix B. “Evaluation Board Schematics”

Updated appendix with new schematics.

Appendix C. “Bill of Materials (BOM)”

Updated appendix with updated BOM.

DS50002333B (05-12-15) All Updated board name to “EVB-LAN9252-HBI” throughout document, corrected misc. typos and grammatical errors.

Section 1.2 “References” Updated list of application notes.

Section 2.4.4 “DIGIO/HBI/SPI+GPIO Selection”

Added additional information on DIGIO mode.

Table 2-13, Table 2-14, and Table 2-15

Simplified table and added note under each table for clarity.

DS50002333A (02-27-15) Initial Release of Document


http://www.microchip.com/support

http://www.microchip.com/support


USER’S GUIDE

Chapter 1. Overview

1.1 INTRODUCTION

The LAN9252 is a 2-port EtherCAT® Slave Controller (ESC) with dual integrated Ether-net PHYs which each contain a full-duplex 100BASE-TX transceiver and support 100Mbps (100BASE-TX) operation. 100BASE-FX is supported via an external fiber transceiver.

Each port receives an EtherCAT® frame, performs frame checking and forwards it to the next port. Time stamps of received frames are generated when they are received. The Loop-back function of each port forwards the frames to the next logical port if there is either no link at a port, if the port is not available, or if the loop is closed for that port. The Loop-back function of port 0 forwards the frames to the EtherCAT® Processing Unit. The loop settings can be controlled by the EtherCAT® master.

Packets are forwarded in the following order:

Port 0 -> EtherCAT® Processing Unit -> Port 1 -> Port 2.

The EtherCAT® Processing Unit (EPU) receives, analyzes and processes the Ether-CAT® data stream. The main purpose of the EtherCAT® Processing unit is to enable and coordinate access to the internal registers and the memory space of the ESC, which can be addressed both from the EtherCAT® master and from the local applica-tion. Data exchange between master and slave applications is comparable to a dual-ported memory (process memory), enhanced by special functions for consistency checking (SyncManager) and data mapping (FMMU). Each FMMU performs bitwise mapping of logical EtherCAT® system addresses to physical device addresses.

The scope of this document is to describe the EVB-LAN9252-HBI+ setup, which sup-ports a HBI/SPI+GPIO Interface and corresponding jumper configurations. The LAN9252 is connected to an RJ45 Ethernet jack with integrated magnetics for 100BASE-TX connectivity. A simplified block diagram of the EVB-LAN9252-HBI+ is shown in Figure 1-1.



FIGURE 1-1: EVB-LAN9252-HBI+ BLOCK DIAGRAM

MicrochipLAN9252

EEPROM

EVB-LAN9252-HBI+

100BASE-TX Ethernet

Magnetics & RJ45

100BASE-TX Ethernet

Magnetics & RJ45

StrapsPort 0 Port 1

Crystal

Power Supply Module

Ethernet Ethernet

5V

HBI or SPI+GPIO Selection

HBI Mode Selection

Board to Board Connector

Board to Board Connector

Onboard Soc PIC32MX795F512L

SPI/SQI/I2C AARDVARK

Fiber-SFP

Port 0

Fiber-SFP

Port 1

UART TempSensor DAC ADC


Overview

1.2 REFERENCES

Concepts and material available in the following documents may be helpful when read-ing this document. Visit www.microchip.com for the latest documentation.

• LAN9252 Data Sheet

• AN 8.13 Suggested Magnetics

• EVB-LAN9252-HBI+ Schematics

• The following application notes:

- AN1916 Integrating Microchip’s LAN9252 SDK with Beckhoff’s EtherCAT® SSC

- AN1920 Microchip LAN9252 EEPROM Configuration and Programming

- AN1907 Microchip LAN9252 Migration from Beckhoff ET1100

1.3 TERMS AND ABBREVIATIONS

IDE - Integrated Development Environment

ESC - EtherCAT® Slave Controller

EVB - Engineering Validation Board

HAL - Hardware Abstraction Layer

HBI - Host Bus Interface

SPI - Serial Protocol Interface

SSC - Slave Stack Code



USER’S GUIDE

Chapter 2. Board Details & Configuration

This chapter includes sub-sections on the following EVB-LAN9252-HBI+ details:

• Power

• Resets

• Clock

• Configuration

• Additional Features

• Limitations

• Mechanicals

2.1 POWER

2.1.1 +5V Power

Power is supplied to the LAN9252 by a +3.3V on-board regulator, which is powered by a +5V external wall adapter. The LAN9252 includes an internal +1.2V regulator which supplies power to the internal core logic. Assertion of the D1 Green LED indicates suc-cessful generation of +3.3V o/p. The SW1 switch must be in the ON position for the +5V to power the +3.3V regulator.

2.2 RESETS

2.2.1 Power-on Reset

A power-on reset occurs whenever power is initially applied to the LAN9252 or if the power is removed and reapplied to the LAN9252. This event resets all circuitry within the LAN9252. After initial power-on, the LAN9252 can be reset by pressing the reset switch SW2. The reset LED D2 will assert (red) when the LAN9252 is in reset condition. For stability, a delay of approximately 180ms is added from the +3.3V o/p to reset release.

2.2.2 Reset Out

The LAN9252 reset pin can be configured as an output to reset the SoC. The RST# pin becomes an open-drain output and is asserted for the minimum required time of 80ms.

2.2.3 GPIO Reset

The EVB-LAN9252-HBI+ provides the option to reset the LAN9252 through a PIC GPIO pin [95(RG14)]. The SW10 switch is used for this selection, as shown in Table 2-1.

TABLE 2-1: RESET CONFIGURATION SWITCH

Switch Short Pins Knob Position Function

SW10 1-3 1-2 System Reset (SYS_RESETN) (Default)

SW10 1-2 1-3 GPIO Reset (RST_GPIO)


Board Details & Configuration

2.3 CLOCK

The EVB-LAN9252-HBI+ utilizes an external 25MHz 25ppm crystal from Cardinal Components Inc. (P/N: CSM1Z-A5B2C5-40-25.0D18-F).

2.4 CONFIGURATION

The following sub-sections describe the various board features and configuration set-tings. A top view of the EVB-LAN9252-HBI+ is shown in Figure 2-1. Figure 2-2 details new features.

FIGURE 2-1: EVB-LAN9252-HBI+ TOP VIEW WITH CALLOUTS



FIGURE 2-2: EVB-LAN9252-HBI+ TOP VIEW NEW FEATURE CALLOUTS

2.4.1 Strap Options

2.4.1.1 CHIP MODE SELECTION

Table 2-2 details the LAN9252 chip mode configuration straps.

2.4.1.2 EEPROM SIZE CONFIGURATION

The EEPROM size configuration strap (J5 & J8) determines the supported EEPROM size range. A low selects 1Kbits (128 x 8) through 16Kbits (2K x 8)_24C16. A high selects 32Kbits (4K x 8) through 512Kbits (64K x 8) or 4Mbits (512K x 8)_24C512.

2.4.1.3 COPPER AND FIBER STRAPS

The LAN9252 supports 100BASE-TX (Copper) and 100BASE-FX (Fiber) modes. In 100BASE-FX operation, the presence of the receive signal is indicated by the external transceiver as either an open-drain, CMOS level, Loss of Signal (SFP) or a LVPECL Signal Detect (SFF).

TABLE 2-2: CHIP MODE CONFIGURATION STRAP

Header Description Pins Settings

J4,J6,J7,J9 Chip mode configuration strap inputs. This strap determines the number of active ports and port types.

1-2

2-3

Short 1-2 for high (pull-up) (Not supported in this EVB)Short 2-3 for low (pull-down) (default)

Note: This EVB supports Chip mode 00 which is 2-port mode, where Port 0 = PHY A and Port 1 = PHY B. This requires J4, J6, J7, and J9 to be pulled-down (2-3) shorted. All other configurations are not supported with this EVB.

TABLE 2-3: EEPROM SIZE CONFIGURATION STRAP

Header Description Pins Settings

J5, J8 EEPROM size configuration strap inputs. This strap deter-mines the supported EEPROM size range.

1-22-3

Short 1-2 for high (pull-up) (default)Short 2-3 for low (pull-down)



This EVB supports 100BASE-TX (Copper) and SFP 100BASE-FX (Fiber) modes. By default Copper Mode is active. Fiber Mode is supported as an assembly option. To select the Copper or Fiber Mode, the respective strap and signal routing resister assembly options must to be configured.

2.4.1.3.1 Copper Mode

The EVB-LAN9252-HBI+ is set to Copper Mode by default. Table 2-4 details the required strap resistor settings for Copper Mode operation.

Additionally, the signal routing resistors detailed in Table 2-5 must be assembled for Copper Mode operation.

2.4.1.3.2 Fiber Mode

The EVB-LAN9252-HBI+ support SFP type 100BASE-FX. To enable Fiber Mode, the respective strap and signal routing resistors must be configured.

Table 2-6 details the required strap resistor settings for Fiber Mode operation.

Additionally, the signal routing resistors detailed in Table 2-7 must be assembled for Fiber Mode operation.

Note: Vendor part number for SFP: Finisar/FTLF1217P2

TABLE 2-4: COPPER MODE STRAP RESISTORS

Resistors Description

R79 (10K) Configures Port 0 & 1 to Copper Mode

R76, R80 (10K) Configures Port 0 and Port 1 to Copper Mode, respectively

Note: R75, R77, and R78 must not be populated (DNP).

TABLE 2-5: COPPER MODE SIGNAL ROUTING RESISTORS


R17, R19, R21, R23 Port 0 Copper Mode enabled

R31, R33, R35, R37 Port 1 Copper mode enabled

Note: R16, R18, R20, R22, R30, R32, R34, and R36 (0402 package) must not be populated (DNP).

Note: Copper Mode related resistors must be DNP while Fiber Mode is active (See Section 2.4.1.3.1 “Copper Mode”).

TABLE 2-6: FIBER MODE STRAP RESISTORS


R77 (10K) Configures Port 0 & 1 to FX-LOS Mode

R75, R78 (10K) Configures Port 0 and Port 1 to Fiber Mode, respectively

Note: R76, R79, and R80 must not be populated (DNP).

TABLE 2-7: FIBER MODE SIGNAL ROUTING RESISTORS


R16, R18, R20, R22 Port 0 Fiber Mode enabled

R30, R32, R34, R36 Port 1 Fiber mode enabled



2.4.1.3.3 FX-LOS Fiber Mode Strap

FX-LOS strap details are shown in Table 2-8. These strap settings determine if the ports are to operate in FX-LOS Fiber Mode or FX-SD/Copper Mode.

2.4.2 LED Indicators

The D3 and D4 LEDs are used to indicate the Link/Activity status on the corresponding EVB ports, as detailed in Table 2-9. The Link/Act LED should be ON at each port when the cable is present. If the Link/Act LED is not ON, it indicates there is an issue with the connection or cable.

Additionally, the D5 LED is used as a RUN indicator (green) to show the AL status of the EtherCAT® State Machine (ESM), as detailed in Table 2-10.

Note: R17, R19, R21, R23, R31, R33, R35, and R37 (0402 package) must not be populated (DNP).

TABLE 2-8: FX-LOS MODE STRAP SETTINGS

R77 (10K) R79 (10K)Reference Voltage (V)

Function

Populate DNP 3.3 A level above 2V selects FX-LOS for Port 0 and Port 1

Populate Populate 1.5 A level greater than 1.5V and below 2V selects FX-LOS for Port 0 and FX-SD / copper twisted pair for Port 1, further determined by FXSDB

DNP Populate 0 (Default) A level of 0V selects FX-SD / copper twisted pair for Ports 0 and 1, further determined by FXSDA and FXSDB

Note: The above strap details describe the LAN9252 function. This EVB does not support SFF Fiber Mode. Therefore, FX-SD related straps are not applica-ble.

TABLE 2-9: D3 AND D4 LINK/ACTIVITY LED STATUS INDICATORS

State Description

Off Link is down

Flashing Green Link is up with activity

Steady Green Link is up with no activity

TABLE 2-10: D5 RUN LED STATUS INDICATOR

State Description

Off The device is in the INITIALIZATION state

Blinking (on 200ms, off 200ms) The device is in the PRE-OPERATIONAL state

Single Flash (on 200ms, off 1000ms) The device is in the SAFE-OPERATIONAL state

On The device is in the OPERATIONAL state

Flickering (on 50ms, off 50ms) The device is booting and has not yet entered the INITIALIZATION state, or the device is in the BOOTSTRAP state and firmware download is in progress. (Optional. Off when not implemented.)



2.4.3 EEPROM Switch

The EVB-LAN9252-HBI+ utilizes 0x50 (7-bit) I2C slave addressing. The SW3 switch can be used to select the A0, A1, and A2 address bits, as shown in Figure 2-3 and Table 2-11. The eighth bit of the slave address determines if the master device wants to read or write to the EEPROM (24FC512).

FIGURE 2-3: SLAVE ADDRESS ALLOCATION

2.4.4 DIGIO/HBI/SPI+GPIO Selection

The EVB-LAN9252-HBI+ supports three LAN9252 configurations:

• DIGIO Mode

• HBI Mode

• SPI + 16 GPIO Mode

DIGIO and HBI modes use the same switch configuration. The DIGIO/HBI or SPI+GPIO configuration is selected using the DPDT SW11 to SW21 switches. By default, the EVB is set to DIGIO mode and no code is programmed to the on-board PIC32MX. In DIGIO mode, headers P1 and P2 can be used to probe the input and out-put control signals. It is not possible to configure the input or see to output on the LED on the EVB. Refer to Table 2-22 for a mapping of the DIGIO signals on the P1 and P2 headers.

TABLE 2-11: EEPROM SWITCH

Switch Description Settings

SW3 I2C EEPROM address selection switch (A0, A1, A2). See Figure 2-3.

ON for logic 0 (default)OFF for logic 1

R/W AA1 A00 A20 11

Start Read/Write

Slave Address

Note: The PDI configuration which is selected in hardware must match with the PDI configuration that is chosen in the EtherCAT SDK during the SSC inte-gration process. An appropriate PDI configuration must be set in the ESC configuration area of the EEPROM.

TABLE 2-12: HBI/SPI+GPIO SWITCH CONFIGURATIONS

Switch Description Settings

SW11 to SW21 Up DIGIO/HBI Mode (Default)

SW11 to SW21 Down SPI+GPIO Mode



FIGURE 2-4: SW11-SW21 DIGIO/HBI/SPI+GPIO MODE SELECTION

2.4.4.1 HBI MODE SELECTION

The LAN9252 supports six HBI modes. These six HBI modes (Multiplexed Modes and Indexed Modes) can be selected using the SPST switches (P/N: 450301014042-Wurth Electronics) SW5 through SW9 and SW22 through SW25. Through the switches the LAN9252 HBI signals are connected to the SoC.

2.4.4.1.1 Multiplexed Modes

The following four HBI Multiplexed Modes are supported:

1. 8-bit Multiplexed single-phase mode

2. 16-bit Multiplexed single-phase mode

3. 8-bit Multiplexed dual-phase mode

4. 16-bit Multiplexed dual-phase mode

Each HBI Multiplexed Mode requires an updated ESI file, EEPROM and PDI driver with configured SSC to be programmed to the PIC32MX. For additional software informa-tion, refer to Chapter 3. “Software Development Kit”.

Figure 2-5 details the switch selection for Multiplexed Mode. All four Multiplexed Modes utilize the same switch positions.

FIGURE 2-5: MULTIPLEXED HBI MODE SELECTION

Table 2-13 details the switch selection for Multiplexed Mode.

DIGIO/HBI Mode

SPI+GPIO Mode

Note: For switch P/N: 450301014042, pin 1 is at the middle of the switch. To short 1-2, knob position must be in the 1-3 position, and vice versa.

TABLE 2-13: MULTIPLEXED HBI MODE SELECTION

Switch Switch Knob Position Start Destination

SW5 Down A0_AD15 A0_CONFIG3

SW6 Up RD_RDWR GPMC_DIR

SW7 Down ALELO_A1 A1_CONFIG3

SW8 Down WR_ENB GPMC_DE0N_CLE

SW9 Down ALEHI_A2 A2_CONFIG3

SW24 Up A0_CONFIG3 GPMC_A0_ALE

SW25 Up A1_CONFIG3 GPMC_A1_ALEHI



2.4.4.1.2 Indexed Mode

There are 2 different Indexed modes, 8-bit and 16-bit. Each HBI Indexed Mode requires an updated ESI file, EEPROM and PDI driver with configured SSC to be programmed to the PIC32MX. For additional software information, refer to Chapter 3. “Software Development Kit”.

8-Bit Indexed Mode

Figure 2-6 details the switch selection for 8-Bit Indexed Mode.

FIGURE 2-6: 8-BIT INDEXED HBI MODE SELECTION

Table 2-14 details the switch selection for 8-bit Indexed HBI Mode.

16-Bit Indexed Mode

Figure 2-7 details the switch selection for 16-Bit Indexed Mode.

FIGURE 2-7: 16-BIT INDEXED HBI MODE SELECTION

Note: When the switch knob is in the down position, pins 1-2 are shorted and the dot on the switch can be seen. When the switch knob is in the up position, pins 1-3 are shorted and no dot can be seen.

TABLE 2-14: 8-BIT INDEXED HBI MODE SELECTION


SW5 Up A0_AD15 AD15_CONFIG3


SW7 Up ALELO_A1 ALELO_CONFIG3


SW9 Up ALEHI_A2 ALEHI_CONFIG3

SW24 Down ALELO_CONFIG3 GPMC_A0_ALE

SW25 Down ALEHI_CONFIG3 GPMC_A1_ALEHI




Table 2-15 details the switch selection for 16-bit Indexed HBI Mode.

2.4.4.2 SPI+GPIO SELECTION

The knob position of SW11 to SW21 must be down to select the SPI+GPIO mode. SW19, SW20, and SW21 are used to route the SPI/SQI signals from the LAN9252 to the SoC. SW11 to SW18 are used to route the 16 GPIO signals from the LAN9252 to the GPIO circuit.

2.4.4.2.1 SPI/SQI/I2C Aardvark Header

J11 and J12 are used as Aardvark/SPI/SQI headers. The respective pin details are shown in Table 2-17.

TABLE 2-15: 16-BIT INDEXED HBI MODE SELECTION


SW5 Down A0_AD15 A0_CONFIG3


SW7 Up ALELO_A1 ALELO_CONFIG3


SW9 Up ALEHI_A2 ALEHI_CONFIG3

SW24 X (Don’t Care) X X

SW25 Down ALEHI_CONFIG3 GPMC_A1_ALEHI


Note: If any other SoC is used, the user must check what modes are supported and configure the HBI mode selection switches accordingly.

TABLE 2-16: SW19-SW21 SIGNAL DEFINITIONS

Switch Signals

SW19 (pin 2-3 & pin 5-6) SIO3 & SIO2

SW20 (pin 2-3 & pin 5-6) SIO0 & SIO1

SW21 (pin 2-3 & pin 5-6) SCK & SCS#

TABLE 2-17: J11 & J12 HEADER PINOUT

Signal Pin Number

SCL J11.1

SDA J11.3

SCK J11.7

SCS# J11.9

SI(SIO0) J11.8

SO(SIO1) J11.5

SIO2 J12.3

SIO3 J12.4



2.4.4.3 GPIO INPUT/OUTPUT SELECTION

To enable the SPI+GPIO configuration, the SW11 to SW18 switches must be in the down position. Additionally, the following switches must be configured to select the input or output modes, as shown in Table 2-18.

2.4.4.3.1 GPIO INPUT Mode

In INPUT Mode, Digital I/O values can be selected through dip switches SW34 and SW40:

• Logic 1 : (Default) SW34 & SW40 Off position. GPI0 to GPI15 tied to pull-up (R90 to R105)

• Logic 0 : The respective knob of 2-way, 8-position dip switch (SW34 & SW40) need to be moved to ON side. Signals can be selected individually.

2.4.4.3.2 GPIO OUTPUT Mode

In OUTPUT Mode, updated GPO values will be seen on the green LEDs (D7 to D22):

• Logic 1 : LED illuminated (green)

• Logic 0 : LED not illuminated.

2.4.5 SoC

The EVB-LAN9252-HBI+ supports both an on-board SoC and add-on SoC. By default, the on-board SoC is enabled. However, an external add-on SoC can be connected via the add-on SoC headers P1 and P2. The SoC selection is configured via the SW26 switch, as detailed in the following subsections.

2.4.5.1 SOC SELECTION

The SW26 switch selects the enabled SoC. The SW26 switch knob position must be down (Text = “PIC”) to select the on-board PIC. If the switch knob position is up (Text = “PIM”), then the add-on board/SoC is selected and the on-board PIC is always in the reset state. Whenever an add-on board/SoC is used, the switch knob must be in the up position.

TABLE 2-18: GPIO MODE SWITCH CONFIGURATIONS

Switches Switch Knob Position Mode

SW28 to SW33SW35 to SW39SW41 to SW45

Short Pins 1 and 2 INPUT Mode

SW28 to SW33SW35 to SW39SW41 to SW45

Short Pins 1 and 3 OUTPUT Mode

Note: The LED (D7 to D22) anode is connected to ASIC.

TABLE 2-19: SOC SELECTION

Switch Position Settings

SW26 Down On-board PIC enabled

SW26 Up Add-on board/SoC enabled



2.4.5.2 ON-BOARD PIC

By default, the on-board Microchip PIC32MX795F512L (U7) is used as the default SoC. The LAN9252 can be connected to the PIC using either an HBI or SPI interface. The selection switches must be configured accordingly to enable the desired interface. Refer to Section 2.4.4 “DIGIO/HBI/SPI+GPIO Selection” and Section 2.4.4.1 “HBI Mode Selection” for additional details.

2.4.5.2.1 Reset

SW27 is used to reset the on-board PIC. The LAN9252 can also reset the SoC if the reset pin is configured to output mode. For stability, a delay of approximately 180ms is added from the 3.3V o/p to reset release.

2.4.5.2.2 ICSP Header

The on-board PIC programing is performed using the ICSP header J13. Table 2-20 details the ICSP header pinout

2.4.5.2.3 SoC EEPROM

The EVB-LAN9252-HBI+ provides an optional SoC EEPROM. Some SoCs may require an EEPROM. However, the PIC on-board SoC and PIC based add-on SoC boards do not require this EEPROM.

2.4.5.3 ADD-ON SOC

An add-on board can be attached to the EVB-LAN9252-HBI+ to use an add-on SoC. The add-on board must be mounted to the P1 and P2 connectors (2x23, 100mil normal gold plated berg stick). The SW26 switch must be in the up position when using an add-on SoC. Additionally, the J10 2-pin jumper must be shorted to route power to the add-on board from the EVB-LAN9252-HBI+.

2.4.5.4 ESC ID SELECT

The signals shown in Table 2-21 are provided as EtherCAT® ID selection for complex ESCs. Jumper J20 and respective pull-up resistors are used to configure the ID select signals high or low. By default, there are no resistors populated and all signals are nei-ther high or low. When required, populating the respective jumper or resistor will change the ID select signal to low.

TABLE 2-20: J13 ICSP HEADER PINOUT

J13 Pin Settings

1 MLCR

2 3V3

3 GND

4 PGD2

5 PGC2

6 NC

TABLE 2-21: ID SELECT SIGNALS

ID Selection Signal

Signal NamePIC Pin Number

10k to Pull High

Pins to Short for Pull Low

ID0 ID0_SELECT_RB0 25 R123 32:31

ID1 ID_SELECT_RB1 24 R124 30:29






2.5 DIGIO & SPI+16GPIO SIGNALS ON P1 AND P2 HEADERS

2.5.1 DIGIO on P1 and P2 Headers (up to 16 bits supported)

The LAN9252 supports a DIGIO mode, where these signals can be probed on the P1 and P2 headers. To enable DIGIO mode, from the default state of the board, the SW26 switch must be changed to the PIM position (upward). The respective DIGIO signal mappings on the P1 and P2 headers are detailed in Table 2-22.

Note 1: In the default state, headers P1 and P2 are not assembled. These headers can each be populated with a Molex 87758-4616.

2: The user must ensure that the EEPROM is configured in DIGIO mode.






ID10 ID_SELECT_RB12 41 R133 12:11


ID12 ID_SELECT_RC1 6 R135 8:7




TABLE 2-21: ID SELECT SIGNALS (CONTINUED)

ID Selection Signal

Signal NamePIC Pin Number

10k to Pull High

Pins to Short for Pull Low

TABLE 2-22: DIGIO MODE P1 & P2 HEADER SIGNALS

HBI Indexed HBI Multiplexed DIGIO P1/P2 Pin

RD/RD_WR RD/RD_WR DIGIO15 P1.8

WR/ENB WR/ENB DIGIO14 P1.10

CS CS DIGIO13 P1.26

A4 - DIGIO12 P1.41

A3 - DIGIO11 P1.44

A2 ALEHI DIGIO10 P2.21

A1 ALELO OE_EXT P1.7

A0/D15 AD15 DIGIO9 P1.15

D14 AD14 DIGIO8 P1.16





D9 AD9 LATCH_IN P1.13

D8 AD8 DIGIO2 P1.19

D7 AD7 DIGIO1 P1.4

D6 AD6 DIGIO0 P1.3

D5 AD5 OUTVALID P1.22

D4 AD4 DIGIO3 P1.23



2.5.2 SPI+GPIO on P1 and P2 Headers (up to 16 bits supported)

The LAN9252 supports an SPI+16GPIO mode, where these signals can be probed on the P1 and P2 headers. To enable SPI+16GPIO mode, from the default state of the board, the SW26 switch must be changed to the PIM position (upward) and SW19, SW20, and SW21 must be changed to the downward side. The respective SPI+16GPIO signal mappings on the P1 and P2 headers are detailed in Table 2-23.

Note 1: In the default state, headers P1 and P2 are not assembled. These headers can each be populated with a Molex 87758-4616.

2: The user must ensure that the EEPROM is configured in DIGIO mode.

D3 AD3 WD_TRIG P1.6

D2 AD2 SOF P1.5

D1 AD1 EOF P1.24

D0 AD0 WD_STATE P1.25

TABLE 2-23: SPI+16GPIO MODE P1 & P2 HEADER SIGNALS

HBI Indexed HBI Multiplexed SPI+16GPIO P1/P2 Pin

RD/RD_WR RD/RD_WR GPI15/GPO15 P1.8

WR/ENB WR/ENB GPI14/GPO14 P1.10

CS CS GPI13/GPO13 P1.26

A4 - GPI12/GPO12 P1.41

A3 - GPI11/GPO11 P1.44

A2 ALEHI GPI10/GPO10 P2.21

A0/D15 AD15 GPI9/GPO9 P1.15

D14 AD14 GPI8/GPO8 P1.16





D9 AD9 SCK P1.13




D5 AD5 SCS# P1.22


D3 AD3 SIO3 P1.6

D2 AD2 SIO2 P1.5

D1 AD1 SO/SIO1 P1.24

D0 AD0 SI/SIO0 P1.25

TABLE 2-22: DIGIO MODE P1 & P2 HEADER SIGNALS (CONTINUED)

HBI Indexed HBI Multiplexed DIGIO P1/P2 Pin



2.6 ADDITIONAL FEATURES

The EVB-LAN9252-HBI+ includes additional features that were not available in the pre-vious revision of the board. This section details these additional features. To learn more about how to use them refer to the Quick Start guide found at microchip.com.

2.6.1 Potentiometer

The EVB-LAN9252-HBI+ includes a potentiometer, as shown in Figure 2-8. The poten-tiometer is used as an input to the PIC32 and is labeled as “pot1” on the board.

FIGURE 2-8: POTENTIOMETER POT1

2.6.2 Temperature Sensor

The EVB-LAN9252-HBI+ includes a Microchip temperature sensor (TC104AVNBTR), as shown in Figure 2-9. The temperature sensor is used as an input into the PIC32 and is labeled “U9” on the board.

FIGURE 2-9: TEMPERATURE SENSOR U9

2.6.3 UART RS-232

A RS-232 connector is present on the board as J24. This allows serial communication with the PIC32. With this connector UART communication is possible as both an input and an output.

2.6.4 DAC

Through an on-board Microchip digital to analog converter (MCP4726) it is possible to use the EtherCAT application to input a value to the DAC and get a calculated voltage output on the DAC. It it labeled as U10 on the board and can be seen next to the poten-tiometer.

2.7 LIMITATIONS

The EVB-LAN9252-HBI+ has the following limitations:

1. While the LAN9252 supports both SFP and SFF Fiber Modes, the EVB-LAN9252-HBI+ supports only the SFP Fiber Mode.

2. SQI is not supported when using the on-board PIC32MX.



2.8 MECHANICALS

FIGURE 2-10: EVB-LAN9252-HBI+ MECHANICAL DIMENSIONS



USER’S GUIDE

Chapter 3. Software Development Kit

This chapter explains the architecture of the LAN9252 EtherCAT® slave stack firmware sample and introduces the SDK framework for use with PIC32MX microcontroller for EVB-LAN9252-HBI+ development.

This chapter includes the following sub-sections:

• Prerequisites

• ESC SDK Sample Overview

• Using the Sample Project

• Programming the LAN9252 EEPROM

3.1 PREREQUISITES

3.1.1 Hardware Requirements

• EVB-LAN9252-HBI+-SPI-SQI-GPIO

• Windows Host Machine with minimum 2GB RAM

• Programmers – Aardvark I2C/SPI Host Adapter, Pickit3 Programmer

3.1.2 Software Requirements

• MPLAB IDE v2.20 or higher

• MPLAB XC Compiler v1.33 or higher

• Total Phase Flash Centre V1.31 or higher

3.2 ESC SDK SAMPLE OVERVIEW

The LAN9252 ESC supports interfacing to an external SoC using an SPI or HBI inter-face. This PIC32 based SDK sample contains separate projects for HBI and SPI inter-faces.

This software SDK is developed as a bare-metal firmware implementation (not specific to any OS) designed to access the LAN9252 ESC features via an HBI or SPI interface. The EtherCAT® slave stack portion of the source is obtained from EtherCAT Technol-ogy Group.

This software project has been tested with the EVB-LAN9252-HBI+ using the PIC32MX SoC.

Figure 3-1 provides an architectural block diagram of the SDK’s various source mod-ules. The subsequent sections detail these blocks.



FIGURE 3-1: PIC32 SOC FIRMWARE FRAMEWORK

3.2.1 User Module

3.2.1.1 SOC INITIALIZATION

This code block is part of the user application that boots the PIC microcontroller with the desired RAM configuration, clock speed, clock source and other related features of the controller, per the user’s configuration.

3.2.1.2 PERIPHERAL INITIALIZATION

This code block configures and initiates the core peripherals (UART, I2C, SPI) and external peripherals (EEPROM, LAN9252).

3.2.1.3 MAIN APPLICATION

This code block contains the code that runs the LAN9252 EtherCAT® slave module demo application.

3.2.2 EtherCAT® Slave Stack

This code block contains the EtherCAT slave stack.

3.2.3 Hardware Abstraction Layer (HAL)

This code block contains the low level layer that provides software hooks/APIs to the application module and slave stack, allowing communication between these modules and the hardware resources. For additional information, refer to the ReadMe.txt file located in the project source folder.


Software Development Kit

3.3 USING THE SAMPLE PROJECT

3.3.1 MPLAB IDE Project Settings & Firmware Download

1. Once the EtherCAT SSC is integrated with LAN9252 SDK as detailed in “Integrat‐ing LAN9252 ‐ PIC32MX SDK with EtherCAT SSC from ETG” application note, Copy it to the desired directory. (For the purposes of this document, the Desk‐top will be the target folder).

2. Open the MPLAB IDE and import the SSC project into the IDE.

FIGURE 3-2: MPLAB IDE OPEN PROJECT

FIGURE 3-3: MPLAB IDE PROJECT DIRECTORY

The target directory contains two project folders:

• PIC32-HBI Project Folder

• PIC32 Project Folder



3.3.1.1 PIC32-HBI PROJECT FOLDER

The PIC32 project folder contains the sample code that enables the LAN9252's HBI interface to communicate with the SoC. HBI demo code is provided for each of the LAN9252’s six HBI configurations. These configurations can be selected respectively from the configuration drop down box as shown in Figure 3-4.

FIGURE 3-4: MPLAB IDE HBI CONFIGURATION SELECTION

3.3.1.2 PIC32 PROJECT FOLDER

The PIC32-SPI project folder contains the demo code that enables the LAN9252's SPI interface to communicate with the SoC.

• Refer to the LAN9252 data sheet for more details on these HBI interface and its modes.

• Refer to Section 2.4.4 “DIGIO/HBI/SPI+GPIO Selection” for SPI jumper configura-tions.

TABLE 3-1: HBI CONFIGURATIONS

HBI Configuration (Project) Description

HBI_INDEXED_8BIT_XC32_PIC32MX79F512 8-bit Indexed mode

HBI_INDEXED_16BIT_XC32_PIC32MX79F512 16-bit Indexed mode

HBI_MDP_8BIT_XC32_PIC32MX79F512 8-bit Multiplexed dual phase mode

HBI_MDP_16BIT_XC32_PIC32MX79F512 16-bit Multiplexed dual phase mode

HBI_MSP_8BIT_XC32_PIC32MX79F512 8-bit Multiplexed single phase mode

HBI_MSP_16BIT_XC32_PIC32MX79F512 16-bit Multiplexed single phase mode



3.3.2 Compiling and Programming SoC Firmware

1. Compile the source code (with corresponding configuration selected if HBI proj-ect is loaded).

FIGURE 3-5: MPLAB IDE COMPILE PROJECT SELECTION

2. If the compilation is successful, the output window will display “BUILD SUC-CESSFUL”, as shown in Figure 3-6.

FIGURE 3-6: MPLAB IDE BUILD SUCCESSFUL

3. Before initiating the firmware download, ensure the debugger/programmer is connected to the EVB’s JTAG pins. (This demo project is debugged with the PICkit-3 In-Circuit debugger/programmer).

4. To program the PIC32 SoC, click the “Make and Program Device Main Project” button.

FIGURE 3-7: MPLAB IDE PROGRAM DEVICE



5. To debug the PIC32 SoC, click “Debug Main Project” button.

FIGURE 3-8: MPLAB IDE DEBUG DEVICE

3.4 PROGRAMMING THE LAN9252 EEPROM

The LAN9252 configures itself to the desired mode (SPI, 6 HBI modes) by reading the strap settings located in EEPROM. The LAN9252 EEPROM is programmed and vali-dated via the TwinCAT master tool. The EEPROM can also be programmed using an external IIC Master, like AARDVARK.

3.4.1 Programming LAN9252 EEPROM using the TwinCAT Master Tool

The programming procedure using the TwinCAT master tool is as follows:

Note 1: This example utilizes the TwinCAT tool. Procedures may differ when using other EtherCAT® master tools.

2: Ensure the system network properties are configured properly for the Eth-erCAT® frames, Ethernet cable linking your system, and EtherCAT® slave board.

1. Load the corresponding ESI file in the directory path "C:\TwinCAT\3.1\Con-fig\Io\EtherCAT". For this demo, the ESI file for the 16-Bit Multiplexed Sin-gle-Phase Mode is used.

2. If TwinCAT installed successfully, a TwinCAT icon will be shown in the bot-tom-right corner of the desktop. After clicking the icon, a pop-up list will display. Select “TwinCAT XAE (VS 2013)”, as shown in Figure 3-9.

FIGURE 3-9: TWINCAT SYSTEM MANAGER



3. Click on “New TwinCAT Project” as shown in Figure 3-10. Choose a name and click “ok”.

FIGURE 3-10: TWINCAT DELETE DEVICE

4. Scan for EtherCAT® slave devices by expanding “I/O” and right clicking “Devices” and then selecting “Scan”, as shown in Figure 3-11.

FIGURE 3-11: TWINCAT SCAN DEVICES

5. After scanning is complete, a window showing devices found will appear similar to Figure 3-12.



FIGURE 3-12: TWINCAT DEVICE LIST

6. Click “Yes” for Scan for Boxes and “Yes” for Activate Free Run.

7. After a successful scan, click the “Device 2 (EtherCAT)” drop down bar on the left panel of the TwinCAT tool (as highlighted in Figure 3-11). Then click the “Online” tab on the right-side panel of the TwinCAT tool, as shown in Figure 3-13. Right click the LAN9252 listing and select “EEPROM Update” from the contextual menu.

FIGURE 3-13: TWINCAT EEPROM UPDATE

8. Upon selecting “EEPROM Update”, the Write EEPROM window will open. Click the “OK” button to initiate EEPROM programming (Figure 3-14).

FIGURE 3-14: TWINCAT WRITE EEPROM



USER’S GUIDE

Appendix A. Evaluation Board Photo

A.1 INTRODUCTION

This appendix shows the EVB-LAN9252-HBI+ Evaluation Board.

FIGURE A-1: EVB-LAN9252-HBI+ EVALUATION BOARD



USER’S GUIDE

Appendix B. Evaluation Board Schematics

B.1 INTRODUCTION

This appendix shows the EVB-LAN9252-HBI+ Evaluation Board Schematics.


Evalu

ation

Bo

ard S

chem

atics

2015-2016 Microchip T

echnology Inc.

DS

50002333C

-page 39

FIG

2

D

C

B

"3V

3 P

rese

nt"

) & SOC :Only Ethercat sku

"Reset"

3V3

V3TP3

BLACK

D1GRN

1A

2C

D2

Br_Red-RA

1A

2C

TP4BLACK

C1

4.7uFDNP

R21K

URE B-1: EVB-LAN9252-HBI+ SCHEMATIC POWER SUPPLY & RESET

5 4 3

Reset Generator

POWER SUPPLY

(Rb)(Ra)OKR-T/3-W12-C

3 V REGULATOR, 3A( 3V3 fixed when Rb=503e)

Note: 1.POR -> Reset to ASIC & SOC (Default)2.RESET O/P from ASIC -> Reset to EX-PHY (PORT23.RESET from SOC (GPIO/RST-O/P) -> Reset to ASIC4.RESET from Push Botton -> Reset to ASIC & SOC

RESET Options

5V_SWEN12_1

5V_EXT35V

3V3

3V3

3V3

3V3

RST#

TP1RED

TP2ORANGE

C3

0.1uF

C6

0.1uF

R8 1K

U1

3_Amp GND3

VIN2

ENABLE1

TRIM5VOUT4

R7100E

1/10W1%

1 2

R54.75K1%

Q1

NDS355AN_NMOS

1G 3

S

2 D

U2

TPS3125

SOT23_5Threshold = 2.64VDelay = 180ms

RESET#1

GN

D2

RESET3

MR#4

VD

D5

SW1

P/N:1101M2S3CQE2Switch, SPDT, Slide

23

1

C4

10uF

C210uF25V

R610K1/10W1%

12

C5

0.1uF

U3

74LVC1G14

2 4

531

SW2

sw_pb_2P

R4470R1%

R33.30K1%

R10R

R92.2K

R4A33R1%

FB1

2A/0.05DCR

J1

1

2

3

EV

B-L

AN

9252-H

BI+

Eth

erCA

T®

Evalu

ation

Bo

ard

Use

r’s Gu

ide

DS

50002333C

-page 40

2015-2016 M

icrochip Technolo

gy Inc.

1

1

D

C

B

A

Power Supply Filtering

Low

ES

R

3V3VDDCR

Size:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043

DB4 12Wednesday, February 17, 2016

JUTLANDLAN9252

EVB-LAN9252-HBISize:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDLAN9252


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDLAN9252

EVB-LAN9252-HBI

C14

0.1u

F

C17

0.1u

F

C11

0.1u

F

C21

0.1u

F

C22

0.1u

F

C15

0.1u

F

C13

0.1u

F

C20

470p

F

C12

1.0u

FD

NP

C16

0.1u

F

C10

0.1u

F

C19

1uF

C18

0.1u

F

FIGURE B-2: EVB-LAN9252-HBI+ SCHEMATIC LAN9252 5

5

4

4

3

3

2

2

D

C

B

A

Note: OSCVSS need to connect to Chip gnd.

REG_EN

RBIAS

VD

D12

TX

1V

DD

12T

X2

VDD12TX2VDD12TX1

OSCOOSCI

3V3

VD

D33

TX

RX

1V

DD

33T

XR

X2

VDDCR

VDD33TXRX1

VDD33TXRX2

3V3

3V3

3V3 3V3

FXSDA/FXLOSA

IRQ

ATEST/FXLOSEN

RXPARXNA

TXNATXPA

TXNBTXPBRXNBRXPB

FXSDB/FXLOSB

GPIO0GPIO1GPIO2

I2C2_SCLI2C2_SDA

RST#

FB3 2A/0.05DCR

R10 12.1K1%

C27 18pF

POWER

INT PORT0

INT PORT1

OSC

I2C

OTHER

SIGNALS

GPIO

(Only for

Lan9252)

U4A

LAN9252

FXSDENA/FXSDA/FXLOSA9

FXSDENB/FXSDB/FXLOSB10

VD

D33

TX

RX

151

TXNA52

TXPA53

RXNA54

RXPA55

VD

D12

TX

156

RBIAS57

VD

D33

BIA

S58

VD

D12

TX

259

RXPB60RXNB61TXPB62TXNB63

VD

D33

TX

RX

264

OSCI1

OSCO2

OSCVDD123

OSCVSS4

REG_EN7

ATEST/FXLOSEN8

RST#11

IRQ44

TESTMODE41

I2CSCL/EESCL/TCK43

I2CSDA/EESDA/TMS42

LINKACTLED0/TDO/LEDPOL0/CHIP_MODE048

LINKACTLED1/TDI/LEDPOL1/CHIP_MODE146

RUNLED/LEDPOL2/E2PSIZE45

VD

D33

5

VD

DIO

114

VD

DIO

220

VD

DIO

332

VD

DIO

437

VD

DIO

547

VD

DC

R1

6

VD

DC

R2

24

VD

DC

R3

38

GN

D65

C25

0.1u

F

FB2 2A/0.05DCR

FB52A/0.05DCR

C24

0.1uF

C231.0uFDNP

C8

0.1uF

C26 18pF

C9

1.0u

F

DN

P

C71.0uFDNP

Y125.000MHz25ppm

12

FB4 2A/0.05DCR

BLM18EG221SN1D

Evalu

ation

Bo

ard S

chem

atics


echnology Inc.

DS

50002333C

-page 41

FIG

1

1

D

C

B

A

Size:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDCopper Mode Interface


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043




Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043



EVB-LAN9252-HBI

URE B-3: EVB-LAN9252-HBI+ SCHEMATIC COPPER MODE INTERFACE

5

5

4

4

3

3

2

2

D

C

B

A

Note:Capacitors C10 through C13 are optional for EMI purposesand are not populated on the LAN8740/41 evaluation board.These capacitors are required for operation in an EMIconstrained environment.

LED1 (Green) = LINK/ACT

LED2 (Yellow) = SPEED

Note:Capacitors C10 through C13 are optional for EMI purposesand are not populated on the LAN8740/41 evaluation board.These capacitors are required for operation in an EMIconstrained environment.

LED1 (Green) = LINK/ACT

LED2 (Yellow) = SPEED

COP-RXPA

COP-TXNA

COP-RXNA

COP-TXPA

COP-RXPB

COP-TXNB

COP-RXNB

COP-TXPB

VDD33TXRX2

VDD33TXRX1

FX_SFP-RXPA

FX_SFP-RXNA

TXPA

TXNA FX_SFP-TXNA

FX_SFP-TXPA

RXPA

RXNA

FX_SFP-RXPB

FX_SFP-RXNB

TXPB

TXNB FX_SFP-TXNB

FX_SFP-TXPB

RXPB

RXNB

C3410pF50V5%DNP

XMIT

RCV

75

75 75

1000 pF 2 kV

RJ45

1

4 & 5

2

3

7 & 8

6

75

GRN

YEL

T1Pulse J0011D01BNL

RD+3

RXCT5

RD-6

TD+1

TXCT4

TD-2

CHS GND8

GN

D13

GN

D1

14

MT

G15

MT

G1

16

NC7

C10

A9

C1

11

A1

12

C2810pF50V5%DNP

C3610pF50V5%DNP

R34 0RDNP

R150R

R1349.9R1/10W1%

R38 0R

RES1210

R37 0R

R2849.9R1/10W1%

R36 0RDNP

R21 0R

R17 0RR16 0RDNP

C370.022uF

50V10%

R33 0RR32 0RDNP

R18 0RDNP

C3110pF50V5%DNP

R24 0R

RES1210

R31 0RXMIT

RCV

75

75 75

1000 pF 2 kV

RJ45

1

4 & 5

2

3

7 & 8

6

75

GRN

YEL

T2Pulse J0011D01BNL

RD+3

RXCT5

RD-6

TD+1

TXCT4

TD-2

CHS GND8

GN

D13

GN

D1

14

MT

G15

MT

G1

16

NC7

C10

A9

C1

11

A1

12

C3010pF50V5%DNP

R1449.9R1/10W1%

C3510pF50V5%DNP

R2549.9R1/10W1%

R23 0R

C2910pF50V5%DNP

R20 0RDNP

R22 0RDNP

R1249.9R1/10W1%

R35 0R

R2649.9R1/10W1%

C3310pF50V5%DNP

R19 0R

C320.022uF

50V10%

R290R

R1149.9R1/10W1%

R2749.9R1/10W1%

R30 0RDNP

EV

B-L

AN

9252-H

BI+

Eth

erCA

T®

Evalu

ation

Bo

ard

Use

r’s Gu

ide

DS

50002333C

-page 42

2015-2016 M

icrochip Technolo

gy Inc.

1

1

D

C

B

A

Fiber Port 1 :SFP Interface

SFP_VCCT2

SFP_VCCR2

SF

P_T

D2-

SF

P_T

D2+

SF

P_R

D2-

SF

P_R

D2+

3V3

Size:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDSFP Interface


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043




Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043



EVB-LAN9252-HBI

C530.1uF

C510.1uF

L1 1uH

TX

Fau

lt2

TX

Dis

able

3

MO

D-D

EF

(2)

4

MO

D-D

EF

(1)

5

MO

D-D

EF

(0)

6

Rat

e S

elec

t7

LOS

8

Vee

R9

Vee

R1

10V

eeR

311

Vee

R2

14

RD

-12

RD

+13

Vcc

R15

Vcc

T16

Vee

T2

17T

D+

18T

D-

19

21212222232324242525262627272828292930303131

+C5210uF16V

+C5010uF16VDNP

C570.1uF

+C5610uF16V

L3 1uH

FIGURE B-4: EVB-LAN9252-HBI+ SCHEMATIC SFP INTERFACE 5

5

4

4

3

3

2

2

D

C

B

A

Fiber Port 0 :SFP Interface

Note:Placecapacitors,and resistorsclose to FOT

Note:Placeresistorsclose toASIC

Note:Placecapacitors,and resistorsclose to FOT

Note:Placeresistorsclose toASIC

SFP_VCCT

SFP_VCCR

SF

P_T

D-

SF

P_T

D+

SF

P_R

D-

SF

P_R

D+

SFP_VCCTSFP_VCCT2

3V3 3V3

3V3

FXSDA/FXLOSA FXSDB/FXLOSB

FX_SFP-TXPA

FX_SFP-RXNA

FX_SFP-RXPA

FX_SFP-TXNA

FX_SFP-RXNB

FX_SFP-RXPB

FX_SFP-TXPB

FX_SFP-TXNB

C49

0.1uF

+C4810uF16V

R4082R

L2 1uH

C39 0.1uF

C42

0.1uF C43 0.1uF

R51130R

J3

FTLF1217P2

Vee

T1

Vee

T1

20

R544.7K

R4482R

R564.7K

R594.7K

R49130R

R4149.9R

R48100E

R574.7K

J2

FTLF1217P2

Vee

T1

TX

Fau

lt2

TX

Dis

able

3

MO

D-D

EF

(2)

4

MO

D-D

EF

(1)

5

MO

D-D

EF

(0)

6

Rat

e S

elec

t7

LOS

8

Vee

R9

Vee

R1

10V

eeR

311

Vee

R2

14

RD

-12

RD

+13

Vcc

R15

Vcc

T16

Vee

T2

17T

D+

18T

D-

19V

eeT

120

21212222232324242525262627272828292930303131

R4549.9R

C470.1uF

R3982R

R47100E

C41 0.1uF

R604.7K

C550.1uF

+C5410uF16V

R554.7K

R4382R

R534.7K

C45 0.1uF

R50130R

+C4610uF16VDNP

R4249.9R

R584.7K

C44

0.1uF

R52130R

L4 1uH

C38 0.1uF

R4649.9R

C40 0.1uF

Evalu

ation

Bo

ard S

chem

atics


echnology Inc.

DS

50002333C

-page 43

FIG

1

1

D

C

B

A

izes can be mounted

OM Lower size(2K X 8)

OM Higher size(2K X 8)

FX_Mode_Strap_1 & 2

�� 12��*��3��)��

�"�� 4��12��*��3��)��

3V3

3V3

3V3

I2C2_SDA

I2C2_SCL

FXSDA/FXLOSA

FXSDB/FXLOSB

:

Number:Rev

: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDSTRAP,GPIO,I2C & FXLOS

EVB-LAN9252-HBI:

Number:Rev

: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043



EVB-LAN9252-HBI:

Number:Rev

: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043



EVB-LAN9252-HBI

R78 10KDNP

R76 10K

R67

2K

R75 10KDNP

R80 10K

R68

2K

URE B-5: EVB-LAN9252-HBI+ SCHEMATIC STRAP, GPIO, I2C & FXLOS

5

5

4

4

3

3

2

2

D

C

B

A

GPIO [0:2] & LED_POL_Strap

LINK/ACT

RUNLED

LINK/ACT

GPIO0 =LED0,LEDPOL0,MNGT0

GPIO1 = LED1,LEDPOL1,MNGT1

GPIO2 = LED2,LEDPOL2,E2PSIZE

Note: --To use GPIOs as LED* Short 2-3 of both jumpers (ex. for GPIO0 short 2-3 of J48 & J51)

1 The LED is set as active low,

MNGT0The LED is set as active high.

MNGT1

0

Signal Name Connector

J48,J51 (1&2)

LED Polarity StrapLogic

E2ESIZE

J48,J51 (2&3)

J50,J53 (1&2)

J50,J53 (2&3)

1

0

J49,J52 (1&2)

J49,J52 (2&3)

The LED is set as active low,

The LED is set as active high.

The LED is set as active low, EEPROM Size=32K bits (4K x 8) through 512K bits (64K x 8) or 4Mbits (512K x 8) (LAN9252 only)

The LED is set as active high.EEPROM Size=1K bits (128 x 8) through 16K bits (2K x 8)

1

0

Management/LED Polarity Strap

I2C EEPROM

TH IC. Different s

I2C EEPR Below 16K

I2C EEPRAbove 16K

�� !"��" �� #��$�� %� �� "#��&��'��#��'�$(

��)(*+��)+,�-��)(.�/��,0�� #�� !"��" �� $�� %� �� "#��&��'�$

��-��*�/��,0�� #��$

FX_Los_Strap_1 & 2

LED1_CATHODE

GPIO1

GPIO1

LED1_ANODELED2_ANODE

LED0_CATHODELED2_CATHODE

GPIO0

GPIO0 GPIO2

GPIO2

LED0_ANODE

LED0_ANODE

LED0_CATHODE

LED1_ANODE

LED1_CATHODE

LED2_ANODE

LED2_CATHODE

I2C2_2I2C2_3

I2C2_7

I2C2_1

3V33V3 3V3

3V33V3

3V3

GPIO0

GPIO1

GPIO2

ATEST/FXLOSEN

Size

Part

Date

Size

Part

Date

Size

Part

Date

R721K

D4GRN

1A

2C

J7

12

3

R731K

R7110K

12

R63

4.7K

R7710KDNP

R64

4.7K

J6

12

3

R66

4.7K

C58

0.1uF

J9

12

3

D3GRN

1A

2C

SW3

SW DIP-4/SM

1234

8765

U5

24FC04

GN

D4

VC

C8

SDA5

SCL6

A01

A12

A23

WP7

J4

12

3

R7010K

12

J5

12

3

R741K

R6910K

12

R65

4.7K

D5GRN

1A

2C

R7910K

J8

12

3

EV

B-L

AN

9252-H

BI+

Eth

erCA

T®

Evalu

ation

Bo

ard

Use

r’s Gu

ide

DS

50002333C

-page 44

2015-2016 M

icrochip Technolo

gy Inc.

1

1

D

C

B

A

ort 1 -2 = To Reset ASIC from SoC-GPIOort 2-3 = To Reset SoC from ASIC

HBI or SPI+GPIO Config selectionShort 1-2 & 4-5 for HBI Config (2-3 & 5-6 open)

Short 2-3 & 5-6 for SPI+GPIO Config (1-2 & 4-5 open)

SW22,SW23 & SW24 = HBI or SPI selection

*(2-3)

*(1-2)

*(2-3)

AD6AD7AD8AD9_SCK

AD10AD11AD12AD13AD14A0_AD15

AD5_SCS#AD4

AD3_SIO3AD2_SIO2AD1_SIO1AD0_SIO0

A3A4

ALEHI_A2ALELO_A1

AD5_SCS#

RD_RDWR_CONFIG3GPMC_DIR

GPMC_OEN_REN

WR_ENB_CONFIG3GPMC_WEN

GPMC_BE0N_CLE

AD2_SIO2AD3_SIO3

AD9_SCK

AD0_SIO0 AD1_SIO1

SCS#_CONFIG5

AD5_CONFIG3

RST#T_GPIO

RESETN

AD2_CONFIG3

SIO2_CONFIG5_CONFIG5

CONFIG3

9_CONFIG3

K_CONFIG5

D0_CONFIG3

IO0_CONFIG5 SIO1_CONFIG5

AD1_CONFIG3

Size:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDLAN9252(Part2)


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043




Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043



EVB-LAN9252-HBI

SW8

JS102011CQN

12

3

SW6

JS102011CQN

12

3

GIO12/GPI12/GPO12/MII_RXD027

GIO11/GPI11/GPO11/MII_RXDV26

TLED2/MII_LINKPOL/LEDPOL629

A1/ALELO/OE_EXT/MII_CLK2525

/DIGIO9/GPI9/GPO9/MII_RXER33

I8/GPO8/MII_TXD3/TX_SHIFT115

I7/GPO7/MII_TXD2/TX_SHIFT016

2/DIGIO6/GPI6/GPO6/MII_TXD121

1/DIGIO5/GPI5/GPO5/MII_TXD022

0/DIGIO4/GPI4/GPO4/MII_TXEN23

D9/AD9/LATCH_IN/SCK19

8/DIGIO2/GPI2/GPO2/MII_MDIO40

7/DIGIO1/GPI1/GPO1/MII_MDC39

DIGIO0/GPI0/GPO0/MII_RXCLK36

D5/AD5/OUTVALID/SCS#50

D3/AD3/WD_TRIG/SIO335

D2/AD2/SOF/SIO212

D1/AD1/EOF/SO/SIO113

D0/AD0/WD_STATE/SI/SIO017

4/DIGIO3/GPI3/GPO3/MII_LINK49

SW10

JS102011CQN

12

3

SW21123

456

SW19123

456

D6

DIODE

1 2

SW20123

456

FIGURE B-6: EVB-LAN9252-HBI+ SCHEMATIC BOARD TO BOARD INTERFACE 5

5

4

4

3

3

2

2

D

C

B

A

Board to Board Connectors for SoC

Sh Sh

5V power to HOST SOC board from EVB Board

Host SOC EEPROM

I2C EEPROMOnly for Host SOC

*(1-2)

*(1-2)

*(1-2)

RD_RDWRWR_ENBCS

AD7_CONFIG3AD3_CONFIG3

GPMC_OEN_RENGPMC_WEN

AD12_CONFIG3AD10_CONFIG3AD14_CONFIG3


CS_CONFIG3

FIFOSEL_LATCH0A3_CONFIG3A1_CONFIG3


GPMC_BE0N_CLEAD13_CONFIG3AD9_CONFIG3AD15_CONFIG3AD11_CONFIG3AD8_CONFIG3


A4_CONFIG3A2_CONFIG3A0_CONFIG3

VDD3V3EXPVDD_5V

SYS_RESETNGPMC_DIR

SIO3_CONFIG5SCS#_CONFIG5SIO1_CONFIG5

VDD3V3EXP

SIO2_CONFIG5

RST_GPIO

ALEHI_CONFIG3

SIO0_CONFIG5SCK_CONFIG5

CS A4

A3

AD4 AD8

AD7 AD6

A0_AD15_CONFIG3

ALEHI_A2_CONFIG3

ALELO_A1

PME_LATCH1

VDD_5V

I2C1_SCL

I2C1_SDAI2C3_2I2C3_3

I2C3_7

I2C3_1

WR_ENBALEHI_A2_CONFIG3ALEHI_A2

AD10

AD13 AD14

A0_AD15_CONFIG3A0_AD15 RD_RDWR

AD12AD11

ALELO_CONFIG3

5V

3V33V3

CS_CONFIG3

GPIO13_CONFIG5 GPIO12_CONFIG5

A4_CONFIG3

A3_CONFIG3

GPIO11_CONFIG5

AD4_CONFIG3


AD8_CONFIG3

AD7_CONFIG3


AD6_CONFIG3

PME_LATCH1

FIFOSEL_LATCH0

A1_CONFIG3

ALELO_CONFIG3

ALEHI_CONFIG3

A2_CONFIG3

A0_CONFIG3

IRQ

RS

SYS_

AD15_CONFIG3


GPIO4_CONFIG5

AD10_CONFIG3

AD13_CONFIG3


AD14_CONFIG3


GPIO6_CONFIG5


GPIO5_CONFIG5

SIO3

AD3_

AD

SC

A

SI2C1_SDA I2C1_SCL

WR_ENB_CONFIG3

RD_RDWR_CONFIG3

R85

4.7K

DN

P

SW12123

456

R84

4.7K

DN

P

SW13123

456

SW7

JS102011CQN

12

3

R86

2KD

NP

U4B

LAN9252

SYNC/LATCH118

SYNC/LATCH034

A4/DIA3/DI

A2/ALEHI/DIGIO10/GPI10/GPO10/LINKAC

A0/D15/AD15D14/AD14/DIGIO8/GPD13/AD13/DIGIO7/GP

D12/AD1D11/AD1D10/AD1

D8/ADD7/AD

D6/AD6/

RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD331

WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD230

CS/DIGIO13/GPI13/GPO13/MII_RXD128

D4/AD

R83

2KD

NP

P2

HEADER 23x2

13579111315171921232527293133353739414345

2468

10121416182022242628303234363840424446

C590.1uFDNP

P1

HEADER 23x2

13579111315171921232527293133353739414345

2468

10121416182022242628303234363840424446

SW18123

456

J10

1 2

C60 0.1uFDNP

R81

4.7K

DN

P

SW15123

456

SW9

JS102011CQN

12

3

SW17123

456

R82

4.7K

DN

P

TP5ORANGE

SW5

JS102011CQN

12

3

SW11123

456

SW4

SW DIP-4/SMDNP

1234

8765

SW16123

456

SW14123

456

U624FC512

DNP

GN

D4

VC

C8

SDA5

SCL6

A01

A12

A23

WP7

Evalu

ation

Bo

ard S

chem

atics


echnology Inc.

DS

50002333C

-page 45

FIG

1

1

D

C

B

A

J73 - SPI AARDVAR HEADERJ73+J74 - SPI STROM HEADER

Aardvark / SPI Storm- Connector

*(2-3)

*(2-3)

M1 & PWM2 Signal for Motor Control

ExternalPowerOption

1-2* = External PWR2-3 = 5V (Default)

PMRD

PMWR

GPMC_A0_ALE

GPMC_A1_ALEHI

_CONFIG5SIO0_CONFIG5

_CONFIG5CONFIG5

PWM2

T_RB0T_RB1T_RB2

T_RB8

T_RB3T_RB4T_RB5

T_RB9T_RB10

T_RC4T_RC3T_RC2

T_RB11

T_RC1

T_RB12T_RB13

5V

3V3

ALEHI_CONFIG3

A1_CONFIG3

A0_CONFIG3

ALELO_CONFIG3

2C2_SCL2C2_SDA

SIO2_CONFIG5SIO3_CONFIG5

WR_ENB_CONFIG3

RD_RDWR_CONFIG3

MC_A1_ALEHI

GPMC_A0_ALE

Size:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDON-Board-PIC32MX


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043




Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043



EVB-LAN9252-HBI

R13

710

KD

NP

R12

610

KD

NP

SW24

JS102011CQN

12

3

R12

810

KD

NP

J18

HEADER 3X2

246

135

R13

110

KD

NP

R12

710

KD

NP

R13

210

KD

NP

TP9

R12

510

KD

NP

R12

910

KD

NP

TP8

R12

410

KD

NP

J1234

12

R13

610

KD

NP

SW25

JS102011CQN

12

3

R1220R

R13

010

KD

NP

R12

310

KD

NP

J20

HEADER 16X2

2468101214161820222426283032

13579

1113151719212325272931

J19

12

3

R13

810

KD

NP

R620RR61 0R

R13

410

KD

NP

R13

310

KD

NP

R13

510

KD

NP

J11

246810

13579

URE B-7: EVB-LAN9252-HBI+ SCHEMATIC PIC32MX

5

5

4

4

3

3

2

2

D

C

B

A

DNP

Decap for U3

DNP

DNP

RESET SW Position 1-2 & 4-5 = PIM ON SW Position 2-3 & 5-6 = PIC ON

Error LED

*(1-2)

*(1-2)

PIC32MX Unused GPIOs with GND probing option

PW

J20

- D

efau

lt O

PE

N; U

sed

as p

robi

ng h

eade

r.S

hort

whe

n E

ther

CA

T ID

nee

d to

be

used

.A

lso

resp

ectiv

e 10

K p

ullu

p re

sist

er

need

to b

e as

sem

bled

SMA for SYNC0 & SYNC1

Assemble R143,R144 & R152 if EtherCAT ID select is required.Temp.Sener, ADC & DAC functionswill not work when EtherCAT ID select is used

MCLR

VDDCORE

PM

RD

ID_SELECT_RB5

RG

13R

G12

GP

MC

_A0_

ALE

ID_SELECT_RC1ID_SELECT_RC2ID_SELECT_RC3ID_SELECT_RC4

RG6

RA0

ID_SELECT_RB4ID_SELECT_RB3

RA

1

PIC_MCLR

MCLR

PIC_MCLR

GP

MC

_A1_

ALE

HI

SCS#

SIO1SCK_

ID_S

ELE

CT

_RB

8ID

_SE

LEC

T_R

B9

ID_S

ELE

CT

_RB

10ID

_SE

LEC

T_R

B11

ID_S

ELE

CT

_RB

12ID

_SE

LEC

T_R

B13

RD11

RG2RG3

RA4RA5

RD9RD8

RA

9R

A10

ID_SELECT_RB1ID_SELECT_RB0

PGC2PGD2

RA

7R

A6

RG15

PWM2

PWM1

RD

14R

D15

RF3

FIFOSEL_LATCH0 PME_LATCH1

RG3RA4RD8RA9RA1RG6RG12RA7

RD15RG2 RD14

RA5RD9RF3RA10RA0RG15RG13RA6

RD11

PM

WR

ID_SELECID_SELECID_SELEC

ID_SELEC


ID_SELECID_SELEC


ID_SELEC

ID_SELEC

ID_SELECID_SELEC

ID_SELECT_RB2

3V3

3V3

3V3

3V3

SYS_RESETN

CS_CONFIG3AD7_CONFIG3AD6_CONFIG3

SIO

0_C

ON

FIG

5S

IO1_

CO

NF

IG5

SC

K_C

ON

FIG

5

SC

S#_

CO

NF

IG5

AD5_CONFIG3

A3_CONFIG3A4_CONFIG3

A2_CONFIG3

I2C1_SDAI2C1_SCL

IRQ

AD

4_C

ON

FIG

3A

D3_

CO

NF

IG3

AD

2_C

ON

FIG

3

RS

T_G

PIO

AD

1_C

ON

FIG

3A

D0_

CO

NF

IG3

AD

8_C

ON

FIG

3A

D9_

CO

NF

IG3

AD

10_C

ON

FIG

3A

D11

_CO

NF

IG3

AD

15_C

ON

FIG

3A

D14

_CO

NF

IG3

AD

13_C

ON

FIG

3A

D12

_CO

NF

IG3

II

FIFOSEL_LATCH0PME_LATCH1

RxDTxD

SoC_OSC2

SoC_OSC1

SoC_SOSCO

SoC_SOSCI

ADC1 INTEMP IN

PIM_MCLR

PGC2PGD2

LED_OUT

Switch _INRD2RD3

DAC_OUT_ADC2

I2C_SDA_DAC_CTLI2C_SCL_DAC_CTL

GP

J21DNP

SIG1

GND12

GND23

GND34

GND45

R87 0R

Y232Khz

C64 11pF

R152 0RDNP

J13

DBG ICSP Header

123456

C65 20pF

J15DHEADER 10x4

481216202428323640

C67

0.1u

F

C75

0.1u

F

J22DNP

SIG1

GND12

GND23

GND34

GND45

Y38 Mhz

J15AHEADER 10x4

15913172125293337

J15CHEADER 10x4

371115192327313539

C73

0.1u

F

R884.7K

R1390R

C71

0.1u

F

R140 1K

C62 10uF

C69

0.1u

F

R143 0RDNP

C61 0.1uF

SW27

sw_pb_2P

C63 11pF

C66 20pF

R144 0RDNP

D23GRN

1 A 2C

J15BHEADER 10x4

261014182226303438

U7 PIC32MX775F256L

AERXERR1

VDD2

PMD53

PMD64

PMD75

RC16

RC27

RC38

RC49

PMA510

PMA411

AERXDV12

MCLR13

AERXCLK/AEREFCLK14

VSS15

VDD116

TMS/RA017

AERXD018

AERXD119

AN5/C1IN+/VBUSON/CN7/RB520

RB421

RB322

RB223

RB124

RB025

PG

EC

2/A

N6/

RB

626

PG

ED

2/A

N7/

RB

727

AE

RX

D2

28

AE

RX

D3

29

AV

DD

30

AV

SS

31

RB

832

RB

933

RB

1034

AE

TX

ER

R35

VS

S1

36

VD

D2

37

TC

K/R

A1

38

SC

K4

39

SS

440

AE

CR

S41

MII2

_CO

L42

PM

A1/

AE

TX

D3/

PM

ALH

43

PM

ALL

/PM

A0/

AE

TX

D2

44

VS

S2

45

VD

D3

46

AE

TX

D0

47

AE

TX

D1

48

SD

I449

SD

O4

50

USBID/RF351SDA3/SDI3/U1RX/RF252SCL3/SDO3/U1TX/RF853VBUS54VUSB55D-/RG356D+/RG257SCL258SDA259TDI/RA460TDO/RA561VDD462OSC1/CLKI/RC1263OSC2/CLKO/RC1564VSS365AETXCLK66AETXEN67EMDIO68SS1/IC2/RD969PMCS270EMDC71INT072SOSCI/CN1/RC1373SOSCO/T1CK/CN0/RC1474VSS475

OC

2/R

D1

76O

C3/

RD

277

OC

4/R

D3

78P

MD

1279

PM

D13

80P

MW

R81

PM

RD

82P

MD

1483

PM

D15

84V

CA

P/V

DD

CO

RE

85V

DD

586

PM

D11

87P

MD

1088

PM

D9

89P

MD

890

RA

691

RA

792

PM

D0

93P

MD

194

TR

D2/

RG

1495

RG

1296

RG

1397

PM

D2

98P

MD

399

PM

D4

100

TP11

WHITE

SW26JS202011CQN123

456

J16

12

3

C68

0.1u

F

C74

0.1u

F

C72

0.1u

F

TP6WHITE

J17

12

3

TP10

WHITE

TP7WHITE

R89 1K

C70

0.1u

F

EV

B-L

AN

9252-H

BI+

Eth

erCA

T®

Evalu

ation

Bo

ard

Use

r’s Gu

ide

DS

50002333C

-page 46

2015-2016 M

icrochip Technolo

gy Inc.

1

1

D

C

B

A

Digital OUTUTS

PO0

PO1

PO2

PO3

PO4

PO5

PO6

PO7

PO8

PO9

PO10

PO11

PO12

PO13

PO14

PO15

Size:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDGPIOs


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDGPIOs


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDGPIOs

EVB-LAN9252-HBI

D11A

1C

2

D21A

1C

2

D14A

1C

2

R117 1K

D20A

1C

2

R115 1K

R107 1K

R106 1K

D10A

1C

2

R108 1K

R112 1K

D8A

1C

2

R110 1K

R120 1K

D15A

1C

2

R118 1K

R116 1K

D16A

1C

2

R114 1K

D9A

1C

2

D13A

1C

2

R109 1K

R113 1K

D19A

1C

2

D18A

1C

2

D7A

1C

2

R111 1K

R121 1KD22

A1

C2

D17A

1C

2

R119 1K

D12A

1C

2

FIGURE B-8: EVB-LAN9252-HBI+ SCHEMATIC GPIOS

5

5

4

4

3

3

2

2

D

C

B

A

Input = one (Default);Input = Zero (change the Switch position)

Digital INPUTS

GPI0GPI1GPI2

GPI6

GPI3GPI4GPI5

GPI7

GPI8GPI9GPI10

GPI14

GPI12GPI13

GPI15

G

G

G

G

G

G

G

G

G

G

G

G

G

G

G

GGPI11

GPO0

GPI0

GPO1

GPI1

GPO2

GPI2

GPO3

GPI3

GPO4

GPI4

GPO5

GPI5

GPO6

GPI6

GPO7

GPI7

GPO8

GPI8

GPO9

GPI9

GPO10

GPI10

GPO11

GPI11

GPO12

GPI12

GPO13

GPI13

GPO14

GPI14

GPO15

GPI15

3V3

3V3

GPIO0_CONFIG5

GPIO7_CONFIG5

GPIO5_CONFIG5

GPIO4_CONFIG5

GPIO3_CONFIG5

GPIO2_CONFIG5

GPIO1_CONFIG5

GPIO6_CONFIG5

GPIO15_CONFIG5

GPIO14_CONFIG5

GPIO13_CONFIG5

GPIO12_CONFIG5

GPIO11_CONFIG5

GPIO10_CONFIG5

GPIO9_CONFIG5

GPIO8_CONFIG5

R98

10K

SW32

JS102011CQN

12

3

SW39

JS102011CQN

12

3

SW30

JS102011CQN

12

3

R97

10K

R93

10K

R10

410

K

R90

10K

SW37

JS102011CQN

12

3

R10

110

KR

102

10K

R10

510

K

R99

10K

R96

10K

SW45

JS102011CQN

12

3

SW28

JS102011CQN

12

3

SW31

JS102011CQN

12

3

SW34

SW DIP-8

12345678

161514131211109

SW40

SW DIP-8

12345678

161514131211109

R95

10K

R94

10K

R10

010

KR

9210

K

SW43

JS102011CQN

12

3

SW35

JS102011CQN

12

3

SW33

JS102011CQN

12

3

R91

10K

SW29

JS102011CQN

12

3

SW42

JS102011CQN

12

3

R10

310

K

SW38

JS102011CQN

12

3

SW36

JS102011CQN

12

3

SW41

JS102011CQN

12

3

SW44

JS102011CQN

12

3

EV

B-L

AN

9252-H

BI+

Eth

erCA

T®

Evalu

ation

Bo

ard

Use

r’s Gu

ide

DS

50002333C

-page 47

2015-2016 M

icrochip Technolo

gy Inc.

1

1

D

C

B

A

DAC (Analog output)

SW for Output

LED for Input

Default Open

Default OpenJ26 Pin 2 = External VrefShort J26 1-2 for Vfer = 3V3

C87 & C88 = Default DNP Assemble only when Vref is used

n DAC need to be connect to onboard MX.

VREF

3V3

3V3

Switch _IN

LED_OUT

DAC_OUT_ADC2

I2C_SDA_DAC_CTLI2C_SCL_DAC_CTL

Size:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDUART, ADC & DAC


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043




Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043



EVB-LAN9252-HBI

C88

0.1u

FD

NP

R1451K

+C8710uF

16VDNP

U10

MCP4726

VOUT1 VSS2 VDD3

VREFF6SCL5SDA4

R15410K1/10W1%

12

J251 2

J26DNP

12

6

0W

R15310K

1/10W1%

12

FIGURE B-9: EVB-LAN9252-HBI+ SCHEMATIC UART, ADC, &DAC

5

5

4

4

3

3

2

2

D

C

B

A

Temp sensor

POT (Analog Input)

RS-232 I/F

�+5 PICkit™ SERIALANALYZER

Default Short

Short only whe

TxD_232RxD_232

TxD_232

RxD_232

TxD

RxD

DAC_OUT

DAC_OUT

3V3

3V3

3V3

3V3

3V3

3V3

RxDTxD

ADC1 IN

TEMP IN

C80

0.1u

F

+C8210uF16V

C79

0.1u

F

R141 470R 1%J271 2

C760.1uF

C83

0.1u

F

J14

HRD 6pin

123456

POT13352T-1-103LF1

CC

W

2W

IPE

R

3C

W

J24

CONNECTOR DB9-M

594837261

1011

C84

0.1u

FD

NP

TIA/EIA-232

RS-232

U8 <Device>

C1+1

C1-3

C2+4

C2-5

VS+2

VS-6

DIN111

RIN113DOUT114

ROUT112

GND15

VCC16

DIN210

DOUT27ROUT2

9RIN2

8

C81

0.1u

F

U9

TC1047Asot23-3-center3

VS

S3

VOUT2

VDD1

D24

GRN

1A2 C

C78

0.1u

F

C770.1uF

R142100E

1/10W1%

1 2

SW50

sw_pb_2P

R1410K1/11%

12

EV

B-L

AN

9252-H

BI+

Eth

erCA

T®

Evalu

ation

Bo

ard

Use

r’s Gu

ide

DS

50002333C

-page 48

2015-2016 M

icrochip Technolo

gy Inc.

1

1

D

C

B

A

PIM unused GPIOs with GND porbing option

PIM TXD & RXD can't be used in HBI mode. In other modes, TXD & RXD can be extrnally connected to UART

IRQ_PIM32MZ

IRQ_PIM24

PIM_DIG_RC1

PIM_DIG_RC3

AN5_RB5

AN3_RB3

AN0_RB0

AN9_RB9AN8_RB8

AN2_RB11

AN1_RB1

PIM_DIG_RC2

PIM_DIG_RC4

AN4_RB4

PIM_RXPIM_TX

IRQ

Size:

Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDPIM


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDPIM


Part Number:Rev

Date: Sheet of

Chennai India

Project

Name:

Page:

Name:Board

UNG_8043


JUTLANDPIM

EVB-LAN9252-HBI

R1490R DNP

21

3

J23HEADER 14X2

DNP

2468

10121416182022242628

13579111315171921232527

FIGURE B-10: EVB-LAN9252-HBI+ SCHEMATIC PIM 5

5

4

4

3

3

2

2

D

C

B

A

��

RN1 RN2 RN3 RN4

HBI

SPI

SQI

YES DNP DNP DNP

DNP

DNP

YES YESDNP

DNP DNPYES

PIM

U6TX=RPD1U6RX=RPF2

SQ

I_D

1

IRQ_PIM24

IRQ

_PIM

32M

Z

AN0_RB0AN1_RB1

AN3_RB3AN4_RB4AN5_RB5

AN

8_R

B8

AN

9_R

B9

PIM_DIG_RC2PIM_DIG_RC1

PIM_DIG_RC4PIM_DIG_RC3

SQ

I_S

CK

SQI_CS

SQI_D0

AN

2_R

B11

VDDCORE_PIM

PIM_PIN11PIM_PIN12

PIM_PIN14

PIM_PIN10

PIM_PIN10PIM_PIN11PIM_PIN12PIM_PIN14

SQI_SCKSQI_D1SQI_D0SQI_CS

PIM_SPI2_SCK SPI_SCKPIM_SPI2_SDI SPI_SOPIM_SPI2_SDO SPI_SIPIM_SPI2_CS SPI_CS

PIM_RXPIM_TX

3V3

SoC_OSC1SoC_OSC2

SoC_SOSCISoC_SOSCO

AD7_CONFIG3AD6_CONFIG3AD5_CONFIG3

AD

4_C

ON

FIG

3A

D3_

CO

NF

IG3

AD

2_C

ON

FIG

3

AD

1_C

ON

FIG

3A

D0_

CO

NF

IG3

FIFOSEL_LATCH0PME_LATCH1

PIM_MCLR

PGC2

PGD2

SIO

2_C

ON

FIG

5

SIO

3_C

ON

FIG

5

RS

T_G

PIO

RD2RD3

WR_ENB_CONFIG3RD_RDWR_CONFIG3

CS_CONFIG3

GPMC_A1_ALEHI

GPMC_A0_ALE

A4_CONFIG3A3_CONFIG3A2_CONFIG3

SCK_CONFIG5

SCS#_CONFIG5

SIO1_CONFIG5SIO0_CONFIG5

RN2 0E1234 5

678

PIM1

PIM CONN

DNP

123456789

10111213141516171819202122232425

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

757473727170696867666564636261605958575655545352

100

51

RN3 0E1234 5

678

C86

10uF

DN

P

RN1 0E

1234 5

678

C85

0.1u

FD

NP

RN4 0E

1234 5

678


USER’S GUIDE

Appendix C. Bill of Materials (BOM)

C.1 INTRODUCTION

This appendix includes the EVB-LAN9252-HBI+ Evaluation Board Bill of Materials (BOM).


EV

B-L

AN

9252-H

BI+

Eth

erCA

T®

Evalu

ation

Bo

ard

Use

r’s Gu

ide

DS

50002333C

-page 50

2015-2016 M

icrochip Technolo

gy Inc.

Vender Vender P/NMurata GRM21BR61E106KA73L

Murata GRM188R71E104KA01D

Murata GRM188R61C105KA93D

Murata GRM188R71H471KA01D

Murata GRM1885C1H180JA01D

Kemet C0603C223K5RACTU

TDK C1608X5R0J106K080AB



AVX TPSB106K016R0500

Wurth electronics 150 060 GS7 500 0

Wurth electronics 150 060 RS7 500 0

Micro Commercial Co 1N4148W‐TP

Murata BLM18EG221SN1D

Cui Stack PJ‐002AH

FCI 68000‐103HLF

FCI 68000‐102HLF

FCI 67997‐210HLF

FCI 67997‐202HLF

FCI 68000‐106HLF

FCI 68000‐106HLF

FCI 67997‐206HLF

FCI 67997‐232HLF

TE 5‐1814832‐1

TE/AMP 5747840‐4

Bourns Inc. 3352T‐1‐103LF

Fairchild NDS355AN

Item Qty Reference Part PCB Footprint DNP2 2 C2,C4 10uF CAP0805 No

3 34

C3,C5,C6,C8,C10,C11,C13,C14,C15,C16,C17,C18,C21,

C22,C24,C25,C58,C61,C67,C68,C69,C70,C71,C72,C73,

C74,C75,C76,C77,C78,C79,C80,C81,C83

0.1uF CAP0603 No

5 1 C19 1uF CAP0603 No

6 1 C20 470pF CAP0603 No

7 2 C26,C27 18pF CAP0603 No

9 2 C32,C37 0.022uF CAP0603 No

12 1 C62 10uF CAP0603 No

13 2 C63,C64 11pF CAP0603 No

14 2 C65,C66 20pF CAP0603 No

15 1 C82 10uF CAP_B_3528 No

17 22D1,D3,D4,D5,D7,D8,D9,D10,D11,D12,D13,D14,D15,

D16,D17,D18,D19,D20,D21,D22,D23,D24GRN LED0603 No

18 1 D2 Br_Red‐RA LED0603 No

19 1 D6 DIODE SOD123 No

20 5 FB1,FB2,FB3,FB4,FB5 2A/0.05DCR RES0603 No

21 1 J1 SKT_PWR_2R0mm_4A_THRU_RA th_conn_pwrjack_dc‐210_rt No

23 9 J4,J5,J6,J7,J8,J9,J16,J17,J19 HDR_1x3 TH_CONN_1X3P No

24 3 J10,J25,J27 CONN_2P th_conn_1x2p No

25 1 J11 HEADER 5X2 TH_CONN_2X5P No


27 1 J13 DBG ICSP Header TH_CONN_1x6P No

28 1 J14 HRD 6pin TH_CONN_1x6P No



32 2 J21,J22 CONN_5P TH_CONN_SMA‐J‐P‐H‐ST‐TH1 No

34 1 J24 CONNECTOR DB9‐M th_conn_db9_m_rt No

38 1 POT1 3352T‐1‐103LF TH_POT_3352T No

40 1 Q1 NDS355AN_NMOS sot23‐NDS No

Bill o

f Materials (B

OM

)


echnology Inc.

DS

50002333C

-page 51

4 Panasonic ERJ‐3GEY0R00V

4 Panasonic ERJ‐3GEYJ102V

4 ageo America 9C06031A3301FKHFT

4 BOURNS CR0603‐FX‐4700ELF

4 BOURNS CR0603‐FX‐33R0ELF

4 Panasonic ERJ‐3EKF4751V




5 Rohm CR03ERTF1212

5 ageo America 9C06031A49R9FKHFT

5 Panasonic ERJ‐2GE0R00X

5 Vishay CRCW12100000Z0EA



6 C&K 1101M2S3CQE2

6 Panasonic EVQ‐PJU04K or EVQ‐5PN04K

7 urth electronics 418117270904

7 urth electronics 450301014042

72 FCI 68000‐103HLF

7 C&K JS202011CQN

7 TE 1‐1825058‐9

7 Keystone 5000

7 Keystone 5003

7 Keystone 5001

8 ulse Electronics J0011D01BNL

1 7 R1,R15,R29,R61,R62,R87,R122 0R RES0603 No

2 24

R2,R8,R72,R73,R74,R89,R106,R107,R108,R109,R110,

R111,R112,R113,R114,R115,R116,R117,R118,R119,

R120,R121,R140,R145

1K RES0603 No

3 1 R3 3.30K RES0603 No Y

4 2 R4,R141 470R RES0603 No

5 1 R4A 33R RES0603 No

6 1 R5 4.75K RES0603 No

7 26

R6,R69,R70,R71,R146,R153,R154,R76,R79,R80,R90,

R91,R92,R93,R94,R95,R96,R97,R98,R99,R100,R101,

R102,R103,R104,R105

10.0K RES0603 No

8 2 R7,R142 100E RES0603 No

9 1 R9 2.2K RES0603 No

0 1 R10 12.1K RES0603 No

1 8 R11,R12,R13,R14,R25,R26,R27,R28 49.9R RES0603 No Y

3 8 R17,R19,R21,R23,R31,R33,R35,R37 0R RES0402 No

4 2 R24,R38 0R RES1210

0 5 R63,R64,R65,R66,R88 4.7K RES0603 No

1 2 R67,R68 2K RES0603 No

8 1 SW1 SW‐SPDT‐SLIDE sw_ck_1101m2s3cqe2 No

9 3 SW2,SW27,SW50 sw_pb_2P sw_pb_2P No

0 1 SW3 SW DIP‐4/SM TH_SW_DIP4 No W

2 8 SW5,SW6,SW7,SW8,SW9,SW10,SW24,SW25 JS102011CQN TH_SW_SPST_3P_10x2p5 No W

A 16

SW5,SW6,SW7,SW8,SW9,SW10,SW24,SW25,SW28,

SW29,SW30,SW31,SW32,SW33,SW35,SW36,SW37,

SW38,SW39,SW41,SW42,SW43,SW44,SW45

HDR_1x3 TH_SW_SPST_3P_10x2p5 No

3 12SW11,SW12,SW13,SW14,SW15,SW16,SW17,SW18,

SW19,SW20,SW21,SW26JS202011CQN TH_SW_DPDT_6P No

4 2 SW34,SW40 SW DIP‐8 SW_DIP_SMT_8P‐ADE08S04 No

5 1 TP1 RED TH_TP_60D40 No

6 1 TP2 ORANGE TH_TP_60D40 No

7 3 TP3,TP4,TP9 BLACK TH_TP_60D40 No

0 2 T1,T2 Pulse ‐ J0011D01BNL th_conn_pulse_rj45_j0026 No P

EV

B-L

AN

9252-H

BI+

Eth

erCA

T®

Evalu

ation

Bo

ard

Use

r’s Gu

ide

DS

50002333C

-page 52

2015-2016 M

icrochip Technolo

gy Inc.

Murata OKR‐T/3‐W12‐C

TI TPS3125L30DBVR

TI SN74LVC1G14DBVR

Microchip LAN9252

Microchip 24FC512‐I/P

Microchip PIC32MX795F512L‐80I/PT

TI TRS3232IDR

Microchip TC1047AVNBTR

Microchip MCP4726A0T‐E/CH

Cardinal Components Inc. CSM1Z‐A5B2C5‐40‐25.0D18‐F

ECS INC ECS‐.320‐12.5‐13X

Citizen Finetech HC‐49/U‐S8000000ABJB

81 1 U1 3_Amp TH_DC‐DC_VERT_5PIN_P67 No

82 1 U2 TPS3125 SOT23_5 No

83 1 U3 74LVC1G14 SOT23_5 No

84 1 U4 LAN9252 IC_QFN64 No

85 1 U5 24FC512 IC_DIP8_300 No

87 1 U7 PIC32MX775F256L IC_TQFP100_12x12x1‐0p4mm No

88 1 U8 TRS3232_SO16 IC_SO16 No

89 1 U9 TC1047A sot23‐3 No

90 1 U10 MCP4726 SOT23_6 No

91 1 Y1 25.000MHz XTAL_HCM49 No

92 1 Y2 32Khz th_xtal_ecs‐31x‐13‐32khz No

93 1 Y3 8 Mhz th_hc49us_2p No

DNP Components

1 1 C1 4.7uF CAP0603 DNP

4 4 C7,C9,C12,C23 1.0uF CAP0603 DNP

8 8 C28,C29,C30,C31,C33,C34,C35,C36 10pF CAP0402 DNP

10 19C38,C39,C40,C41,C42,C43,C44,C45,C47,C49,C51,

C53,C55,C57,C59,C60,C84,C85,C880.1uF CAP0603 DNP

11 7 C46,C48,C50,C52,C54,C56,C87 10uF CAP_B_3528 DNP

16 1 C86 10uF CAP0603 DNP

22 2 J2,J3 FTLF1217P2 CONN_FX_SFP_FTLF1217P2 DNP

29 1 J15 HEADER 10x4 TH_CONN_4X10P DNP

33 1 J23 HEADER 14X2 TH_CONN_2x14P DNP

35 1 J26 CONN_2P th_conn_1x2p DNP

36 4 L1,L2,L3,L4 1uH L0805 DNP

37 1 PIM1 PIM CONN TH_CONN_PIM100 DNP

39 2 P1,P2 HEADER 23x2 TH_CONN_2X23P DNP

52 8 R16,R18,R20,R22,R30,R32,R34,R36 0R RES0402 DNP

55 4 R39,R40,R43,R44 82R RES0603 DNP

56 4 R41,R42,R45,R46 49.9R RES0603 DNP

57 2 R47,R48 100E RES0603 DNP

Bill o

f Materials (B

OM

)


echnology Inc.

DS

50002333C

-page 53

5

5

6

6

6

6

7

7

7

8

8 4 R49,R50,R51,R52 130R RES0603 DNP

9 12 R53,R54,R55,R56,R57,R58,R59,R60,R81,R82,R84,R85 4.7K RES0603 DNP

2 19R75,R77,R78,R123,R124,R125,R126,R127,R128,R129,R130,

R131,R132,R133,R134,R135,R136,R137,R13810K RES0603 DNP

4 2 R83,R86 2K RES0603 DNP

5 4 R139,R143,R144,R152 0R RES0603 DNP

7 1 R149 0R RES0603‐3 DNP

1 1 SW4 SW DIP‐4/SM TH_SW_DIP4 DNP

8 1 TP5 ORANGE TH_TP_60D40 DNP

9 5 TP6,TP7,TP8,TP10,TP11 WHITE TH_TP_60D40 DNP

6 1 U6 24FC512 IC_DIP8_300 DNP


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EVB-LAN9252-HBI+ EtherCAT Evaluation Board User's GuideEVB-LAN9252-HBI+ ETHERCAT® EVALUATION BOARD...

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Transcript of EVB-LAN9252-HBI+ EtherCAT Evaluation Board User's GuideEVB-LAN9252-HBI+ ETHERCAT® EVALUATION BOARD...