Evangeline F.Y. Young Department of Computer Science ...fyyoung/YoungCV - web.pdf · Department of...

Extended Curriculum Vitae Evangeline F.Y. Young

Department of Computer Science & Engineering The Chinese University of Hong Kong

April 26, 2011

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Table of Contents 1. Personal and Employment Details………………………….....…….2

2. Awards and Highlights ……………………………………….……...3

3. Research....……………………………………………………………...4

3.1 Journal Publications ……………………..........................……..4

3.2 Conference Publications ………………..………………...……7

3.3 Book Chapters……………………………………..…………...12

3.4 Funding………………………………………………..………..12

3.5 Awards in Research …………………………………..……….14

3.6 Other Contributions……………………………………..…….15

4. Teaching…………………………………………………….………....16

4.1 Classroom Teaching…………………………………….….....16

4.2 Postgraduate Supervision……………………………….…...17

4.3 Awards in Teaching…………………………………….…….19

5. Service…………………………………….…………………….……..20

5.1 Service to Department……………..………………....….…....20

5.2 Service to Faculty…………………..…………………..……...20

5.3 Service to University/College……..…………………........…20

5.4 External Service…..………………………………………........21

5.5 Awards in Service..……………………………………..…......21

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1. Personal and Employment Details Evangeline F.Y. Young

Department of Computer Science and Engineering

The Chinese University of Hong Kong

Academic Qualifications:

Ph.D. in Computer Science, The University of Texas at Austin, 1999

Research Topics: VLSI Computer-Aided Design

M.Phil. in Computer Science, The Chinese University of Hong Kong

Research Topics: Neural Network

B.Sc. in Computer Science, The Chinese University of Hong Kong

Employment History:

Associate Professor, The Chinese University of Hong Kong, 2004 – present.

Assistant Professor, The Chinese University of Hong Kong, 1999 – 2004.

Summer Intern, Intel Strategic CAD Labs, summer 1997.

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2. Awards and Highlights Awards in Research: 1. Winner of the ISPD 2011 Routability-Driven Placement Contest organized by IBM.1

2. Best Paper Award Nomination from International Symposium on Physical

Design (ISPD) 2011.

3. First Runner-up in the ISPD 2010 High Performance Clock Network Synthesis

Contest organized by IBM.2

4. Best Paper Award Nomination from IEEE International Conference on

Computer-Aided Design (ICCAD) 2010.

5. Best Paper Award Nomination from IEEE Asian South Pacific Design

Automation Conference (ASP-DAC) 2010, 2009 and 2003.

Awards in Teaching: 1. VC’s Exemplary Teaching Award from the Chinese University of Hong Kong

2001-02.

2. Faculty Exemplary Teaching Awards from the Chinese University of Hong Kong

2001-02 and 2004-05.

3. Department’s Exemplary Teaching Awards from the Chinese University of Hong

Kong 2000-01 and 2001-02.

Awards of Graduate Students under my Supervision: 1. Outstanding Master Thesis Award from the Engineering Faculty 2010.

2. Best Master Paper Awards in the ACM (Hong Kong) Postgraduate Research Day

2003 and 2004.

Awards in Service: 1. Departmental Exemplary Service Award 2008 - 09.

Professional Service: I have served in the past few years in the program committees of a number of

important international conferences in VLSI CAD, e.g., ICCAD, ISPD, ASP-DAC and

GLSVLSI. I also serve as associate editor for Integration, the VLSI Journal and for the

IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems.

1,2 EETimes coverage of the contests: http://www.eetimes.com/electronics-news/4088267/IBM-benchmarks-prod-microprocessor-designers http://www.eetimes.com/electronics-news/4215124/ISPD-reveals-3-D--maskless-lithography-trends-

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3. Research My research interests are in the area of VLSI Computer-Aided Design and my focus

is on the physical design automation. My research spans the major areas in VLSI

CAD including floorplanning, placement and routing. Besides these major areas, I

also research and publish in some advanced and specialized areas, like biochip

design and analog design automation. My research focus can be summarized as

follows:

Advanced Floorplanning and Placement Problems

Global Routing – Theory and Practice

Analog Automation

Biochip Design

3.1 Journal Publications: J.1 MSV-driven Floorplanning, Qiang Ma, Zaichen Qian, Evangeline F.Y. Young

and Hai Zhou, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems. To appear.

J.2 Placement and Routing for Cross-Referencing Digital Microfluidic Biochips,

Zigang Xiao and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems. To appear.

J.3 On the Construction of Optimal Obstacle-avoiding Rectilinear Steiner

Minimum Tree, Liang Li, Tao Huang and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 30(5):718-731, 2011.

J.4 Bus Matrix Synthesis based on Steiner Graphs for Power Efficient

System-on-Chip Communications, R. Wang, Y. Zhang, N.C. Chou, Evangeline F.Y. Young, C.K. Cheng and R. Graham, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 30(2):167-179, 2011.

J.5 Simultaneous Handling of Symmetry, Common Centroid and General

Placement Constraints, Qiang Ma, Linfu Xiao, Yiu-cheong Tam and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 30(1):85-95, 2011.

J.6 Complexity of 3-D Floorplans by Analysis on Graph Cuboidal Dual Hardness,

Renshen Wang, Evangeline F.Y. Young and Chung-kuan Cheng, ACM

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Transaction on Design Automation of Electronic Systems, 15(4), Article 33, 2010. J.7 Multi-voltage Floorplan Design, Qiang Ma and Evangeline F.Y. Young, IEEE

Transactions of Computer-Aided Design of Integrated Circuits and Systems, 29(4):607-617, 2010.

J.8 Handling Routability in Floorplan Design with Twin Binary Trees, Steve T.W.

Lai, Evangeline F.Y. Young and Chris C.N. Chu, Integration, the VLSI Journal. 42(4):449-456, 2009.

J.9 Block Flipping and White Space Distribution for Wirelength Minimization ,

Chiu-Wing Sham and Evangeline F.Y. Young, Integration, the VLSI Journal, Vol. 42, No. 2, p246-253, February, 2009.

J.10 Congestion Prediction in Early Stages of Physical Design, Chiu-Wing Sham,

Evangeline F.Y. Young and Jingwei Lu, ACM Transaction on Design Automation of Electronic Systems, Vol. 14, No. 1, Article No. 12 (12:1-12:18), January, 2009.

J.11. Multi-bend Bus Driven Floorplanning, Jill H.Y. Law and Evangeline F.Y.

Young, Integration, the VLSI Journal, 41(2):306-316, 2008. J.12 Optimizing Wirelength and Routability by Searching Alternative Packings in

Floorplanning, Chiu-Wing Sham, Evangeline F.Y. Young and Hai Zhou, ACM Transaction on Design Automation of Electronic Systems, Vol.13, No.1, Article No.21 (21:1-21:13), January, 2008.

J.13 Wire Retiming Problem with Net Topology Optimization, Dennis K.Y. Tong,

Evangeline F.Y. Young, Chris Chu and Sampath Dechu, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 26(9):1648-1660, 2007.

J.14 Test Scheduling for BISTed Embedded SRAMs with Data Retention Faults ,

Qiang Xu, Baosheng Wang, Andre Ivanov and F. Y. Young, IEE Proceedings: Computers and Digital Techniques, Special Issue on ETS'06, Vol.1, pp.256-264, May 2007.

J.15 Area Reduction by Deadspace Utilization on Interconnect Optimized Floorplan,

Chiu-Wing Sham and Evangeline F. Y. Young, ACM Transaction on Design Automation of Electronic Systems, 12(1):1-11, 2007.

J.16 Placement Constraints in Floorplan Design, Evangeline F.Y. Young, Chris C.N.

Chu and M.L. Ho, IEEE Transactions on Very Large Scale Integration Systems, 12(7):745-745, 2004.

J.17 Non-Rectangular Shaping and Sizing of Soft Modules for Floorplan Design

Improvement, Chris C.N. Chu and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 23(1):71-79, 2004.

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J.18 Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning, Arthur W.K. Mak and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 22(7):952-959, 2003.

J.19 Twin Binary Sequences: A Non-redundant Representation for General

Non-slicing Floorplan, Evangeline F.Y. Young, Chris C.N. Chu and Zion Cien Shen, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 22(4):457-469, 2003.

J.20 Routability Driven Floorplanning with Buffer Block Planning, C.W. Sham and

Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 22(4):470-480, 2003.

J.21 Slicing Floorplan with Clustering Constraint, W.S. Yuen and F.Y. Young, IEEE

Transactions of Computer-Aided Design of Integrated Circuits and Systems, 22(5):654-658, 2003.

J.22 Handling Soft Modules in General Nonslicing Floorplan using Lagrangian

Relaxation, F.Y. Young, Chris C.N. Chu, W.S. Luk and Y.C. Wong, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 20(5):687-692, 2001.

J.23 On Extending Slicing Floorplans to Handle L/T-shaped Modules and

Abutment Constraints, F.Y. Young, Hannah H. Yang and D.F. Wong, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 20(6):800-807, 2001.

J.24 Slicing Floorplan with Range Constraints, F.Y. Young, D.F. Wong and Hannah

H. Yang, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 19(2):272-278, 2000.

J.25 Slicing Floorplan with Boundary Constrants, F.Y. Young, D.F. Wong and

Hannah H. Yang, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 18(9), pp.1385-1389, 1999.

J.26 Generation of Universal Series-Parallel Boolean Functions, F.Y. Young, C.N.

Chu and D.F. Wong, Journal of the ACM, 46(3), pp.416-435, 1999. J.27 How Good are Slicing Floorplans, F.Y. Young and D.F. Wong, Integration, the

VLSI Journal, Vol.23, pp.61-73, 1997. J.28 A Chinese Dictionary System Based on Fuzzy Logic and Object-Oriented

Approach, K.S. Leung, Y. Fan and F.Y. Young, Computer Processing of Chinese and Oriental Languages - An International Journal of the Chinese Language Computer

Society, World Scientific Publishing, Vol.6, No.2, pp.205-219, 1992, Canada.

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3.2 Conference Publications: C.1 An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees

among Complex Obstacles, Tao Huang and Evangeline F. Y. Young, Proceedings ACM/IEEE Design Automation Conference (DAC), 2011.

C.2 An Optimal Algorithm for Layer Assignment of Bus Escape Routing on PCBs,

Qiang Ma, Evangeline F. Y. Young and Martin D. F. Wong, Proceedings ACM/IEEE Design Automation Conference (DAC), 2011.

C.3 Grid-to-Ports Clock Routing for High Performance Microprocessor Designs,

Haitong Tian, Wai-Chung Tang, Evangeline F.Y. Young and C. N. Sze, International Symposium on Physical Design (ISPD), 2011. Best Paper Award Nomination.

C.4 A Monte-Carlo Floating-Point Unit for Self-Validated Arithmetic, Jackson

Ho-Chuen Yeung, Evangeline F. Y. Young and Philip Leong, Proceedings ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2011.

C.5 A Provably Good Approximation Algorithm for Rectangle Escape Problem

with Application to PCB Routing, Qiang Ma, Hui Kong, Martin D. F. Wong and Evangeline F. Y. Young, Proceedings IEEE Asian South Pacific Design Automation Conference (ASP-DAC), 2011.

C.6 Obstacle-avoiding Rectilinear Steiner Minimum Tree Construction: An Optimal

Approach, Tao Huang and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2010. Best Paper Award Nomination.

C.7 Practical Placement and Routing Techniques for Analog Circuit Designs, Linfu

Xiao, Evangeline F.Y. Young, Xiaoyong He and K.P. Pun, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2010.

C.8 Local Clock Skew Minimization Using Blockage-aware Mixed Tree-Mesh Clock

Network, Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2010.

C.9 Droplet-routing-aware Module Placement for Cross-referencing Biochips,

Zigang Xiao and Evangeline F.Y. Young, International Symposium on Physical Design (ISPD), 2010.

C.10 Physical Synthesis of Bus Matrix for High Bandwidth Low Power On-chip

Communications, Renshen Wang, Evangeline F.Y. Young, Ronald Graham and

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Chung-Kuan Cheng, International Symposium on Physical Design (ISPD), 2010. C.11 A Dual-MST Approach for Clock Network Synthesis, Jingwei Lu, Wing-Kai

Chow, Chiu-Wing Sham and Evangeline F.Y. Young, Proceedings IEEE Asian South Pacific Design Automation Conference (ASP-DAC), 2010. Best Paper Award Nomination.

C.12 CrossRouter: A Droplet Router for Cross-Referencing Digital Microfluidic

Biochips, Zigang Xiao and Evangeline F.Y. Young, Proceedings IEEE Asian South Pacific Design Automation Conference (ASP-DAC), 2010.

C.13 Fixed-outline Thermal-aware 3D Floorplanning, Linfu Xiao, Subarna Sinha,

Jingyu Xu and Evangeline F.Y. Young, Proceedings IEEE Asian South Pacific Design Automation Conference (ASP-DAC), 2010.

C.14 Generation of Optimal Obstacle-avoiding Rectilinear Steiner Minimum Tree,

Liang Li, Zaichen Qian and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2009.

C.15 Multi-voltage Floorplan Design with Optimal Voltage Assignment, Zaichen

Qian and Evangeline F.Y. Young, International Symposium on Physical Design (ISPD), 2009.

C.16 Analog Placement with Common Centroid and 1-D Symmetry Constraints,

Linfu Xiao and Evangeline F.Y. Young, Proceedings IEEE Asian South Pacific Design Automation Conference (ASP-DAC), 2009. Best Paper Award Nomination.

C.17 Obstacle-avoiding Rectilinear Steiner Tree Construction, Liang Li and

Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2008.

C.18 Network Flow Based Power Optimization under Timing Constraints in

MSV-driven Floorplanning, Qiang Ma and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2008.

C.19 3-D Floorplanning using Labeled Tree and Dual Sequences , Renshen Wang,

Evangeline F.Y. Young, Yi Zhu, Fan Chung Graham, Ronald Graham and Chung-Kuan Cheng, International Symposium on Physical Design (ISPD), 2008.

C.20 TCG-based Bus Driven Floorplanning, Tilen Ma and Evangeline F.Y. Young,

Proceedings IEEE Asian South Pacific Design Automation Conference (ASP-DAC), 2008.

C.21 Voltage Island-Driven Floorplanning, Qiang Ma and Evangeline F.Y. Young,

Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2007.

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C.22 Analog Placement with Common Centroid Constraints, Qiang Ma, Evangeline F.Y. Young and K.P. Pun, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2007.

C.23 Post-placement Voltage Island Generation, Royce L.S. Ching, Evangeline F.Y.

Young, Kevin C.K. Leung and Chris Chu, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2006.

C.24 Analog Placement with Symmetry and Other Placement Constraints,

Yiu-cheong Tam, Evangeline F.Y. Young and Chris Chu, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), 2006.

C.25 Optimal Cell Flipping in Placement and Floorplanning, Chiu-wing Sham,

Evangeline F.Y. Young and Chris Chu, Proceedings ACM/IEEE Design Automation Conference (DAC), 2006.

C.26 Retention-Aware Test Scheduling for BISTed Embedded SRAMs, Qiang Xu,

Baosheng Wang and Evangeline F.Y. Young, IEEE European Test Symposium, pp.83-88, 2006.

C.27 Block Alignment in 3D Floorplan using Layered TCG, Jill H.Y. Law, Evangeline

F.Y. Young and Royce L.S. Ching, ACM Great Lakes Symposium on VLSI, pp.376-380, 2006.

C.28 Shuttle Mask Floorplanning with Modified -Restricted Grid, Royce L.S. Ching

and Evangeline F.Y. Young, ACM Great Lakes Symposium on VLSI, pp.85-90, 2006.

C.29 Multi-Bend Bus Driven Floorplanning, Jill H.Y. Law and Evangeline F.Y.

Young, International Symposium on Physical Design (ISPD), pp.113-120, 2005. C.30 Congestion Prediction in Early Stages, Chiu-wing Sham and Evangeline F.Y.

Young, International Workshop on System-Level Interconnect Prediction, pp.91-98, 2005.

C.31 Congestion Prediction in Floorplanning, Chiu-wing Sham and Evangeline F.Y.

Young, IEEE Asian South Pacific Design Automation Conference (ASP-DAC), pp.1107-1110, 2005.

C.32 Multilevel Interconnect-Driven Floorplanning, Evangeline F.Y. Young and

Joseph C.S. Lau, Mid-West Symposium on Circuits and Systems, pp., 2005. C.33 Area Reduction on Interconnect Optimized Floorplan using Deadspace

Utilization, Chiu-wing Sham and Evangeline F.Y. Young, Mid-West Symposium on Circuits and Systems, pp., 2005.

C.34 Performance-Driven Register Insertion in Placement, Dennis K.Y. Tong and

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Evangeline F.Y. Young, International Symposium on Physical Design (ISPD), pp.53-60, 2004.

C.35 Retiming with Interconnect and Gate Delay, Chris C.N. Chu, Evangeline F.Y.

Young, Dennis K.Y. Tong and Sampath Dechu, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), pp.221-226, 2003.

C.36 Clustering Based Acyclic Multi-way Partitioning, Eric S.H. Wong, Evangeline

F.Y. Young and W.K. Mak, Proceedings of the 13th ACM Great Lakes Symposium on VLSI, pp.203-206, 2003.

C.37 A New and Efficient Congestion Evaluation Model in Floorplanning: Wire

Density Control with Twin Binary Trees, Steve T.W. Lai, Evangeline F.Y. Young and Chris C.N. Chu, Proceedings of Design, Automation and Test in Europe (DATE), 2003.

C.38 Fast Buffer Planning and Congestion Optimization in Interconnect-driven

Floorplanning, Keith K.C. Wong and Evangeline F.Y. Young, IEEE Asian South Pacific Design Automation Conference (ASP-DAC), pp.411-416, 2003. Best Paper Award Nomination.

C.39 Interconnect-Driven Floorplanning by Searching Alternative Packings, Bruce

C.W. Sham, Evangeline F.Y. Young and Hai Zhou, IEEE Asian South Pacific Design Automation Conference (ASP-DAC), pp.417-422, 2003.

C.40 Twin Binary Sequences: A Non-redundant Representation for General

Non-slicing Floorplan, Evangeline F.Y. Young, Chris C.N. Chu and Zion Cien Shen, International Symposium on Physical Design (ISPD), pp.196-201, 2002.

C.41 Routability Driven Floorplanner with Buffer Block Planning, C.W. Sham and

Evangeline F.Y. Young, International Symposium on Physical Design (ISPD), pp.50-55, 2002.

C.42 Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning,

Wai-Kei Mak and Evangeline F.Y. Young, International Symposium on Physical Design (ISPD), pp.190-195, 2002.

C.43 Congestion Estimation with Buffer Planning in Floorplan Design, C.W. Sham,

W.C. Wong and Evangeline F.Y. Young, Proceedings of Design, Automation and Test in Europe (DATE), pp.696-701, 2002.

C.44 Non-rectangular Shaping and Sizing of Soft Modules in Floorplan Design,

Chris C.N. Chu and Evangeline F.Y. Young, Proceedings of Design, Automation and Test in Europe (DATE), pp.1101, 2002.

C.45 A Unified Method to Handle All Kinds of Placement Constraints in General

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Non-slicing Floorplan, F.Y. Young, Chris C.N. Chu and M.L. Ho, IEEE Asian South Pacific Design Automation Conference (ASP-DAC), pp.661-667, 2002.

C.46 Slicing Floorplans with Clustering Constraints, W.S. Yuen and F.Y. Young,

IEEE Asian South Pacific Design Automation Conference (ASP-DAC), pp.503-508, 2001.

C.47 On Extending Slicing Floorplans to Handle L/T-shaped Modules and

Abutment Constraints, F.Y. Young, Hannah H. Yang and D.F. Wong, Conference on Chip Design Automation, 16th World Computer Congress, August, 2000, pp.269-276.

C.48 Floorplan Area Minimization using Lagrangian Relaxation, F.Y. Young, Chris

C.N. Chu, W.S. Luk and Y.C. Wong, International Symposium on Physical Design (ISPD), pp.174-179, 2000.

C.49 Integrated Floorplanning and Interconnect Planning, H.M. Chen, H. Zhou, F.Y.

Young, D.F. Wong, Hannah H. Yang and Naveed Sherwani, Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), pp.354-357, 1999.

C.50 Slicing Floorplans with Range Constraints, F.Y. Young and D.F. Wong,

International Symposium on Physical Design (ISPD), pp.97-102, 1999. C.51 Slicing Floorplans with Boundary Constraints, F.Y. Young and D.F. Wong,

IEEE Asian South Pacific Design Automation Conference (ASP-DAC), pp. 17-20, 1999.

C.52 Slicing Floorplans with Pre-placed Modules, F.Y. Young and D.F. Wong,

Proceedings IEEE International Conference on Computer-Aided Design (ICCAD), pp.252-258, 1998.

C.53 How Good are Slicing Floorplans?, F.Y. Young and D.F. Wong, International

Symposium on Physical Design (ISPD), pp.144-149, 1997. C.54 On the Construction of Universal Series-Parallel Functions for Logic Module

Design, F.Y. Young and D.F. Wong, IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp.482-488, 1997.

C.55 Parallel implementation of partially connected recurrent network, F.Y. Young

and L.W. Chan, IEEE Conference on Neural Networks, Orlando, Vol.4, pp.2058-2063, 1994.

C.56 Chaos in recurrent networks, L.W. Chan and F.Y.Young, International

Symposium on Speech, Image Processing and Neural Networks, Hong Kong, Vol.1, pp.225-229, 1994.

C.57 Using recurrent network for time series prediction, Lai wan Chan and

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F.Y.Young, World Congress on Neural Networks, Portland, Vol.4, pp.332-336, 1993.

C.58 Ring-structured recurrent neural network, Lai wan Chan and F.Y. Young,

World Congress on Neural Networks, Portland, Vol.4, pp.328-331, 1993. C.59 Sequence recognition using recurrent backpropagation network, F.Y. Young

and L.W. Chan, Proceedings of The International Joint Conference on Neural Networks, Beijing, China, Vol.2, pp.557-562, 1992.

3.3 Book Chapters Evangeline F.Y. Young, “Floorplan Representations”, Book Chapter in The Handbook of Algorithms for VLSI Physical Design Automation, CRC Press. Cheng-kok Koh, Evangeline F.Y. Young and Yao-Wen Chang, “Buffer Planning”, Book Chapter in The Handbook of Algorithms for VLSI Physical Design Automation, CRC Press. Evangeline F.Y. Young, “Slicing Floorplan Orientation, 1983; Stockmeyer”, Entry in Encyclopedia of Algorithms, Springer.

3.4 Funding

1. Title: A Unified Method to Handle all Placement Constraints in Floorplan Design

(PI)

Source: CUHK Direct Grant (Project ID: 2050219)

Duration: 1999 - 2002

Amount: HKD 150,000

2. Title: Interconnect-Driven Multilevel Floorplan Design (PI)

Source: Hong Kong RGC Earmarked Research Grant (Reference:

CUHK4231/01E)

Duration: 2001 - 2004

Amount: HKD 387,248

Co-I: Professor Martin D.F. Wong and Dr. Hannah H. Yang

3. Title: Interconnect-Driven Floorplanning for 3-D Chips (PI)

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CUHK4188/03E)

Duration: 2003 - 2005

Amount: HKD 377,149

4. Title: Retiming in Physical Planning of System-on-Chips (PI)


Duration: 2004 - 2006

Amount: HKD 150,000

5. Title: Architectural-Level Global Interconnect Planning (PI)


Duration: 2005 - 2007

Amount: HKD 65,360

6. Title: Shuttle Mask Floorplanning (PI)


CUHK4181/06E)

Duration: 2006 – 2008

Amount: HKD 356,000

7. Title: Voltage Island Partitioning and Floorplanning (PI)


CUHK4184/07E)

Duration: 2007 – 2009

Amount: HKD 418,000

8. Title: Optimal Block Orientation for Interconnect Issues during Placement and

Floorplanning (Co-I)


Polyu5262/07E)

Duration: 2007 – 2009

Amount: HKD 418,000

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PI: Dr. Chiu-Wing Sham

Other Co-I: Professor Chong-Nuen Chu

9. Title: Placement with Analog Topological Constraints (PI)


CUHK4189/08E)

Duration: 2009 – 2011

Amount: HKD 528,152

10. Title: Voltage Scaling for Low Power Design (PI)


Duration: 2010 – 2011

Amount: HKD 62,000

11. Title: New Interconnect-Centered VLSI/CAD Techniques for High-Performance

ASIC Designs (Co-I)

Source: Innovation & Technology Commission-Innovation and Technology

Support Programme

Duration: 2010 – 2011

Amount: HKD 983,250

PI: Professor David Y.L. Wu

3.5 Awards in Research 1. Winner of the ISPD 2011 Routability-Driven Placement Contest organized by

IBM.

2. Best Paper Award Nomination from International Symposium on Physical

Design (ISPD) 2011.

3. First Runner-up in the ISPD 2010 High Performance Clock Network Synthesis

Contest organized by IBM.

4. Best Paper Award Nomination from IEEE International Conference on

Computer-Aided Design (ICCAD) 2010.

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5. Best Paper Award Nominations from the IEEE Asian South Pacific Design

Automation Conference (ASP-DAC) 2010, 2009 and 2003.

3.6 Other Contributions

3.6.1 Service on Editorial Boards 1. Associate Editor for the IEEE Transactions of Computer-Aided Design of

Integrated Circuits and Systems from January 2010 to present. 2. Associate Editor for Integration, the VLSI Journal from May 2011 to present.

3.6.2 Organization of Conferences Program Committees of: 1. IEEE International Conferences of Computer-Aided Design 2007, 2008, 2009. 2. International Symposium on Physical Design 2003, 2004, 2009, 2010, 2011. 3. IEEE Asian South Pacific Design Automation Conference 2005, 2006, 2008, 2009,

2010. 4. ACM Great Lakes Symposium on VLSI 2007, 2008, 2009, 2010, 2011. Organizing Committees of: 1. Applied Reconfigurable Computing Symposium 2012 (Local Co-chair). 2. ACM (Hong Kong) Postgraduate Research Day 2003, 2004.

3. IEEE International Conference on Field-Programmable Technology 2002 (Publicity).

4. International Conference on Intelligent Data Engineering and Automated Learning 2000

Session Chairs of: 1. International Conference of Computer-Aided Design 2008. 2. Asian South Pacific Design Automation Conference 2005, 2006, 2008. 3. Design, Automation and Test in Europe 2002.

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4. Teaching

4.1 Classroom Teaching I have taught the following courses in the past six years:

1. CSCI 3130 Formal Languages and Automat Theory 2. CSCI 3190 Introduction to Discrete Mathematics and Algorithms 3. CENG 5270 EDA for Physical Design of Digital Systems 4. GES1810 Perspectives in Engineering and Technology

The first two courses are undergraduate major required courses for the CS students and the CE students respectively. Their objectives are to equip students with the essential background knowledge to understand Computer Science and Computer Engineering from a solid mathematical perspective. The third course is a graduate level course on VLSI CAD. I aim at bringing the students up-to-date knowledge of the research directions and methodologies in VLSI CAD or other related areas in order to prepare students to do research in these fields. The last course is a general education course offered for the Shaw College and shared by a number of teachers in the Engineering Faculty. The teaching evaluations of these courses are summarized below:

Year Course Code Mean Score Adjusted Mean Score

2004 - 05 T1 CSC 3130 - 5.52 (4.86)

2004 - 05 T2 CEG 5270 - 5.67 (4.88)

2005 - 06 T1 CSC 3130 - 5.31 (4.82)

2005 - 06 T2 CEG 5270 - 5.50 (4.98)

2006 - 07 T1 CSC 3130 - 5.42 (4.85)

2006 - 07 T2 CEG 5270 - 5.60 (4.94)

2007 - 08 T1 CSC 3130 - 5.10 (4.81)

2007 - 08 T2 CEG 5270 - 5.78 (5.30)

2008 - 09 T1 CSC 3190 4.67 4.89 (4.75)

2008 - 09 T1 GES 1810 5.14 5.16

2008 - 09 T2 CEG 5270 5.75 5.75 (5.34)

2009 - 10 T1 CSC 3190 4.90 (4.85) 5.00 (4.99)

2010 - 11 T2 CSCI 3190 - 5.40 The scores in brackets are departmental average and those marked by “-“ are not available. Note that I also taught the general education course from 2004 to 2008 but the scores are not available to me for those years. All the scores are in the scale of [1(worst) - 6(best)]

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4.2 Postgraduate Supervision This section lists all the current or former graduate students studying under my supervision.

Ph.D. Students Supervised: 1. Miss Xu He (2010 – present)

Thesis Title: Routability-Driven Placement

2. Mr. Tao Huang (2009 – present) Thesis Title: Rectilinear Steiner Minimum Tree Construction Award: Best Paper Award Nomination from the IEEE International Conference on Computer-Aided Design 2010

3. Mr. Linfu Xiao (2007 – present)

Thesis Title: A Practical System for Analog Circuit Layout Automation Award: Best Paper Award Nomination from the IEEE Asian South Pacific Design Automation Conference 2009

4. Dr. Bruce Chiu-Wing Sham (2003 – 06) Thesis Title: Interconnect Planning in Physical Design in VLSI Current Status: Lecturer in Polytechnic University

Ph.D. Students Co-supervised: 1. Mr. Jackson Ho-Chuen Yeung (2010 – present)

Thesis Title: To be determined

M.Phil. Students Supervised: 1. Mr. Fuqian Qian (2010 – present)

Thesis Title: Clock Tree Construction with Process Variation

2. Mr. Guxin Cui (2009 – present) Thesis Title: Analog Automation

3. Mr. Haitong Tian (2009 – present) Thesis Title: Clock Routing for High Performance Microprocessor Designs Award: Best Paper Award Nomination from the International Symposium on Physical Design 2011 Current Status: Admitted into the Ph.D. program in UIUC

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4. Miss Yan Jiang (2009 – 11) Thesis Title: Fixed Outlined Bus-Driven Floorplanning

5. Mr. Zigang Xiao (2008 – 10) Thesis Title: Placement and Routing for Cross-Referencing Digital Microfluidic Biochips Current Status: Ph.D. student in UIUC

6. Mr. Zaichen Qian (2008 – 10) Thesis Title: Low Power Design in Layout and System Levels

7. Mr. Liang Li (2007 – 09) Thesis Title: Obstacle-Avoiding Rectilinear Steiner Tree Awards: Outstanding Master Thesis Award from the Engineering Faculty 2010

8. Mr. Qiang Ma (2006 – 08) Thesis Title: Voltage Island-Driven Floorplanning Current Status: Ph.D. student in UIUC

9. Mr. Kevin Chi-Kwan Leung (2005 – 07) Thesis Title: Predictive Floorplanning with Fixed Outline Constraints

10. Mr. Tilen Ma (2005 – 07) Thesis Title: TCG-based Bus-driven Floorplanning

11. Mr. Royce Lap-Sze Ching (2004 – 06) Thesis Title: Reticle Floorplanning and Voltage Island Partitioning

12. Miss Jill Hoi-Ying Law (2003 – 05) Thesis Title: Bus-Driven Floorplanning

13. Mr. Dennis Ka-Yau Tong (2002 – 04) Thesis Title: Circuit Retiming in Physical Design Award: Best Master Paper Award in the ACM (Hong Kong) Postgraduate Research Day 2004

14. Mr. Eric Sze-Hon Wong (2001 – 03) Thesis Title: Delay Driven Multi-Way Circuit Partitioning

15. Mr. Steve Tsz-Wai Lai (2001 – 03) Thesis Title: Efficient Approaches in Interconnect-Driven Floorplanning Award: Best Master Paper Award in the ACM (Hong Kong) Postgraduate Research Day 2003

16. Mr. Keith Wai-Chiu Wong (2000 – 02) Thesis Title: Routability Optimization with Buffer Planning in Floorplan Design Award: Best Paper Award Nomination from the IEEE Asian South Pacific Design

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Automation Conference 2003

17. Mr. Bruce Chiu-Wing Sham (2000 – 02) Thesis Title: Interconnect-Driven Floorplanning

18. Miss Wing-Seung Yuen (1999 – 2001) Thesis Title: Scalability and Interconnection Issues in Floorplan Design and Floorplan

4.3 Awards in Teaching

1. VC’s Exemplary Teaching Award from the Chinese University of Hong Kong

2001-02.

2. Faculty Exemplary Teaching Awards from the Chinese University of Hong Kong

2001-02 and 2004-05.

3. Department’s Exemplary Teaching Awards from the Chinese University of Hong

Kong 2000-01 and 2001-02.

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5. Service This section lists my service to the department, the Faculty, the Shaw College, the University and my external service.

5.1 Service to Department

1. Graduate Panel Committee Member 2002 – 11

2. Curriculum Committee Member 2009 – 10

3. Admission Committee Member 2001 - 06

4. Staff Selection Committee 2005 - 06

5. Chairman, Departmental Newsletter Committee 1999 - 05

6. Staff-Student Consultative Committee Member 1999 - 05

7. Alumni Matters Committee Member 1999 - 05

8. Time-Tabling Committee Member 2000 - 05

9. Program Promotion and Student Recruitment Committee Member 2000 - 05

10. Department Handbook and CD Committee Member 2001 - 05

11. Student Academic Contest (ACM Programming Contest) 2003 - 05

12. Admission Coordinator 2004 - 05

13. Student Recruitment Committee Member 1999 - 00

5.2 Service to Faculty

1. Engineering Faculty Board 2007 – 09

2. Summer Engineering Academy 2007

3. Orientation Camp Faculty Advisor 2002 – 03

4. Alumni Forum Committee Member 2002 – 03

5.3 Service to University/College

1. Shaw College Alumni Affairs Committee 2004 – 11

2. Shaw General Education Committee 2009 – 11

3. Dean Search Committee 2008 – 09

4. Shaw College Scholarship, Award and Financial Assistance Committee 2008 – 09

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5. Teaching General Education Course 2001 - 08

6. Departmental College Coordinator 2001 – 02, 2007 – 08

7. Shaw College Mentorship Programme Committee 2004 – 06

5.4 External Service

1. Organizing Committee of ACM (Hong Kong) Collegiate Programming Contest,

2002, 2003, 2005, 2007

2. Advisor, Hong Kong YWCA 2005 - 06

3. Head Judge, ACM (HK) Collegiate Programming Contest 2005

4. Vice-chairman of ACM (Hong Kong) 2002 – 04

5. Moderator, Hong Kong A-Level Examination 2000 - 03

6. Adjudicator, Joint School Science Exhibition 2001 - 03

7. Chairman, ACM (HK) Collegiate Programming Contest 2002

8. Secretary of ACM (Hong Kong) 2001 – 02

5.5 Awards in Service Departmental Exemplary Service Award 2008 - 09

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