EUV Mask Challenges, Status, and Closing the Remaining...

Accelerating the next technology revolution

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SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center

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EUV Mask Challenges, Status, and

Closing the Remaining Technology

Gaps

Frank Goodwin, Vibhu Jindal, Patrick Kearney,

Ranganath Teki, Jenah Harris-Jones, Andy Ma,

Arun John Kadaksham, Stefan Wurm

SEMATECH

SEMATECH Champion Data

• Achieved 12 defects @ 45 nm or 8 defects @ 50 nm from M7360 inspection – 10 pits (from substrate), 1 handling defect, 1 defect from deposition

• 65% reduction in defects from last year champion data (23 defects @50nm)

10/4/2012 2

M7360 Dense Scan M1350

IEUVI Mask TWG; 2012 EUVL Symposium; Brussels

Yield analysis with M1350 (>70nm) and

M7360 (>45 nm)

• Quality blanks: ~70% of yield below 30 defects >70nm from M1350 – 60% of Quality blanks have less than 30 defects >45 nm from

M7360

– 20% of Quality blanks have less than 20 >45 nm from M7360

10/4/2012 3 IEUVI Mask TWG; 2012 EUVL Symposium; Brussels

Improvement made in Blank Defectivity

11 defects 14 defects 12 defects

@5

0 n

m+

@

50

nm

+

@7

0 n

m+

10/4/2012 IEUVI Mask TWG; 2012 EUVL Symposium; Brussels 4

Mask Blank Defect Density Trend

• 2015 – Overall defect counts should meet requirements

– Large size “Killer” defects still present and remain a concern for mask yield

• HVM – Significant challenges remain to meet logic requirements

• Process yields are not good

5 10/4/2012

0.001

0.010

0.100

1.000

10.000

100.000

10/06/03 02/17/05 07/02/06 11/14/07 03/28/09 08/10/10 12/23/11

De

fect

De

nsi

ty /

Pro

cess

Ru

n

Date of Process Run

Mask Blank Defect Density Trend (@73nm SiO2 equiv.)

2015 Memory

2015 Logic

Memory HVM

Logic HVM

Defect requirements of device manufactures have changed


Multilayer (ML) blank defectivity

• Most significant gains made in reduction of defects have been with the substrate – Cleaning induced defects

– Substrate quality improvement at suppliers

Deposition defects

dominate

Substrate defects

dominate

> ~70 nm >

6 10/4/2012 IEUVI Mask TWG; 2012 EUVL Symposium; Brussels

Substrate challenges

• Approximately 60%-65% of total mask blank defects originate from substrate defects

• Meeting simultaneously: substrate finish, figure (flatness), roughness and defect specifications is still a significant challenge – Substrates are amorphous in nature, making it difficult to control

CMP

• Reaching figure and finish specifications requires several iterations between global and local polish – This creates defects such as scratches or embedded particles

• The surface physical and chemical properties are modified by the polish steps and do interact with the cleaning processes – Tight management and control between final polish and cleans to

ensure cleaning does not introduce additional defects

10/4/2012 7 IEUVI Mask TWG; 2012 EUVL Symposium; Brussels

EUV Substrate Gaps

• Defect levels, roughness and flatness specifications must be met for successful EUVL implementation

EUVL Substrate Requirements

@22 nm HP node

Specification Source Current Status

Defect size 30 nm ITRS 2011 Update

0 defects @ 40 nm+

Defect density 0.003 def/cm2 SEMI standards,

2009 update

0 defects @ 40 nm+

Roughness 0.046 nm P. Naulleau, LBNL

~0.05 nm

Flatness 26 nm PV ITRS 2011 Update

80-100 nm typical

Local Slope 1.8 microradians

ITRS 2011 Update

No issues

Defects

Roughness

Flatness

0.003 def/cm2

0.046 nm 26 nm


Veeco Nexus Low Defect Deposition Ion-

Beam Deposition Tool

• Ion Beam Deposition (IBD) – The leading technology

demonstrating the potential to achieve defect free mask blanks

• Configuration of current tool – Source, target, and substrate

locations identical to 1995 Lawrence Livermore design

– Ion source: Veeco RIM-210 producing a focused ion beam

– 4 Target Turret

– Removable stainless shields

– Rectangular chamber design select by tool manufacturer


Scattered ions

Scattered ions

Overspray of Ion Source

• Divergence of the ion beam result in high energy ions hitting shields – Sputtering of shields

10/4/2012 10

Net etch

Ideal Ion Beam Profile Real Ion Beam Profile

Ions hitting shields

Etching of door shield

Ions hitting substrate


Optimized Ion Beam Profile For Defect

Reduction

• Higher operating voltages/currents can give narrower focus on target

• New parameters give < ¼ % of peak etch at edge of target – Does not completely eliminate sputtering of shields

Initial source parameters Optimized source parameters

Outer pink contour is ~¼ % of peak etch rate


Tool and Process Limitations

• Limitations of deposition chamber and process – Overspray of ion source

– Substrate Handling

– Process yield, significant number of deposition cycles required to reach quality deposition region

– Small process window for reflectance uniformity

– Shield surfaces

– Proximity of substrate to shields

• New Deposition Tool is Required – Cleaner, less divergent ion source

– Chamber with a larger volume

– New substrate location •May require flexibility to move substrate to multiple positions

– Cleaner handling of substrates and mask blanks •May require dual pod solution


Mask Blank ML Deposition Challenges

• Approximately 20%-25% of total mask blank defects come are deposition related

• Mask blank defectivity requirements have not yet been demonstrated – Large “killer” defects are a significant problem

• Prohibits implementation of defect mitigation schemes

• Comes from deposition tool and process

• Detected on each mask blank SEMATECH has measured

– Defect counts are close to meeting memory and pilot line logic requirements

• Requres ~4X improvement to meet logic HVM specifications

• Deposition process yield – Quality deposition region is only 10%, at best, of overall process

run

– Target surfacing and burn-in critical


EUV Mask Blank Gaps

• Defect levels, roughness, and reflectivity

EUVL Mask Blank Requirements @22 nm HP

node

Specification Source Current Status

Defect size 18 nm ITRS 2011 Update 12 defects @ 45 nm+

Defect density 0.002 defects/cm2 Device Manufactures 0.043 defects/cm2

Roughness (rms) 0.05 nm Defect Metrology ~0.14 nm

Reflectivity 65% ITRS 2011 Update 63%-64%


Limitations of current Mo/Si multilayers

• Thick silicide layer on silicon layer (B) reduces reflectivity

• Molybdenum crystallites in ML increases roughness – Increase LER in wafer images

– Negatively impacts defect inspection

– Maintains reflectivity as the crystallites inhibit silicide formation at Mo to Si interface (D)

Investigating interface engineering and eliminating Mo crystallite formation

Amorphous silicon layer Thick silicide layer on silicon Polycrystalline molybdenum layer Thin silicide layer on molybdenum

A B C D

Mo/Si ML microstructure


Reducing Molybdenum Crystallites

• First attempt with 1nm thick film in Mo layer – Successfully inhibited Mo grain

growth

– Lower AFM roughness than standard ML

– Sample is at AIT for speckle measurement

• EUV reflectivity dropped – Showed unacceptable

reflectivity loss of 2.9% for > 0.5nm thickness

– Reflectivity recovered for 0.5nm

• Waiting on confirmation of crystallite growth suppression

Mo crystallites No Mo crystallites


Mo/Si Interface Engineering for Reflectivity

Improvement • Demonstrated 1.2% improvement in

overall reflectivity – 66.6% with no Mo crystallite

suppression

– 63.7% with Mo crystallite the suppression process

• Integrated process has demonstrated: – Reduction of mask blank roughness by

suppressing molybdenum crystallite formation

• Should help with speckle/LER and defect inspection.

– Reflectivity is recoverable through Mo/Si interface engineering

• Currently waiting on additional measurements – Impact on speckle


Mask Blank Roadmap


Defect Detection with Non-Actinic Tool • Invisible with SEM and optical review

• But printed on wafer and detect with AIT inspection

• Pit phase defect: 86 nm SiO2 size on M1350

SEM Image AIT Image MET Image

• Bump phase defect: 98 nm SiO2 size on M1350

SEM Image AIT Image MET Image 10/4/2012 IEUVI Mask TWG; 2012 EUVL Symposium; Brussels 19

High Level Requirements for Actinic Blank

Inspection

• Inspection requirements:

– Substrate pits/bumps (phase defects) must be detected

– Particles, even just under the capping or top multilayers

(amplitude defects) must also be detected

• Classification and review requirements:

– Review should accurately localize the defects so

mitigation by pattern shifting can be used.

– Defects should be classified, and near the sensitivity

limit, reviewed to determine printability


Defect Trends of Suppliers

• Defect trends of mask

blank suppliers are

improving

• However, delivered mask

blanks will have some

defects

• Defect printing mitigation

methods will be needed

AGC: from 2011 EUV Symposium

HOYA: from 2011 SPIE Adv Litho


Mask Layout Pattern Shift

• Position design layout so that all mask blank defects remain covered by the absorber

• Remaining questions: – Probability of eliminating all blank defects using pattern shift

– Potential impact on field size

– Allowed defect count and size distribution

• Successful pattern shift requires: – Excellent coordinate accuracy

– Low-defect fiducial process

– Infrastructure for sorting blanks and matching to mask patterning

– All printing defects need to be detectable


Current EUV Mask Technical Gaps

• Challenges with defects continue: – Substrate Defects

•Defects become visible after deposition

– Multi-Layer Deposition •Killer defects from ML deposition still an issue

•Low process yield

– Defect free EUV masks •Mitigation of mask blank defects will be required

– Metrology •What inspection capability existing is running out of steam

• Inspection tools required to meet HVM requirement are not available

• Infrastructure – New generation of ML deposition tool is needed

– Metrology and inspection tool development required


Closing the Gaps

• Mask blank suppliers maintaining their current roadmaps

• Consortia and Mask Blank Suppliers continue to work on EUV development – Substrate polishing and cleaning

– ML Deposition Tool and Process

• Consortia and Tool Suppliers are addressing tool gaps – Inspection tools

• Mask Blank (substrate?)

• Pattern Mask

– Deposition • Next generation IBD tool

• Pre-production exposure tools – Increasing mask manufacturing cycles of learning

– Driving focus on process yield across all areas of mask manufacturing

• Lack of metrology tools demands wafer print for process and defect verification which is slowing learning

• Increased focus by industry on addressing HVM needs


Thank You


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EUV Mask Challenges, Status, and Closing the Remaining...

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