EuCARD-BOO-2010-004.pdf

EuCARD-BOO-2010-004

European Coordination for Accelerator Research and Development

PUBLICATION

Front-end Electronics for MultichannelSemiconductor Detector Systems;

EuCARD Editorial Series on AcceleratorScience and Technology, Vol.08

Grybos, P (AGH-UST, Krakow, Poland)

17 August 2012

The research leading to these results has received funding from the European Commissionunder the FP7 Research Infrastructures project EuCARD, grant agreement no. 227579.

This work is part of EuCARDWork Package 4: AccNet: Accelerator Science Networks.

The electronic version of this EuCARD Publication is available via the EuCARD web site or on the CERN Document Server at the following URL :

Pawe Grybo

Front-end Electronicsfor Multichannel

SemiconductorDetector Systems

Institute of Electronic SystemsWarsaw University of Technology Warsaw 2010

Editorial Series on ACCELERATOR SCIENCE

Kazimierz KorbelAndrzej Napieralski

the part of 64-channel DEDIX integrated circuit (photo courtesy of Luciano Ramello)

Front-end electronics for multichannel semiconductor detector systems i

CONTENTS

Acknowledgements ...................................................................................................................... iii List of symbols .............................................................................................................................. iv Abbreviations and acnonyms used in the text..............................................................................viii 1. Introduction ................................................................................................................................1 2. Semiconductor detectors.............................................................................................................5

2.1. Materials for semiconductor detectors ............................................................................6 2.2. Reverse bias p-n junction ................................................................................................8 2.3. Charge generation in detector........................................................................................13 2.4. Charge transport ............................................................................................................15 2.5. Ramo theory and signal formation ................................................................................19 2.6. Detector geometry .........................................................................................................21 2.7. Important detector parameters.......................................................................................23

3. Architecture of front-end electronics ........................................................................................27

3.1. Types of amplifiers........................................................................................................29 3.2. Charge sensitive amplifier.............................................................................................31

3.2.1. Ideal charge sensitive amplifier .........................................................................31 3.2.2. Realistic charge sensitive amplifier ...................................................................33 3.2.3. Examples of core amplifier architectures...........................................................37 3.2.4. Feedback configuration......................................................................................40 3.2.5. Test injection circuit ..........................................................................................42

3.3. Shaper............................................................................................................................43 3.3.1. Signal shaping....................................................................................................44 3.3.2. Noise analysis ....................................................................................................56

3.4. Noise optimization of CSA input transistor ..................................................................62 3.4.1. Strong inversion region......................................................................................63 3.4.2. Moderate and weak inversion regions ...............................................................66

3.5. Aspect of fast signal processing ....................................................................................70 3.5.1. Pulse pile-ups at CSA output .............................................................................71 3.5.2. Pole-zero cancellation circuit.............................................................................72 3.5.3. Base line restorer ...............................................................................................75

3.6. Further signal processing...............................................................................................80 3.6.1. Discriminators....................................................................................................83 3.6.2. Peak Detector Derandomizer .............................................................................86

4. Important aspect of multichannel low noise mixed-mode integrated circuits..........................89

4.1. Noise modeling in MOS transistors ..............................................................................91 4.1.1. Channel thermal noise........................................................................................91 4.1.2. Flicker noise.......................................................................................................94 4.1.3. Short channel effects..........................................................................................96

Front-end electronics for multichannel semiconductor detector systems ii

4.2. Cross-talk in mixed mode circuits.................................................................................98 4.2.1. Generation, transmission and reception of switching noise ...............................98 4.2.2. Reducing the noise generation .........................................................................102 4.2.3. Increasing the immunity of analog part ...........................................................103 4.2.4. Isolation techniques .........................................................................................103 4.2.5. Summary of crosstalk reduction techniques ....................................................106

4.3. Random matching and offsets .....................................................................................107 4.3.1. Mismatch parameters of MOS transistors........................................................109 4.3.2. Transistor matching in various processes ........................................................112 4.3.3. Current matching in MOS transistors ..............................................................114 4.3.4. Random matching in circuits ...........................................................................115 4.3.5. Layout rules for good matching .......................................................................116 4.3.6. Matching on multichip modules ......................................................................118 4.3.7. Mismatch simulation using Monte Carlo analysis ...........................................119

5. Radiation damage in silicon detectors and readout electronics...............................................121

5.1. Total dose effects ........................................................................................................122 5.1.1. Displacement damage ......................................................................................122 5.1.2. Ionization effects..............................................................................................123

5.2. Single event effects .....................................................................................................127 5.3. Radiation tolerant design of readout electronics .........................................................128

6. Examples of multichannel counting IC for X-ray applications...............................................131

6.1. Requirements for multichannel counting systems.......................................................132 6.2. ASIC for strip detectors...............................................................................................135 6.3. Solutions for pad detectors and small array of pixel detectors ....................................141 6.4. Solutions for pixel detectors........................................................................................148

7. References ..............................................................................................................................173

Front-end electronics for multichannel semiconductor detector systems iii Acknowledgements

This monograph is the result of countless interactions with many people who de-voted their precious time and effort trying to teach me electronics. At various occasions I have met them at universities, research institutes, conferences, meetings, or just on the web. I would like to thank them all for their open mind, patience and cordial assistance. I have also benefited from suggestions made by my reviewers: Prof. Kazimierz Korbel and Prof. Andrzej Napieralski.

I wish to extend my appreciation to Robert Szczygie for proof-reading and Mar-cin Grybo for his help with drawing figures. I am also grateful to Janusz Ole and Bo-ena Bryzek-Ole for linguistic corrections. Finally, I would like to thank my wife Joanna and family for their continuous support.

The part of the work presented in this monograph was supported by the Ministry of Science and Higher Education, Poland, Projects no. N515 262 235 in the years 20082010 and Project no. N515 243 037 in the years 20092011.

Pawe Grybo

iv Front-end electronics for multichannel semiconductor detector systems

LIST OF SYMBOLS

A fitting parameter AF SPICE exponent constant for flicker noise A area proportionality constant of variation of current factor ACox area proportionality constant of variation of gate oxide capacitance A area proportionality constant of variation of body factor Ai real part of pole AL proportionality constant of variation of channel length A area proportionality constant of variation of mobility AP area proportionality constant of variation of parameter P AW proportionality constant of variation of channel width AVT0 area proportionality constant of variation of threshold voltage a constant exponent constant of flicker noise N fitting parameter b constant current factor in MOS transistor n, p beta of transistor npn, beta of transistor pnp C capacitance Cb capacitance to the backplane Cbu capacitance to the backplane per unit strip length C , CVT0 matching parameters Cc coupling capacitance Cdet detector capacitance CF feedback capacitance Cgs gate-source capacitance Cgd gate-drain capacitance Cin input amplifier capacitance Cn capacitance to the neighbour strip (interstrip capacitance) Cnu capacitance to the neighbour strip per unit strip length Cox oxide capacitance per unit area Cov overlap gate-diffusion capacitance per channel width Cpar parasitic capacitance of connection detector - CSA CT sum of capacitances Cdet, C1 and Cpar Ctest test capacitor C1 input transistor capacitance D spacing distance De,Dh diffusion coefficient for electrons, holes DI threshold adjust implant dose d detector thickness E, Emax, Emin electric field, maximum electric field, minimum electric field Eg energy bandgap Eph photon energy Ew weighting field ENC equivalent noise charge ENCf ENC contribution from flicker voltage noise ENCi ENC contribution from current noise ENCw ENC contribution from thermal voltage noise Si silicon permittivity ox oxide permittivity

Front-end electronics for semiconductor detector systems v F Fano factor F() amplitude characteristics Fv,Fvf, Fi filter constants for ENCw, ENCf, ENCi f frequency fin average frequency of input pulses fD duty factor of input pulses f0 noise count rate at zero threshold level fnoiMod switch for flicker noise model in BSIM4 F Fermi potential MS gate-semiconductor work function difference T thermal voltage T=kT/q GBW gain bandwidth product GDSNIO channel thermal noise coefficient in HSPICE gds source-drain conductance gm gate transconductance gmb body transconductance H0 constant H(s) filter transfer function body factor n thermal noise factor changing from weak to strong inversion IBEAM, IBEAM0 beam intensity, primary beam intensity ID0 process dependent parameter for subthreshold current IDB drain-bulk current Idet detector leakage current IDS drain-source current iD detector current pulse ik current induced at k electrode if normalized forward current inoW ratio of if /W

dfdi2 power spectral density of current noise

j imaginary unit J current density JR, JRg reverse current density, reverse generation current density k Boltzman constant K constant Kf flicker noise constant Kfn , Kfp flicker noise constants of NMOS and PMOS transistors KF SPICE flicker noise constant Kv voltage gain K0 DC gain L channel length Leff effective channel length Lind inductance Lmin minimum channel length channel length modulation parameter m fitting parameter mobility att attenuation coefficient e , h mobility of electrons, holes eff effective mobility

vi Front-end electronics for multichannel semiconductor detector systems

after mobility after irradiation NA acceptor doping density Na channel dopant density ND donor doping density Neh number of electron-hole pairs Nit number of interface traps Not number of oxide traps NLEV switch for noise model parameter in HSPICE NOIA, NOIB, NOIC parameters for flicker noise in BSIM4 NTNOI parameter for more accurate fitting of thermal noise in BSIM4 n, nG number (i.e. filter order) ni intrinsic carrier concentration ns subthreshold slope factor npo electron concentration in p-type semiconductor in thermal equilibrium P parameter p p = s p0 real pole in Ohkawa method p0=A0 pi complex poles in Okhawa method (i =1,2.3 ..) and pi = Ai Wi pno hole concentration in n-type semiconductor in thermal equilibrium n resistivity of n-type silicon q elementary charge Q charge Q(s) polynomial Qc charge associated with the depletion region Qin input charge Qinv total inversion channel charge Qox fixed oxide charge density Qtot total charge Qtest injected charge via test capacitor Ctest R resistance Rbias detector bias resistance RDS bias dependent drain-source resistance in BSIM4 model Rin input amplifier resistance Rpz effective resistance in PZC circuit Rsu effective resistance of strip per unit strip length Rf effective CSA feedback resistance rds small signal drain-source resistance r spread of charge carriers with respect to trajectory without diffusion S variation of the current factor with a distance S variation of the body factor with a distance SP variation of the parameter P with a distance SVT0 variation of the threshold voltage with a distance s s = j si pole conductivity or rms deviation of normal distribution n voltage noise rms photo photoabsorption cross section T absolute temperature Tepi epi-layer thickness t time timp charge collection time at detector electrode

Front-end electronics for semiconductor detector systems vii te, th collection time for electron, holes temax, thmax maximum collection time for electron, holes tox oxide thickness tm width of the pulse at the fraction m of its peak height, where m is speci-

fied as 0.1, 0.01 etc. tp pulse peaking time, measured from 1% of the peak height to the centre

of the peak tp1 bipolar pulse peaking time, measured from 1% of the peak height to the

center of its peak tp2 bipolar pulse peaking time, measured from 1% of the peak height of the

primary lobe to the peak of the undershoot txo crossover time of a bipolar pulse tnoiMod switch for thermal noise model in BSIM4 time constant e , h carrier lifetime for electrons, carrier lifetime for holes g carrier generation lifetime f, HP, LP, 1, 2,in time constants u, ue, uh charge velocity, electron velocity, hole velocity W channel width Wdep width of depletion region Wi imaginary part of pole WSIopt optimum transistor width for minimum ENCw - strong inversion case WSI optimum transistor width for minimum ENCw angular frequency 0, 1, 2 poles of transfer function V potential Vbi built-in potential Vdep depletion voltage VDS drain-source voltage VDSsat drain-source saturation voltage VGS gate-source voltage Vosr random offset VR reverse bias voltage Vref reference voltage VT threshold voltage VT0 threshold voltage for VSB = 0 VTH comparator threshold voltage Vtest voltage step applied to test capacitor Ctest VSB source-bulk voltage

dfdv2 power spectral density of voltage noise

vin input voltage signal vout output voltage signal ydep average channel thickness Z atomic number Zin input impedance

viii Front-end electronics for multichannel semiconductor detector systems

ABBERIVATIONS AND ACRONYMS USED IN THE TEXT

ADC Analog-to-Digital Converter AGH UST AGH University of Science and Technology AMS austriamicrosystems ASIC Application Specific Integrated Circuit ATLAS A Toroidal Lhc ApparaturS BLH Base Line Holder BLR Base Line Restorer BNL Brookhaven National Laboratory BSIM Berkeley Short-channel IGFET Model CASTOR Counting and Amplifying SysTem fOr Radiation detection IC CCD Charge Coupled Devices CERN European Organization for Nuclear Research CIX Counting and Integrating X-ray IC CMOS Complementary Metal Oxide Semiconductor CMS Compact Muon Solenoid CPPM Centre de Physique des Particules de Marseille CSA Charge Sensitive Amplifier DAC Digital-to-Analog Converter DEDIX Dual Energy Digital Imaging of X-ray IC DDR Double Data Rate DPAD Digital Pixel Array Detector DxCTA chip name EKV mathematical model of MOSFET developed by C.C. Enc, F. Krummenacher and A. E. Vittoz e-h electron-hole ELT Enclosed Layout Transistor ENC Equivalent Noise Charge FEOL Front-End-Of Line FNAL Fermi National Accelerator Laboratory HEP High Energy Physics IC Integrated Circuit LDD Light Doped Drain LET Linear Energy Transfer LHC Large Hadron Collider IGFET Isolation Gate Field Effect Transistor LVDS Low Voltage Differential Signaling MBU Multiple Bit Upsets MEDIPIX Medical Pixel Chip MIP Minimum Ionizing Particle MOS Metal Oxide Semiconductor MOSFET MOS Field Effect Transistor MPEC Multi Picture Element Counters IC MPW Multi-Project-Wafer run NIEL NonIonizing Energy Loss NMOS N-channel MOSFET OTA Operational Transconductance Amplifier PD Peak Detector PILATUS PIxeL ApparaTUs for the SLS

Front-end electronics for semiconductor detector systems ix PIXSCAN small animal X-ray CT-scaner PMOS P-channel MOSFET PSD Position Sensitive Detector PSI Paul Scherrer Institute PX90 Pixel Xray readout 90 nm IC PZC Pole-Zero Cancellation RAM Random Access Memory RELAXD high REsolution Large Area X-ray Detectors sd standard derivation SEBO Single Event Burt-Out SEE Single Event Effect SEFI Single Event Function Interrupt SEGR Single Event Gate Rupture SEL Single Event Latchup SES Single Event Snapback SET Single Event Transient SEU Single Event Upset SHE Single Hard Error SLS Swiss Light Source SOI Silicon In Isolator SPECTRE simulation program for circuit analysis SPICE Simulation Program with IC Emphasis SRAM Static Random Access Memory SSD Silicon Strip Detector STM STMicroelectronics TIMEPIX chip developed at CERN ToT Time-over-Threshold TSMC Taiwan Semiconductor Manufacturing Company TSV Through Silicon Vias VIPIC Vertically Integrated Pixel Imaging Chip VLSI Very Large Scale Integration XPAD Xray Pixel Advanced Detector XPCS X-ray Photon Correlation Spectroscopy

Introduction 1

1. INTRODUCTION

The history of semiconductor detectors started in 1951 when K. McKay noticed

that the german diode could be used for detection of particles [1]. A reversely biased diode proved to be the best solution for particle and radiation detection. The sixties and seventies saw the development of both semiconductor detectors and readout electronics, optimized mainly for spectroscopy applications. In those times, a classical detector sys-tem consisted of a single detector and a single readout channel. The theory connected with a signal shaping, a noise optimization, pile-up effects in the front-end electronics were being intensely developed then [2].

Another important step was the use of the planar process by J. Kemmer [3] to pro-duce a strip detector. Since then semiconductor detectors with many electrodes and with the pitch typically in the range from 50 m to 200 m have been used as position sensi-tive devices. Fast development of the VLSI technology has allowed designing mul-tichannel integrated readout electronics for these detectors according to the rule stating

2 Introduction

that each detector electrode is readout by an independent electronic channel. Such posi-tion sensitive semiconductor systems have been used for many years in High Energy Physics (HEP) experiments, where the number of readout electronic channels comes up to several millions [4,5]. Nowadays, similar systems are used in different X-ray imaging techniques in solid-state physics, material science, medicine, etc. In these applications, the trend is to build the position sensitive detection system, which will provide also in-formation about energy of photons.

For many years, the author has worked on different aspects related to front-end electronics for semiconductor detector systems, namely: designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal proc-essing, crosstalk reduction and good matching performance, optimization of semiconductor detection systems in respect to the effects of radiation damage.

The presented monograph is the result of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure of this book is sche-matically shown in Fig. 1.1.

Fig. 1.1. Book structure.

Introduction 3

The source of the signal is a semiconductor detector, which is described in Chap-

ter 2 together with its equivalent electric model. The theory of the signal shaping and noise optimization is presented in Chapter 3. During the design of multichannel inte-grated circuits for detector systems certain important aspects connected with VLSI tech-nologies must be taken into account, i.e. noise modeling, crosstalk between digital and analog parts of an integrated circuit and the problem of mismatch. These aspects for CMOS bulk technology are discussed in Chapter 4. Because the detector and readout electronics operate in radiation fields they suffer from radiation damages, and a brief description of these effects is given in Chapter 5. The best source of knowledge on how to solve various problems of readout electronics are working multichannel ASICs used in detector systems. Detailed descriptions of them can be found in journals (mainly IEEE TNS, NIM A), conference proceedings, technical reports or PhD theses. The solu-tions for high energy physics are also described in excellent books, like [4,5]. However, the last decade has also brought a dynamic development of applications using strip and pixel semiconductor detectors for different X-ray imaging techniques. The examples of multichannel readout electronics working in single photon counting mode for X-ray imaging applications have been dealt with in Chapter 6.

The author hopes that this monograph will help young designers of VLSI elec-tronics who frequently join scientific laboratories after graduation and work on semi-conductor detectors and readout electronics. Their task is often to design multichannel Application Specific Integrated Circuits (ASIC) for strip or pixel semiconductor detec-tor, and they often raise the question how to design successfully the analog part of mul-tichannel front-end electronics. There are two aspects to be smoothly inter-connected in such a design, namely: theory of signal processing in detector readout electronics which was developed many years ago, VLSI technology, which, despite its obvious advantages has also some relevant limita-tions.

Semiconductor detectors 5

2. SEMICONDUCTOR DETECTORS

Semiconductor Position Sensitive Detectors (PSD) have been successfully used in particle physics experiments for more than two decades. From the wide variety of these detectors, the following are most frequently used: strip/pixel detectors, charge coupled devices (CCD), silicon drift chambers, monolithic active pixels. This chapter focuses on the first group of detectors, which is the most popular for parti-cle physics experiments and also more frequently used in X-ray imaging applications. The strip/pixel detector is an array of individual sensor elements which in response to a single particle/photon produce a short current pulse on a given electrode. The position of this electrode determines the hit position. The further pulse processing in a front-end

6 Semiconductor detectors

electronics can provide not only binary information (YES/NO pulse on a given elec-trode) but also information about energy deposited in the detector or about time event. In particle physics experiments several layers of such detectors allow to reconstruct the particle track. In X-ray imaging techniques these detectors can work in a single photon counting mode providing information about the spatial photon distribution and some-times also about photon energies. An advantage of single photon counting detectors is essentially an infinite dynamic range contrary to the integration-type detectors (like those used in CCD cameras), which usually have problems with a limited dynamic range and a low contrast of an image.

This chapter presents briefly basic physic phenomena in a semiconductor detector together with a process of pulse generation in the detector medium. Different possible geometry (strip, pixel, pad) of these detectors is presented. The detector geometry and the type of material used determine not only spatial resolution of the detector and its efficiency, but also influence its electrical parameters like capacitance or leakage current per single electrode. These parameters can be modeled in an equivalent electric scheme of the sensor and later, easily implemented together with the front-end electronics dur-ing numerical simulation.

2.1. MATERIALS FOR SEMICONDUCTOR DETECTORS

A good material for a solid-state detector should possess the following features: large signal in response to particle/photon deposited energy, which requires

a small energy bandgap of a given material to ensure low average energy for the hole-electron generation,

low atomic number Z and low density in case of tracking application for particle physic experiments (particle energy is measured in the calorimeter system),

high atomic number Z and high density in case of X-ray and -ray spectroscopic and imaging applications; high density leads to a large energy loss per traversed length and higher probability of absorbing all photons in a beam,

high mobility of charge carriers and no trapping effects to collect all the gener-ated charge in a short period of time (important for an operation with high radia-tion intensity),

large carrier lifetime to increase so-called charge collection efficiency, defined as a collected charge on the electrode to a total deposited charge,

low leakage current in room temperature; too small bandgap can result in a sig-nificant thermally generated current,

large and high quality crystal (good homogeneity, low impurity levels, high re-sistivity) to produce a large area detector,


radiation hardness especially in case of new accelerator experiments where ra-diation doses are really high,

stable and matured industrial fabrication and processing with relatively low cost and good availability.

Table 2.1 shows the main parameters of different semiconductor materials and diamond (insulator) often used to produce Position Sensitive Detector (PSD).

Table. 2.1. Important parameters of materials used for detector. Parameter Si Ge GaAs CdTe CdZnTe Diamond# Average Z 14 32 31/33 48/52 48/30/52 6

Energy bandgap [eV] 1.12 0.67 1.43 1.44 1.6 5.48 Density [g/cm3] 2.3 5.3 5.4 6.1 5.8 3.5

Energy for electron-hole pair generation [eV] 3.64 2.96 4.2 4.43 4.6 13.1

Mobility at T =300K [cm2/Vs] - electrons

- holes

1350 480

1900 3900

8000 400

1100 100

1000 100

1800 1200

Carrier lifetime [s] 250 250 0.0010.01 0.12 0.12 0.001 # Diamond is classified as an insulator

For nearly three decades, the silicon has been the most popular material used for semiconductor detectors [3, 6]. A very advanced silicon technology is driven by elec-tronics industry. The silicon material fulfills nearly all of the above points, with the ex-ception of high Z and radiation hardness. Because of low Z =14 and matured stable technology, it is very attractive for a tracking detector in particle physics experiments. These experiments are often performed on high luminosity machines like the Large Hadron Collider (LHC), where the expected radiation doses are very high. For silicon tracker doses up to 10 Mrad of ionizing particles and fluences of 10131014 neutron/cm2 are expected in over ten years of LHC operation [7]. In such conditions both the bulk damages [8, 9] and ionization effects in silicon oxide [10, 11] are observed. The low Z and low silicon density limit its X-ray applications mainly to low energy photons. A standard 300 m thick detector converts nearly all 8 keV X-ray, but only 26.7% of 20 keV X-ray and 2% of 60 keV X-ray. Therefore, many laboratories make an effort to produce detectors more efficient for high X-ray energy, with the use of other semicon-ductor materials [12, 13], such as high purity germanium (Ge) and compound semicon-ductors, like gallium arsenide (GaAs), cadmium telluride (CdTe), cadmium zinc tellu-ride (CdZnTe).

Germanium has smaller bandgap than silicon (0.67eV vs. 1.12eV for Si) and has a very good energy resolution [14]. However, low energy bandgap greatly increases a reverse current and a Ge detector typically is cooled to nitrogen temperature (77 K). Germanium, because of high photoabsorption cross section photo Z 4-5, is more attrac-tive for higher X-ray energies than silicon [15].

Gallium arsenide has been studied as the material for a semiconductor detector for -ray since the early 1960s [12, 13, 16]. Because of its potential radiation hardness,


it is also used in military applications and tested for possible applications in particle physics experiments. GaAs has relatively high mobility. Because of impurities in the order of 1015 cm-3, its carrier lifetime is only 10 ns. Due to trapping effects, it also suf-fers from an incomplete charge collection.

CdTe and CdZnTe have high density and high Z (ZCd = 48, ZTe = 52, ZZn =30). Because of large photon absorption cross section and possibility of operation at room temperature, they are used for X-ray and -ray spectroscopic and also for medical imag-ing applications [17-19]. CdTe and CdZnTe generally suffer from poor hole collection. The hole mobility is very low h 100 cm2/Vs and tends to be much smaller than for electrons e 1000 cm2/Vs. The detectors with CdTe Schottky contacts have lower leakage currents than ohmic devices. However, Schottky detectors have a problem with polarization effects [20]. The technology of CdTe and CdZnTe detectors is still limited to small crystal and the connections with front-end electronics are more difficult than in case of Si detectors.

Diamond, as a material with low Z, is a good candidate for tracking applications in particle physics [21]. It has very good radiation hardness, even for radiation expected at LHC. Diamond is classified as an insulator and in order to create hole-electron pair, an average energy of 13.1 eV is required. Large detector samples have not been achieved yet. Because of very long trapping times, the signal from a diamond detector increases during radiation ("pumping" or "priming" effect [22]).

2.2. REVERSE BIAS P-N JUNCTION

A reversed biased pn junction is a basic element for silicon detector and its pa-rameters influence the detector characteristics. Let us consider an abrupt p+n junction under the reversed bias as shown in Fig. 2.1. The following assumption is made: con-stant doping densities of ND in the n-type side (i.e. ND = 1012 atoms/cm3) and NA in the p-type side (i.e. NA = 1016 atoms/cm3). Even for zero applied bias voltage, there is a re-gion at the junction where the mobile charges (electrons and holes) are removed, leaving fixed acceptor and donor ions. This region is called the depletion region or space charge region. Because of the fixed ions in this area, there is a built-in potential equal to [23, 24]:

2lni

DATbi n

NNV = (2.1)

where T = kT/q 26 mV (at T = 300 K) and ni is the intrinsic carrier concentration in pure silicon (ni 1.451010 cm-3 at T = 300 K). The above numbers of ND and NA give

Semiconductor detectors 9 Vbi 1 V. If we apply reversed bias voltage VR , the total voltage across the junction increases to VR+Vbi. The overall charge neutrality requires that

AD NWNW 21 = (2.2)

where W1 and W2 are the width of the depletion region in p+ an n side of the junction. Because NA >> ND the depletion region extends predominantly into the n-side region and the width of depletion layer Wdep = W1 + W2 W1.

Fig. 2.1. The abrupt p+n junction under the reversed bias condition: a) junction, b) charge density, c) electric field, d) potential.


The potential is described by Poisson's equation

Si

DqNdx

Vd=2

2

for W1 x < 0 (2.3)

Si

AqNdx

Vd=2

2

for 0 < x W2 (2.4)

where q is electron charge and Si is the permittivity of silicon (1.0410-12 F/cm). Inte-gration of the above equations with boundary conditions E = 0 for x =W1 and x =W2 gives

( )Si

D WxqNxE 1)( += for W1 x < 0 (2.5)

( )Si

A WxqNxE 2)( = for 0 < x W2 (2.6)

and the maximum Emax of the electric field is at x = 0

Si

A

Si

D WqNWqNE 21

max == (2.7)

Integration of equations (2.5) and (2.6) gives voltage drops in the p+ side and n side of the junction equal to

Si

DWqNV 22

11 = (2.8)

Si

AWqNV 22

22 = (2.9)

Using the eq. (2.2), (2.8) and (2.9) the total voltage drop across the junction is:


+=+

A

D

Si

DRbi N

NWqNVV 12

21

(2.10) Because for asymmetrical p+n junction (NA >> ND), the above equation can be rewritten as

Si

DRbi

WqNVV 22

1=+ (2.11) The width of a depletion layer Wdep W1 is given as:

( )D

RbiSidep qN

VVW += 2 (2.12) There are two important conclusions from the above equation. The first conclusion is that for the abrupt junction, the width of depletion region is proportional to square root of the applied reversed voltage VR. The second one is that a depletion voltage Vdep, which guarantees the total depletion of the whole detector area (with the thickness d), is lower for a purer detector material (lower ND or higher resistivity silicon). The full de-pletion voltage is given as:

biSi

DdWdepRdep V

dqNVV == = 2|

2

(2.13)

For detector production silicon wafers with resistivity in the range from 5 to 10 kcm are used. The relation between the resistivity n (n-type silicon) and the dopant concen-tration ND is

Den Nq

1= (2.14)

where e is the mobility of electrons (for low electric field e is equal to 1350 cm2/Vs at T = 300 K). Using formulae (2.13) and (2.14) the depletion voltage Vdep can be rewritten


bienSi

dep Vd

V = 22

(2.15)

For example, for the given above resistivity of a detector wafer of 300 m thick (based on n-type material) the depletion voltage Vdep is in the range from about 31 V to 63 V.

The depleted junction volume is free from the mobile charges and forms a capaci-tor. Since there is a voltage-dependent charge QC associated with the depletion region, the junction capacitance can be calculated as

( )( )biR

DSi

dep

Si

Si

depD

depD

R

C

VVNq

WWqNd

WqNddVdQC +==

== 2

2

2

(2.16)

According to the above equation, the capacitance is inversely proportional to square root of the applied reversed voltage VR .

The reversed bias junction has always a dark or leakage current which can be ap-proximated by the sum of diffusion components in the neutral region and the generation current in the depletion region (for pno >> npo and |VR| > 3kT/q) [23]

g

depi

D

i

p

hR

WqnNnDqJ +=

2

(2.17)

where JR is the reversed current per unit area, ni is the intrinsic carrier concentration, g is the carrier generation lifetime, Dh is diffusion coefficient for holes and h is carrier lifetime for holes. In case of semiconductor with small values of ni (like Si), the genera-tion current may dominate [23]. The additional components to the detector leakage cur-rent are surface generation current and avalanche breakdown current at high voltage.

A method to reduce the detector current is to reduce the temperature. Consider the generation current JRg where the temperature dependence is hidden in the intrinsic carrier concentration ni and in the generation lifetime g.The JRg is proportional to [4]

kTE

TJ gRg 2exp2 (2.18)

Semiconductor detectors 13 where Eg is the energy bandgap and k is the Boltzman constant. For silicon (Eg = 1.12 eV) the temperature drop by every 8 K means the generation current reduc-tion by factor of 2. So, in order to reduce the detector leakage current and noise associ-ated with it, the detector is often cooled.

2.3. CHARGE GENERATION IN DETECTOR

An interaction of a charge particle or electromagnetic radiation with sensor mate-rial is a basis for their detection. The mechanism of this interaction is different, depend-ing on particle or photon energy.

Electromagnetic radiation interacts with the detector material via several main processes, depending on photon energies, namely: photoelectric effect, coherent scatter-ing, incoherent scattering and pair production. During the photoelectric effect or pair production, the photon is absorbed in the sensor material, while it is scattered and changes its direction in Compton effect. The photon beam going through the sensor does not change its energy but is attenuated according to the absorption law [25]

( )xIxI attBEAMBEAM = exp)( 0 (2.19)

where IBEAM0 is the primary beam intensity and IBEAM(x) is beam intensity after crossing the detector medium in x distance and att is an attenuation coefficient. The photon cross section vs. energy in silicon is shown in Fig. 2.2.

Fig. 2.2. The photon cross section vs. energy in silicon.


The average number of e-h pairs produced by a single photon of energy Eph ab-sorbed in a semiconductor detector is given as

eh

ph

EE

N = (2.20)

where Eeh is energy needed for ionization (energy required to create an e-h pair). In sili-con Eeh = 3.6 eV and it is different from band gap energy Eg = 1.12 eV because an exci-tation of an electron to a conduction band requires a simultaneous transfer of both en-ergy and momentum. In silicon the minimum of the conduction band and the maximum of the valence band have a wave vector offset and during the excitation the momentum is transferred to lattice vibration [4]. For example, the X-ray photon of 8 keV (absorbed in Si by photoelectric effect) produces about 2200 e-h pairs and the charge deposition is located nearly in a single point (see Fig. 2.3(a)). The number of produced pairs is also subject to statistical fluctuation described by Fano factor F according to [26]

eheh FNN = 2 (2.21)

The Fano factor is a function of temperature and for Si the measured F value is between 0.07 and 0.16 [2729].

(a) (b)

Fig. 2.3. Generation of a hole-electron pair in silicon strip detector for: a) low energy X-ray - charge is generated nearly in a single point, b) minimum ionization particle - charge is generated along particle

track.

A high energy charge particle (like in high energy physics experiments) traverses the sensor and deposits there a part of its energy. The energy is deposited by many scat-tering processes with electrons of sensor material and the energy deposition is described by "long" Bethe-Bloch formula [30]. Along the particle trajectory hole-electron pairs are

Semiconductor detectors 15 produced (see Fig. 2.3(b)). A minimum ionizing particle produces about 77 e-h pairs per m path length in Si, which means about 23000 e-h pairs for the popular 300 m thick silicon detector. This is only the most probable value of generated charge because the process of energy deposition for minimum ionizing particles is subject to statistical fluc-tuation described usually by Landau-Vaviliov distribution (or Bichsel distribution - see Fig. 2.4). These distributions show a long tail, so there is a significant probability of higher energy deposition and more generated charge.

Fig. 2.4. A comparison of noiseless Bichsel and Vavilov distributions for a single 300 m long track

segment (reprinted from [31] 1995, with permission from Elsevier, http://www.sciencedirect.com/science/journal/ ).

2.4. CHARGE TRANSPORT

There are two mechanisms of charge carrier transport drift and diffusion. In the presence of an external field the charge moves parallel to the electric field and it is ac-celerated between random collisions with the lattice. The average carrier drift velocity is given by

Eu eer= (2.22)

Eu hhr= (2.23)

In silicon at low field (up to about 104 V/cm) the mobility is constant. At 300 K

the mobility is 1350 cm2/Vs for electrons and 480 cm2/Vs for holes. For high electric field (E > 105V/cm) the carrier drift velocity saturates at the level of 107 cm/s. The holes and electrons move in opposite directions and the time required for carriers to traverse


the detector volume is called collection time. Collection time depends on a charge gen-eration point, detector thickness and the applied electric field.

The electric field in reversed biased p+n diode depends on the applied VR voltage. Fig. 2.5 shows only the n-side of the diode for three different cases: partial depletion voltage, full depletion voltage and overdepleted voltage. Compared to Fig. 2.1 the x-axis is shifted of detector thickness to simplify the further calculations.

(a)

(b)

(c)

Fig. 2.5. Electric field in a reversed biased diode (only n-side is shown) for different values of applied voltages VR : a) VR < Vdep , b) VR = Vdep , c) VR > Vdep .

To shorten collection time the overdepleted case with VR > Vdep is mostly used. In

that case the field distribution can be written as

min)( ExqNxE

Si

D += (2.24)

where

dVV

E depRmin (2.25)

Let us consider a pair of carriers (electron and hole) generated at point x0 (see

Fig. 2.5(c)). The motion equations are the following [32]

+= minExqNdt

dxSi

Dh for hole (2.26)

+= minExqNdt

dxSi

De for electron (2.27)

Semiconductor detectors 17 Integrating the above equations with the initial condition x = x0 at t = 0 one obtains for hole 0 t th

++= tNqE

qNxE

qNx

Si

Dh

D

Si

D

Sih

expmin0min (2.28)

and for electron 0 t te

++= tNqE

qNxE

qNx

Si

De

D

Si

D

Sie

expmin0min (2.29)

The velocities uh = dxh/dt and ue = dxe/dt as a function of time are

+= tNqxqNEu

Si

Dh

Si

Dhh

exp0min (2.30)

+= tNqxqNEu

Si

De

Si

Dee

exp0min (2.31)

The collection times th and te can be calculated directly from (2.28) and (2.29)

( )( ) min0

min

//ln

EqNxEqNd

qNt

DSi

DSi

Dh

Sih

++= (2.32)

( )

( ) minmin0

//ln

EqNEqNx

qNt

DSi

DSi

De

Sie

+= (2.32)

For holes the collection time is the longest if x0 = 0 and then

( )( ) min

minmax /

/lnEqN

EqNdqN

tDSi

DSi

Dh

Sih

+= (2.33)


For electrons the collection time is the longest if x0 = d and then

( )( ) min

minmax /

/lnEqN

EqNdqN

tDSi

DSi

De

Sie

+= (2.34)

The examples of the maximum charge collection time (assuming that charge cross the whole detector thickness) for different bias voltages of the detector are calculated in Table 2.2. For the calculation it is assumed that the silicon resistivity is 10 kcm (Vdep = 31 V) and the detector thickness is d = 300 m.

Table. 2.2. Examples of the maximum collection times in Si detector with Vdep = 31 V and d = 300 m calculated according to equations (2.33) and (2.34).

Applied voltage VR [V] temax for electrons [ns] thmax for holes [ns] 45 17.9 50.2 60 12.1 34.1 90 7.6 21.5

120 5.6 15.9 180 3.7 10.5

The long collection time can influence the energy resolution of the position sensi-

tive detector because of a diffusion process. In case of gradient concentration, the ran-dom movement of the charge carries is more probable in the direction of lower concen-tration. So, the cloud of charge carriers spreads out with respect to the trajectory without diffusion. The average square deviation 2r during the time interval t is [32]

tDr he,2 2= (2.35)

where De is a diffusion coefficient for electrons and Dh is a diffusion coefficient for holes. In position sensitive detector, like a strip or a pixel detector, the diffusing cloud of charge carriers can be divided between neighboring detector electrodes. This effect is called charge sharing or charge division and in case of a small pitch between detector electrodes it deteriorates the detector energy resolution [33, 34]. The relationship be-tween diffusion coefficient and mobility is the following [23]

hehe qkTD ,,

= (2.36)

Semiconductor detectors 19 In silicon the diffusion coefficients are De 35 cm2/s (3.5 m2/ns) for electrons and Dh 12 cm2/s (1.2 m2/ns) for hole. The spread of thermal diffusion is larger for longer time collections, so for this reason, in position sensitive detectors the collection time should be minimized.

The second important case where collection time plays an important role, is the case of using very fast readout electronics. The shaping time in the readout electronics should be longer than the collection time to integrate all the charge generated in the de-tector. Otherwise, the pulse amplitude in the readout electronics is proportional only to the fraction of generated charge and this phenomenon is called ballistic deficit [4].

2.5. RAMO THEORY AND SIGNAL FORMATION

After the charge generation, the holes and electrons start to move in the detector medium because of the applied electric field. A movement of generated charge carriers induces current pulse in detector electrodes (a current flow i(t) in the circuit connected to the detector electrode). The current flow begins instantaneously and finishes when all the charges (both electrons and holes) are collected. The polarity of induced currents by holes and electrons on a given detector electrode are the same, because the charges of opposite signs move in opposite directions. The current ik(t) induced at k electrode of the detector by the infinitesimal movement of the charge q is described by the Ramo theo-rem [35]

wkk Euqti =)( (2.37)

where ku is drift velocity and wE is a weighting field. The weighting field is obtained by applying unit potential to k electrode and zero to all other electrodes and it is differ-ent from the electric field inside the sensor. For practical cases (such as strip or pixel detector) the numerical calculation is necessary to obtain pulse shape at different elec-trodes. The pulse shape strongly depends on initial distribution of electrons and holes, detector geometry and electric field distribution [32, 36].

Consider the simple case with parallel plate geometry and linear field distribution for VR > Vdep as shown in Fig. 2.5(c). The weighting field is in this case Ew = 1/d. Ac-cording to the Ramo theorem the following expression can be written for current in-duced by the motion of charge carriers (see eq. (2.30)(2.31))


+= tNqxqNE

dqti

Si

Dh

Si

Dhh

exp)( 0min (2.38)

+= tNqxqNE

dqti

Si

De

Si

Dee

exp)( 0min (2.39)

The examples of generated current pulse are shown in Fig. 2.6(a).

In case of very large overbias of a detector (VR >> Vdep) the electric field in the de-tector can be approximated as a uniform field E VR /d. The weighting field is in this case Ew = 1/d and velocity is u = VR /d. Using the Ramo theorem one obtains

Rhh Vdqti 2)( = (2.40)

Ree Vdqti 2)( = (2.41)

The examples of the current pulses for the uniform field are shown in Fig. 2.6(b).

(a)

(b)

Fig. 2.6. Examples of pulse shapes for parallel plate geometry and: a) linear field distribution, b) uniform field [32, 37].


2.6. DETECTOR GEOMETRY

A position sensitive semiconductor detector is an array of individual sensor ele-ments and, in most cases, each element is readout by an individual electronic channel (other solutions using charge division effect are also possible [38, 39]). In case of sili-con, the detectors are built as matrices of reverse biased diodes processed on common high-resistivity substrate (510 kcm) of 250500 m thick. The sensitive area can be divided into individual diodes of the shapes according to the geometrical requirements of the experiment, concerning the area to be covered and the spatial resolution. The ex-amples of a strip detector are shown in Fig. 2.7. Single sided strip detectors (mostly with strip pitch in the range from 20 m to 200 m - see Fig 2.7(a)) provide one dimensional information and requires a relatively low number of readout electronic channels per detector area. Sometimes in X-ray imaging systems the silicon strip detector is illumi-nated from the edge (so that photons enter the detector along the strips) [40,41]. The using of detector in edge-on configuration increases the photon absorption for higher X-ray energies.

(a)

(b)

Fig. 2.7. Simplified view of strip position sensitive detector: a) single sided strip, b) double sided strip.

Fig. 2.8. Ambiguity of position reconstruction in double sided silicon strip detectors.


The double sided detector (see Fig. 2.7(b)) is an interesting option for 2-D imag-ing. The second orthogonal set of strips is made on the backside of the detector, how-ever this solution is limited to a low intensity radiation experiment [42]. Assume that two photons hit the detector at the same time (see Fig. 2.8). The two photons produce signals in two upper and bottom strips. From the reconstruction of the hits, four posi-tions are possible: two real hits and two "ghost" hits. To minimize the number of "ghost" hits, radiation intensity must be limited or a very fast and precise coincidence system has to be used.

Fig. 2.9. Simplified view of 2D position sensitive pad detector.

Fig. 2.10. Hybrid pixel detector - sensor and readout chip are connected together using bump-bond

technique.

A real two dimensional imaging is possible using pad or pixel detector - see Fig. 2.9 and Fig. 2.10. A pad detector requires a trace to each electrode, because the readout electronic channels are connected at one, two or four sides of this detector (usu-ally by a simple wire bonging technique) [43]. This limits the maximum number of the readout channels (to about several hundreds of channels). A pixel detector does not have

Semiconductor detectors 23 such limitations. For an X-ray imaging application a pixel area as small as 55 m 55 m [44] is used, however larger pixels like 130 m 130 m [45] or 172 m 172 m [46] are more popular. For HEP application, a rectangle pixel shape is also used like, for example 150 m 100 m [47], 400 m 50 m [48] or 425 m 50 m [49]. The pixel architecture requires that the pixel size of the detector and the pixel size of a single readout electronic channel must be identical (see Fig. 2.10). Power limitation and area limitation for pixel readout electronic are really challenging [50]. Additionally, a bump-bonding process [5, 51] (to connect a sensor and a readout chip together) is not cheap process.

Spatial resolution of position sensitive detectors shown in Fig. 2.7 and Fig. 2.9 is determined not only by geometry of the detector (strip/pixel pitch) but also by: intrinsic spatial resolution of a detector resulting from the interaction of photons with the detector material and charge transport processes (diffusion spread, charge sharing, etc.) [33, 52], parameters of the readout electronic system, especially signal to noise ratio (SNR) is discussed in detail in Chapter 3.

2.7. IMPORTANT DETECTOR PARAMETERS

The 3-D model of a DC coupled Si strip detector is shown in Fig. 2.11 [53]. The components shown in this scheme represent: Cbu - capacitance to the backplane per unit strip length, Cnu - capacitance to the neighbour strips per unit strip length (interstrip capacitance), Rsu - effective resistance of strip per unit strip length. The effective strip resistance is a parallel connection of a highly doped semiconductor strip (diffusion/implantation p+ or n+ type) and a low resistivity metal strip. The resis-tance of the metal strip (usually Al) per unit length depends on the metal thickness and width. For example, for 1 m thick and 20 m wide Al strip has resistance of 1520 /cm.

Fig. 2.11. Simplified 3D model of DC-coupled strip detector.


(a)

(b)

Fig. 2.12. Simplified model of position sensitive detector: a) DC-coupled, b) AC-coupled.

If the current pulse shape is not important for the performed experiment (in most

cases the current pulse is integrated in a charge sensitive amplifier), then the strip resis-tance can be neglected and the model can be significantly simplified to the scheme shown in Fig. 2.12(a), where Cb and Cn represent the total capacitance of the strip to the backplane and to the neighbour strips respectively. An AC-coupled detector model (Fig. 2.12(b)) contains additionally coupling capacitance Cc (between p+ strip and metal strip) and the bias resistance Rbias.

The parameters of the detector are usually measured before connections of the readout integrated circuit, however, some of them can be approximated in advance. The backplane capacitance per strip length is

dp

lC Sib (2.42)

where p is the strip pitch and d is the detector thickness. This capacitance slightly de-pends also on the strip width. For example, for a 280 m thick detector with 50 m pitch the measured Cb/l is 0.150.18 pF/cm (for strip width w is in the range from 1030 m) [53]. The capacitance to the neighbour strip (interstrip capacitance) in a Si detector can be approximated as [54]

++=p

mwl

Cn 2062.103.0 (2.43)

where, in the above formula, the strip width and pitch in m and Cn/l are obtained in pF/cm. This capacitance depends on the quality of field oxide between strips and usually increases after strong irradiation. In most cases this capacitance is in the range of 0.81.5 pF/cm [5255].


In case of an AC-coupling detector, one should also take into account also de-coupling capacitance Cc/l = 10-30 pF/cm and bias resistance Rbias. The bias resistance depends on the used structure to bias the detector (diffusion resistor, FOXFET structure, etc.) and it varies in the range from 200 k up to over 100 M.

An additional detector parameter is detector leakage current Idet which strongly depends on the bulk material quality (high resistivity Si is better but more expensive), process production, temperature and radiation damage. For example, for a good new Si detector with 50 m pitch and standard 300 m thickness, this leakage current should be below 100 pA/cm (at room temperature).

A simplified model for a pixel detector is similar to the one shown in Fig. 2.12 (a). The capacitance to the backplane for pixel area A is

dAC Sib

(2.44) For example, for a 300 m thick detector with the pixel area A equals to

100100 m2, this capacitance is about 3.5 fF. The more important component is ca-pacitance to the neighbour pixel and it strongly depends on implant/diffusion area. One has to expect the total capacitance for a 125125 m2 square pixel is of 100 fF, and of about 200 fF for a long and narrow 40050 m2 pixel [5]. Because the capacitance of a pixel detector itself is really small, other parasitic components of the closely spaced detector readout electronics should be taken into account (capacitance between the detector and ground/bias plane of readout IC, capacitance of bump bonds etc.).

As for the noise performance of the detector readout system, three parameters of position sensitive detector are important: total capacitance per strip/pixel (sum of bulk capacitance, interstrip capacitance, para-sitic capacitance of the connection with readout IC), shot noise of detector leakage current (per strip/pixel), thermal noise of the bias resistor (AC coupled detectors only). The noise performance of readout electronics is discussed in detail in Chapter 3.

The second effect related to detector capacitance is the crosstalk between detector electrodes. Due to interstrip/interpixel capacitance, the charge deposited on a single electrode can induce parasitic signals on neighboring strips/pixels. Consider the simple scheme shown in Fig. 2.12(a). In most systems, the relationship between input capaci-tance Cin of readout electronics and detector capacitances are the following

bnin CCC >>> 2 (2.45)


Fig. 2.13. Simplified model of one detector electrode together with the input capacitance Cin of readout

electronics.

The simplified scheme of one electrode node can be drawn as shown in Fig. 2.13. The charge Qtot deposited at node X leads to the voltage

bnin

totX CCC

QV ++= 2 (2.46)

The charge Qin which flows to the readout electronics is

+++=++= bnin

bntotin

bnin

totin CCC

CCQCCCC

QQ2

212

(2.47)

The remaining charge fraction (Qtot Qin) is located by half on left and right elec-

trodes. To minimize this crosstalk between the electrodes, the effective input capaci-tance Cin of readout electronics must be much higher than the total strip/pixel capaci-tance (2Cn + Cb).

Architecture of front-end electronics 27

3. ARCHITECTURE OF FRONT-END ELECTRONICS

The current pulse provided by the sensor is amplified and shaped in the front-end electronics. Different modes of signal acquisition are possible: current mode, voltage mode or mode with Charge Sensitive Amplifier (CSA) at the input. An example of front-end electronics using the mode with CSA is schematically shown in Fig. 3.1. A current signal generated in the silicon strip/pixel detector is integrated in a charge sensitive preamplifier. At the output of the preamplifier one obtains a voltage step with amplitude proportional to the total charge generated in the detector. The voltage step is fed to the main amplifier called a shaper, which provides pulse shaping according to the timing requirements and the filtration of noise to maximize the signal to noise ratio.

Further processing of the shaped signal can be done in different ways depending on specific applications. Possible options are schematically shown in Fig. 3.1. The first one is based on so-called binary readout architecture. In that case the comparator detects

28 Architecture of front-end electronics

the presence of the signal of amplitude above the preset threshold and in response pro-vides 1-bit yes/no information. The second way of processing the shaped signal employs an analog-to-digital converter (ADC), where the amplitude of the signal corresponding to each individual photon is measured, and then the information is stored and used for off-line processing. The third option is used for timing measurements - determination of the time of occurrence.

Fig. 3.1 Example of a front-end electronics used in a detector readout system.

The number of front-end channels in readout systems in most cases is equal to the

number of strips/pixels in the semiconductor detector. In case of readout electronics for strip detector, multichannel integrated circuits are mostly designed as 32, 64 or 128 channels integrated circuits, which are the basis for building larger modules consisting of several hundreds up to a few thousands readout channels (see Fig. 3.2) [56].

Fig. 3.2. Fragment of multichip module: 512- strip detector connected to eight 64-channel readout ASICs.


3.1. TYPES OF AMPLIFIERS

The signal reception from a detector can be realized in the front-end electronics in three main modes [32, 37]: current mode: to preserve pulse shape, voltage mode: to obtain high signal amplitude at the amplifier input, mode with charge sensitive amplifier to integrate a detector current pulse.

As the option with the CSA is most widely used in the front-end electronic system it is presented in detail in the next chapter. To distinguish between the current and volt-age modes, a simplified scheme of a detector and input amplifier is useful (see Fig. 3.3). The capacitance CT is a sum of detector capacitance Cdet, input transistors capacitance C1 and stray capacitance Cpar of the connection between the detector and front-end electron-ics. The resistance Rin represents the input resistance of the amplifier. For the detector pulse, the current iD provided to the amplifier can be written as

inTDR RsC

sisi += 11)()( (3.1)

Fig. 3.3. Simplified scheme of a detector and input amplifier [37].

In the current mode the signal from the detector is amplified without change in its shape. This requires a very low input time constant in= RinCT and this means the re-quirements of small input resistance Rin of the amplifier.

In the voltage mode the voltage signal produced at the input of the amplifier is much higher thanks to high value of the input resistance Rin and it can be written as


ininT

DR RRsCsisv += 1

1)()( (3.2)

However, the above increase of pulse amplitude vR results in long time constant in at the amplifier input and the detector pulse shape is no longer preserved but it is determined by this long time constant. The possible practical realization of current and voltage modes are schematically shown in Fig. 3.4 (timp is the charge collection time at detector electrode).

(a)

(b)

Fig. 3.4. The examples of realization of an input stage of front-end electronics: a) current configurations, b) voltage configurations.


3.2. CHARGE SENSITIVE AMPLIFIER

3.2.1. Ideal charge sensitive amplifier

The option with ideal charge sensitive amplifier at the input is shown in Fig. 3.5. The capacitance CF is connected in the feedback of the core amplifier with the gain of K0.

Fig. 3.5. Simplified scheme of a charge sensitive amplifier.

Summing the current at the CSA input one obtains

Foutout

Tout

D sCvKvsC

Kvsi

+=

00

)( (3.3)

where vout is the voltage at CSA output. The above equation gives the CSA transfer function

TFD

out

CCKK

ssisv

++= )1(1

)()(

0

0 (3.4)

which for K0 >> 1 simplifies to:


FD

out

sCsisv 1)()( (3.5)

Using the eq. (3.4) the signal at CSA output can be written as

++=impt

DTF

out dttiCCKKtv

00

0 )()1(

)( (3.6)

where timp is the charge collection time at the detector electrode. Assuming at the input the delta-like current pulse iD(t) = Qin(t) one obtains at the CSA output the voltage step which is proportional to total charge carried by the detector pulse

inTF

out QCCKKtv ++= )1()( 0

0 (3.7)

For K0 >> 1 the above equation can be simplified to

F

inout C

Qtv =)( (3.8)

The important feature of an ideal CSA is an independence of the output voltage to the detector capacitance which is guaranteed by the requirement

TF CCK >>+ )1( 0 (3.9) For the ideal integrator its input impedance Zin is capacitive and the effective high

input capacitance is guaranteed by the high gain K0 of the amplifier (due to the Miller effect [24])

FF

in sCKsCKsZ

00

1)1(

1)( += (3.10)

The large input capacitance of CSA and the requirements (3.9) guarantee that most of the charge produced by the detector is transferred to the amplifier (see eq. (2.47)).


3.2.2. Realistic charge sensitive amplifier

In a realistic CSA two additional aspects should be taken into account: feedback capacitance CF has to be discharged to avoid saturation of the amplifier, e.g. by the effective resistance Rf connected in parallel to CF, the core amplifier has frequency-dependent voltage gain, which in the simplest form with one pole can be written as

0

0

1)()(

sK

Ksvsv

Vin

out

+== (3.11)

where K0 is the DC gain and 0 is the dominant pole of the amplifier. The gain band-width product of the amplifier is GBW = K00. With the above aspects in mind let us consider the CSA scheme shown in Fig. 3.6 with additional unity gain buffer to ensure small output impedance [5]

Fig. 3.6. Charge sensitive amplifier based on a core amplifier with frequency dependent voltage gain.

Summing the currents in the input node one obtains

( )

++= F

foutinTinD sCR

svsvsCsvsi 1)()()()( (3.12)


Substitution in (3.12) the vin(s) from eq. (3.11) results in

0

2

00

0

0

1)1(1)()(

FT

fFT

f

D

out

CCsR

CKCsR

KK

sisv

++

+++++

= (3.13)

Because K0 >> 1 and assuming that the requirement DF CCK >>+ )1( 0 is ful-filled the equation (3.13) can be rewritten as

( )GBW

RCCs

GBWCRs

Rsisv

fFTFf

f

D

out ++

++

211)()(

(3.14)

The above transfer function has two poles 1 and 2 which are usually real and widely separated (1


The second high-frequency pole according to (3.13) - (3.16) is given by

FT

F

CCCGBW +2 (3.18)

There are two time constants connected with the above poles feedback time con-stant f = 1/1 and 2 = 1/2 and the transfer function of the CSA can be rewritten as

( )( )

++=++ 22

22 111

11)()(

ssCssR

sisv

f

f

f

f

Ff

f

D

out (3.19)

In the time domain in response to the input current pulse iD(t) = Qin(t) one ob-tains at the CSA output

( ) ( )[ ]22

expexp)(

ttCQtv f

f

f

F

inout = (3.20)

The exemplary time responses are shown in Fig. 3.7. The time constant f is re-sponsible for slow signal decay and 2 determines the rise time at CSA output.

For very high feedback resistance Rf (according to (3.17) the time constant f ) one obtains

( )[ ]2exp1)( tCQtv

F

inout (3.21)

For a very fast core amplifier GBW (according to (3.18) the time constant 2 0) and finite f the equation (3.20) simplifies to

( )fF

inout tC

Qtv = exp)( (3.22)


(a)

(b)

Fig. 3.7. Time response of the CSA for different time constants (horizontal scales in both figures are different): a) f is responsible for slow signal decay, (b) 2 determines the rise time at CSA output.

The realistic CSA amplifier has also different input impedance than specified by eq. (3.10). For low frequency > 0 the gain drops linearly with frequency and it can be expressed as

sGBW

sKKV = 00 (3.24)

Assuming large Rf and for high frequency >> 0 the input impedance of CSA is

GBWCsCGBWssZ

FFin

11)( = (3.25)


This impedance appears as a resistance Rin = (CF GBW)-1. The situation at the in-put of the amplifier becomes similar to situation shown in Fig. 3.3. The time constant at the CSA input in= RinCT equals

GBWCC

F

Tin = (3.26)

In order to transfer quickly the charge generated by the detector to the charge sensitive amplifier, the GBW of the core amplifier must be sufficiently large.

3.2.3. Examples of core amplifier architectures

Cascode amplifier architecture is one of most commonly used solutions for CSA core [5769] because of its simplicity, high output resistance, reduction of unwanted Miller multiplication of gate-drain capacitance Cgd of the input transistor and possible operation at high frequency. A differential amplifier configuration is also used espe-cially in case of required good power supply rejection ratio [44, 6871], however it gives worse noise performance than single ended stages. There are also some successful designs using a CMOS inverter for CSA core (NMOS and PMOS transistors with both gates connected at the input and their drains connected as an output). This solution pro-vides low noise performance, however with limited open-loop gain [72,73].

(a)

(b)

Fig. 3.8. Examples of core amplifiers: a) cascode stage, b) folded cascode stage.


The simple cascode is shown in Fig. 3.8(a). The main transistor M1 sometimes operates at lower supply voltage to save power consumption. Its dimensions are sized according to input detector capacitance to minimize the noise (see Chapter 3.3.2). The primary function of M2 is to keep small signal resistance at the drain of M1 low. There-fore, the cascode transistor M2 has sufficiently high transconductance and collects all signal current from M1. In the simple cascode the same current flows through M3 and M1 transistors, which makes it difficult to obtain simultaneously high transconductance gm1 of input transistor M1 and high output resistance rds3 of transistor M3 at the same time. An additional current source connected like transistor M4, can help in this case [61, 74]. The M4 which sinks the significant part of current from transistor M1 and al-lows obtaining high gm1/gds3 ratio and high gain in low frequency region. The output source follower M5M6 works as an output buffer.

For a connection of DC feedback loop and for an operation of the input transistor with lower supply voltage, the folded cascode configuration (shown in Fig. 3.8(b)) is more convenient. To obtain higher output resistance of the folded cascode stage a cur-rent cascode source is often used, instead of a simple current mirror M4.

The input transistor of the cascode stage can be NMOS or PMOS and the choice of the transistor type depends on: noise performance of both types of transistor in the selected technology, sensitivity of a given transistor type to a substrate noise, other aspects, for example, quality of NMOS or PMOS current sources in case of us-ing enclosed gate transistor layout, etc.

Taking into account the folded cascode only i.e. the transistors M1M4 (without output source follower M5-M6 and neglecting the bulk effect of M2 gmb2 = 0) the low frequency voltage gain can be written as

)()()(

42123412

221

dsdsdmdsdsdsds

dsmm

in

X

ggggggggggg

vv

++++++= (3.27)

where gm1 gm4 are transconductances of transistors M1M4 and gds1 gds4 are their out-put conductances. Assuming that gm2 >> gds1, gds2, gds4 and gds3 gds2 , the above equa-tion can be rewritten as

3

1

ds

m

in

out

gg

vv (3.28)

The dominant pole of the folded cascode can be expressed as

XX RC1

0 = (3.29)

Architecture of front-end electronics 39 where the total capacitance seen from the node X equals to CX. RX is given as

( ) ( )[ ]{ }2412413 1|||||| dsdsdsmdsdsdsX rrrgrrrR ++ (3.30)

The simplified noise scheme of the folded cascode is shown in Fig. 3.9. The noise calculated to the cascode input is given as

( )df

dvgg

dfdv

gg

dfdv

ggg

dfdv

dfdv n

m

mn

m

mn

m

dsdsnn24

21

24

23

21

23

22

21

241

21

2

++++= (3.31)

where gds1 =1/rds1 and gds4=1/rds4. In a good design the dominant part of the noise comes from the main transistor M1, because gm1 is high. However, special attention should be paid to current source M4 and its reference (not shown in Fig. 3.8(b)). The problem is that drain currents of transistors M1 and M4 (for cascode design used in CSA applica-tion) are nearly equal and to reduce the last term in eq. (3.31), a designer should keep the transconducance gm4 of current source M4 as small as possible (i.e. using transistor M4 with relatively long channel L4).

Fig. 3.9. Simplified noise scheme of a folded cascode stage.


3.2.4. Feedback configuration

After integration of a current pulse in the CSA, the feedback capacitor CF should be discharged by the reset block (Fig. 3.5) during a short period of time to prevent satu-ration of the amplifier [75]. There are two basic techniques implemented for discharging the feedback capacitance: switch reset and continuous discharge.

(a)

(b)

(c)

(d)

(e)

(f)

Fig. 3.10. Most frequently used reset systems in CSA feedback - see description in text below.

A switch reset technique is shown schematically in Fig. 3.10(a) [76, 77]. A switching circuit periodically resets the feedback capacitor. The trigger signal for discharging the capacitors can be provided by the central clock of an experiment or gen-erate individually in each channel. In case of X-ray measurements the signals appear randomly in time and independently in each channel. After receiving a signal from the detector electrode, the circuit has to generate a trigger signal to discharge the capacitor. In order to generate such a trigger signal one needs to implement a threshold discrimina-tor in every channel. One can also apply a reset signal to all channels synchronously, after a certain period of time, having in mind the maximum rate of input pulses and

Architecture of front-end electronics 41 a saturation limit of the CSA, however such a solution results in additional deadtime of the whole system. The disadvantages of this solution are sampled noise and a possible problem with charge injection from switch control voltage.

Continuous discharging can be completed either by a resistor parallel to the ca-pacitor or by a controlled current source (see Fig. 3.10(b)(f)). In either case, the dis-charging component contributes to the parallel noise at the CSA input. In order to limit this noise source, one should use a large value resistor or a low discharging current. Using a physical resistor (Fig. 3.10(b)) seems to be a simple solution, however the resis-tance should be in the range from hundreds of k to a few G (resistor value depends on noise requirement of an experiment and a peaking time of the shaper). It is difficult to obtain large value resistance in a monolithic process with a low parasitic capacitance. Instead of a simple resistor, many designers use a feedback MOS transistor working in triode or saturation region [57, 78, 79]. This is a compact solution with the possibility to control feedback resistance, however nonlinear effects must be taken into account.

More complex feedback solutions are shown in Fig. 3.10(d)(f): the configuration shown in Fig. 3.10(d) uses a current conveyor feedback [80, 81]. In response to a signal at CSA output a reference current is produced in a low value resistor R. This reference current is significantly reduced in the network based on current mirror and discharges the feedback capacitor, the technique shown in Fig. 3.10(e) is also based on a current mirror and uses a cur-rent source [82, 83]. With no activity, the feedback transistor M2 stays in the linear re-gion. When the signal appears, the M2 enters the saturation region and the copy of bias current Ibias discharges the capacitor, discharge system shown in Fig. 3.10(f) uses a differential stage. The baseline recov-ery after signal integration is achieved by the low frequency feedback loop that sets the output voltage of the CSA to the reference voltage VREF [84]. Proper circuit compensa-tion is an important issue in this case. The effective feedback resistance is equal to Rf = 2/gm1. Other solutions using a differential stage are also possible [58, 85], but with-out the mentioned above low frequency feedback.

There are also two aspects which should be taken into account while choosing one of the above options as reset system in given applications, namely: for a DC coupled detector leakage current should be automatically accommodated by the CSA - the good candidates are e.g. the solutions in Fig. 3.10(c) (especially with the feedback transistor working in saturation region) and in Fig. 3.10(f), the long decay time constant of the preamplifier output signal, which produces the limitations of the pulse rate due to the pulse pile-ups. The implementation of the Pole-Zero Cancellation (PZC) circuit can significantly help in this case (see Chapter 3.4.2) and adding of a PZC circuit is relatively easy in the cases shown in Fig. 3.10(b) and 3.10(c).


3.2.5. Test injection circuit

As discussed before, the detector can be considered as a source of a charge signal. Thus, for measuring analog parameters one has to inject some charge to the CSA input. It is important to verify the correct operation of an integrated circuit on the wafer level or later, when the integrated circuit is mounted in the module and the detector has still not been connected. This is typically done by applying a voltage step Vtest through a small test capacitor Ctest at the input of the CSA as shown in Fig. 3.11.

Fig. 3.11. Small capacitor Ctest at CSA input can work as charge injector.

The injected charge is equal to

( )testtest

FVdet

test

testtesttest CV

CKCC

CVQ +++

=1

1 (3.32)

Since in practice Ctest

Architecture of front-end electronics 43 application of voltage step function seems more appropriate in this case. Generating a voltage step function inside the integrated circuit is difficult, but it can be applied using an external arbitrary waveform generator. Another option is to feed a known small current Iinj to the preamplifier input during a known time interval Tinj. The injection charge is equal to Qtest = IinjTinj.

(a)

(b)

Fig. 3.12. Possible realization of the test injection circuits: a) generation of voltage steps on resistor R [86], b) switching between two lines with different DC potentials [87].

3.3. SHAPER

The shaper stage after the CSA is added to perform the following tasks: to filter the CSA output signal in order to improve the signal to noise ratio in the sys-tem, to add more gain in the signal processing chain, to shorten the pulse duration and to reduce the possibility of pile-up pulses.

The choice of the filter type, order and its time constants strongly depends on specified energy resolution of the readout system and its high rate operation require-ments [2, 32, 8892]. There is a wide range of shapers built in hybrid technologies and which use components of the shelf. However, in case of a multichannel ICs there are additional very strong requirements on a low power budget and a small area occupied by the single channel, and a practical realization of all filter types in the IC technology is limited. For the purpose of this book three types of filters often used in the multichannel ICs are described:


unipolar semi-Gaussian pulse shaper CR-(RC)n, bipolar semi-Gaussian shaper with two high-pass sections (differentiators) and n inte-grators of type CR2-(RC)n, nearly true Gaussian shaper obtained using Ohkawa synthesis method [93].

At first, the transient response of these filters to a voltage step (obtained at a CSA output) is described. In Chapter 3.3.2 the improvement of the signal to noise ratio in the detector system by using the filters is analyzed in detail.

Definitions used in the pulse shaping time are as follows (see Fig. 3.13) [94, 95]: tp: pulse peaking time, measured from 1% of the peak height to the center of the peak, tp1: bipolar pulse peaking time, measured from 1% of the peak height to the center of its peak, tp2: bipolar pulse peaking time, measured from 1% of the peak height of the primary lobe to the peak of the undershoot, txo: crossover time of a bipolar pulse, tm: width of the pulse at the fraction m of its peak height, where m is specified as 0.1, 0.01 etc.

(a)

(b)

Fig. 3.13. Timing definition in pulse shaping: a) unipolar pulse, b) bipolar pulse [94, 95].

3.3.1. Signal shaping

Unipolar semi-Gaussian pulse shaper. A simple semi-Gaussian pulse shaper of type CR-(RC)n, which consists of one CR differentiator and n integrators (Fig. 3.14), becomes one of the most popular in the multichannel ICs.


Fig.3.14. Semi-Gaussian pulse shaper of type CR-(RC)n.

For the CR-(RC)n filter with the same integrator and differentiator time constants i = d = the transfer function is given by [92, 96]

n

ssssH

+

+=

11

1)( (3.33)

Assuming an ideal unity voltage step at the shaper input and taking the transfer function of the filter given by (3.33), one obtains the shaper output signal in the time domain as

= tt

ntv

n

out exp!1)( (3.34)

The peak amplitude of the signal is

n

n

ennv!max

= (3.35)

with the peaking time tp = n . The family of shaper output pulses for a given time con-stant is shown in Fig. 3.15(a). Increasing the filter order results in decreasing the sig-nal amplitude, but makes the pulse more symmetrical. Higher filter order is more suit-able for high rate application, however to obtain the same peaking time for the higher shaper order, one should shorten the time constant of the filters. The family of the pulses with the normalized amplitude and the time scale, but different orders, is shown in Fig. 3.15(b). For higher order filters the shaper output pulse returns to the baseline faster, and this directly influences the high rate operation and reduces the probability of

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