Research ArticleError Detection and Correction On-Board Nanosatellites UsingHamming Codes

Caleb Hillier and Vipin Balyan

Department of Electrical Electronic and Computer Engineering Cape Peninsula University of TechnologyCape Town South Africa

Correspondence should be addressed to Vipin Balyan vipinbalyanrediffmailcom

Received 29 October 2018 Revised 30 December 2018 Accepted 14 January 2019 Published 10 February 2019

Academic Editor Yagang Zhang

Copyright copy 2019 Caleb Hillier and Vipin Balyan-is is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

-e field of nanosatellites is constantly evolving and growing at a very fast speed -is creates a growing demand for moreadvanced and reliable EDAC systems that are capable of protecting all memory aspects of satellites -e Hamming code wasidentified as a suitable EDAC scheme for the prevention of single event effects on-board a nanosatellite in LEO In this paper threevariations of Hamming codes are tested both in Matlab and VHDL -e most effective version was Hamming [16 11 4]2 -iscode guarantees single-error correction and double-error detection All developed Hamming codes are suited for FPGAimplementation for which they are tested thoroughly using simulation software and optimized

1 Introduction

Satellites have many applications with earth observation(EO) being one of the primary applications EO satellites usesmart image sensors to monitor and capture data on theearthrsquos surface and in some cases infrared is used to lookbeneath -is information can be used to monitor urbandevelopment vegetation growth natural disasters etc Withsatellite imaging constantly evolving and improving thecaptured information contains higher detail and improvedresolution (smaller than 1meter) making the data moreuseful -is is achieved using a wide range of spectral bandcameras [1] With constant improvement the captured dataare becoming increasingly sensitive and valuable -is re-sults in a growing need for security privacy and reliabilityon-board satellites [1 2] It has been proven that satelliteswhilst in orbit are susceptible to unauthorized intrusionsmeaning a satellite can be hacked Cryptographic protectioncan be implemented to provide protection against theseintrusions Usually satellite links are modelled with anAWGN channel [3 4] Encryption is the most popular andconventional method adopted for cryptographic protectionagainst unauthorized intrusions on earth and in spaceEncryption on-board EO satellites have become the normwhen data are transmitted between the satellite and the

ground station [5] However the encryption algorithmstypically implemented are proprietary or outdated algo-rithms like DES -is raises concerns as encryption algo-rithms protecting potentially highly sensitive informationshould meet the current and latest encryption standards [6]

-e Hamming error correction and detection code werefirst introduced by Richard Hamming in 1950 -e workinitially conducted on Hamming codes allowed large-scalecomputing machines to perform a large number of opera-tions without a single error in the end result [7] Hammingcode is a linear block error detection and correction schemedeveloped by Richard Hamming in 1950 [7] -is schemeadds additional parity bits (r) to the sent information (k)-e codeword bits can be calculated according to n 2rndash 1-is means the amount of information data bits can becalculated by k 2r minus rndash 1 Using a parity-check matrixand a calculated syndrome the scheme can self-detect andself-correct any single-event effect (SEE) error that occursduring transmission Once the location of the error isidentified and located the code inverts the bit returning it toits original form Hamming codes form the foundation ofother more complex error correction schemes -e originalscheme allows single-error correction single-error detection(SECSED) but with an addition of one parity bit an ex-tended Hamming version allows single-error correction and

HindawiJournal of Electrical and Computer EngineeringVolume 2019 Article ID 3905094 15 pageshttpsdoiorg10115520193905094

double-error detection (SECDED) [8] Table 1 shows theoriginal Hamming codersquos classification and parameters

-e Hamming code initially started as a solution for theIBM machines that crashed when an error occurred Whenthe code was developed it was considered a breakthroughbut no one in 1950 could have predicted it being used toensure data reliability on-board nanosatellites Due to thecapabilities and versatility of Hamming codes new papersare constantly published

11 Background EDAC codes are classified mainlyaccording to the approach the code takes when performingerror detection and correction Hamming codes fall underthe following classifications Error detection and correctioncodes gt Forward error correction (FEC) gt Block gtBinary codes -is is shown graphically in Figure 1

A Hamming block is basically a codeword containingboth the information signal (k-bit long) and parity bits (r-bitlong)-eHamming scheme can function using a systematicor nonsystematic codeword (Table 2)

12 EDAC Scheme Selection -e EDAC scheme selection isalmost solely dependent on its application -e work in thispaper focuses on EDAC on-board a nanosatellite -isimplies that a solution is needed to detect and correct errorsinduced by radiation on-board a nanosatellite during its lowearth orbit (LEO) specifically the ZA-Cube missions

-e ZA-Cube missions are a series of nanosatellitemissions being developed by French South African Instituteof Technology (FSATI) in collaboration with Cape PeninsulaUniversity of Technology (CPUT) -e name of this initialnanosatellite is the ZA-cube 1 [9] -e successor to ZA-cube1 will be ZA-Cube 2 which will orbit at around 550Km [10]

Ideally the effects of single-error upset (SEU) andmultiple-error upset (MEU) should have been monitored inZA-cube 1 unfortunately this was not done and thereforethis information is unavailable However this data weregathered by the Alsat-1 which was the first Algerianmicrosatellite launched into LEO -is work was published[11] -is data is a good indication of what ZA-cube 2 will beexposed to as the Alsat-1 is also sun synchronised orbit(SSO) and LEO (ZA-cube 2 orbit being roughly 100Kmcloser to earth) -is means the radiation dosages for ZA-cube 2 should be slightly lower than that experienced bythe Alsat-1 However the data from the Alsat-1 can beconsidered as a worst case scenario for ZA-cube 2 -is datais shown Table 3 [11]

Using the data provided in Table 3 it becomes apparentthat SEU is by far more likely error to occur as a result ofradiation SEU on average cause plusmn97 bit flips to occurduring a single day (Figure 2) Obviously the majority(about 80) of these errors occur while the nanosatellite istraversing through the SAA which could range roughlybetween 5 and 10 minutes

Using the information shown using Table 3 and Figure 2Hamming code will be used as the EDAC scheme imple-mented to deal with SEU Hamming code allows both errordetection and correction of single-bit upsets and can be

extended to detect double bit flips Once a double bit flipis detected the information can be erased and a requestto resend the information can be raised Should the nano-satellite be traveling through the South Atlantic Anomaly(SAA) it is possible to implement triple modular re-dundancy (TMR) that can deal with double-byte errors andsevere errors

Hamming code was selected mainly as it meets theEDAC requirements implementation complexity is mini-mum and cost of additional hardware is kept minimal Forexample commercial off-the-shelf (COTS) devices can beused

2 Overview of Hamming Code

In the sections to follow a detailed overview of the Ham-ming code will be given By touching on the parameters andfoundation principles the reader should have a solid un-derstanding of the Hamming code

Hamming code is an EDAC scheme that ensures noinformation transmittedstored is corrupted or affected bysingle-bit errors Hamming codes tend to follow the processillustrated in Figure 3 -e input is errorless information ofk-bits long which is sent to the encoder -e encoder thenapplies Hamming theorems calculates the parity bits andattaches them to the received information data to form acodeword of n-bits -e processed information whichcontains additional parity bits is now ready for storage

-e type of storage is dependent on the applicationwhich in this paper is RAM used by the on-board computer(OBC) of a nanosatellite It is during storage that errors aremost likely to occur Errors usually occur when radiatedparticles penetrate the memory cells contained within theRAM -ese errors are defined as bit flips in the memoryHamming codes are capable of SECSED but can be extendedto SECDED with an additional parity bit

-e decoder is responsible for checking and correctingany errors contained within the requested data -is is doneby applying the Hamming theorem which uses a parity-check matrix to calculate the syndrome-e decoder checkslocates and corrects the errors contained in the codewordbefore extracting the new error-free information data

21GeneralAlgorithm Asmentioned previously Hammingcode uses parity bits to perform error detection and cor-rection -e placement of these parity bits is dependent on

Table 1 Hamming code classification and parameters

Hamming code Hamming (7 4)Developed by Richard HammingType Linear block codeCode rate 1ndash(r(2rminus 1))

Alphabet (Σ) q 2Block length n 2rminus 1 where rge 2 n 7Message length k 2rminus rminus 1 k 4Distance dmin le nndashk + 1 dmin 3Notation [2rminus 1 2rminus rminus 1 dmin]2 [7 4 3]2

2 Journal of Electrical and Computer Engineering

whether or not the code is systematic or nonsystematic InTable 4 a typical codeword layout is shown Please note thatthis table only includes bit positions 1 to 16 but can continueindefinitely From Table 4 the following observations can bemade

(i) Bit position (codeword) is dependent on theamount of data bits protected

(ii) Parity bit positions are placed according to 2 to thepower of parity bit

(a) 20 1 21 2 22 4 23 8 and 24 16

(iii) Parity bitrsquos relationship to bit position and data bits(also shown using Figure 4)

(b) Parity bit 1 (P1) represents bit position 1 (P1)3 5 7 etc (all the odd numbers)

(c) Parity bit 2 (P2) represents bit position 2 (P2)3 6 7 10 11 etc (sets of 2)

(d) Parity bit 4 (P4) represents bit position 4 (P4)5 6 7 12 13 etc (sets of 4)

(e) Parity bit 8 (P8) represents bit position 8 (P8)9 10 11 12 13 etc (sets of 8)

(f ) Parity bit 16 (P16) represents bit position 16(P16) 17 18 19 etc (sets of 16)

(iv) -e position in between the parity bits are filled withdata bits

(v) -e layout makes each column have a unique paritybit combination for each bit position

Error control

Automatic repeat request (ARR)

Block code

Hybrid automatic repeat request

(HARR)

Forward error correction (FEC)

Block code

Nonbinary

ReedndashSolomon Codes

Systematic

Nonsystematic

Binary

Hamming codes

BCH codes

Convolutional code

Binary

Systematic

Turbo codes

Nonsystematic

Viterbi algorithm

Nonbinary

Error control

Forward error correction (FEC)

Block code

Binary

Hamming codes

Figure 1 Classification of Hamming code

Table 2 Systematic and nonsystematic codewordsSystematic [k0 k1 k2 k3 k4 k5 k6 k7 r0 r1 r2]Nonsystematic [r0 r1 k0 r2 k1 k2 k3 k4 k5 k6 k7]

Table 3 Memory errors that observed on Alsat-1 during a 7-yearperiod

Event upset observation for Alsat-1System monitored OBC 386 RAMDISK memoryEDAC code R-S (256252)Memory size 32MbytesHybrid SYS84000RKXLI-70 (4M times 8-bit)

Device Samsung SEC KM684000BLT-5L512K times 8-BIT SRAM

Observation period 2510 days November 292002ndashOctober 12 2009

Bits monitored 268435456No of single-bit errors 244150 (986)No of multiple-bit errors 217 (008)No of double-byte errors 2996 (121)No of severe errors 230 (009)

000

2000

4000

6000

8000

10000

008 121 009

Perc

enta

ge

Type of error ()

No of single-bit errors

No of double-byte errors

No of multiple-bit errors

No of severe errors

9860

Likelihood of error occurring in a day

Figure 2 Likelihood of error occurring in a day

Journal of Electrical and Computer Engineering 3

(vi) -is unique parity bit combination is known as thesyndrome value

22 Construction of GeneratorMatrix (G) Generator matrix(G) is used when encoding the information data to form thecodeword G forms one of the foundations on which theHamming code is based Due to the relationship between thegenerator matrix and parity-check matrix the Hammingcode is capable of SECSED

G(ktimesn) is defined as the combination of an identity matrix(I) of size k times k and a submatrix (P) of size k times r [12]

Gktimesn Iktimesk Pktimesr

11138681113868111386811138681113960 1113961 (1)

23 Construction of Parity-Check Matrix (H) Parity-checkmatrix (H) is used when decoding and correcting thecodeword in order to extract an error-free messageH formsone of the foundations on which the Hamming code is

Output

(i) Extracts information datafromerror-free codeword(k-bits long)

(ii) No errors

Decoder

(i) Uses a parity-check matrix to calculate the syndrome

(ii) Locates and correct any errors

(iii) Codeword of n-bits long

(iii) All errors corrected

Storage

(i) Errors due to space radation

(ii) Error in the form of SEU DEU and MEU

Encoder

(i) Uses a generator matrix to calculate the Hamming codeword

(ii) Codeword of n-bits long

(iii) No error

Input

(i) Information data (k-bits long)

(ii) No errors

Figure 3 General layout of Hamming code

Table 4 Bit layout of Hamming code (nonsystematic)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

-e syndrome allows errors to be located and corrected For example if parity bits P1 P4 and P8 show an error the location of the error can be found by1(P1) + 4(P4) + 8(P8) 13-erefore the error affected data bit 9 (D9) in position 13 shown in bold-e above explanation shows the general algorithm usedwhen implementing Hamming code

P3

D2

P2

D1

P1

D4

D3

(a)

P1

P2 P3

P4D1 D8D3

D11

D5

D2 D6

D4 D10

D9 D7

(b)

Figure 4 Parity vs data Hamming (7 3) (a) and Hamming (15 11) (b)

4 Journal of Electrical and Computer Engineering

based Due to the relationship between the parity-checkmatrix and generator matrix the Hamming code is capa-ble of SECSEC

H(rtimesn)is defined as the combination of a negativetransposed submatrix (P) of size k times r and an identity matrix(I) of size r times r [12]

Hrtimesn minusPTktimesr Irtimesr

11138681113868111386811138681113960 1113961 (2)

24 -e Relationship between G and H -e relationshipbetween G and H is shown as

GlowastHT 0 (3)

As a final note on G and H it is possible to manipulatethis matrix from systematic to an equivalent nonsystematicmatrix by using elementary matrix operations which are thefollowing

(i) Interchange two rows (or columns)(ii) Multiply each element in a row (or column) by a

nonzero number(iii) Multiply a row (or column) by a nonzero number

and add the result to another row (or column)

25 Hamming Encoder -e Hamming encoder is re-sponsible for generating the codeword (n-bits long) from themessage denoted by (M) and generator matrix (G) Oncegenerated the codeword contains both the message andparity bits -e codeword is calculated using the formula

codewordnminusbits mod2 Mkminusbits lowastGktimesn( 1113857 (4)

-e mathematical expression in (4) is essentially madeup of AND and XOR gates -e gategraphical expression isillustrated in (Figure 5)

26 Hamming Decoder -e Hamming decoder is re-sponsible for generating the syndrome (r-bits long) from thecodeword (n-bits long) denoted by C and parity-checkmatrix (H) Once generated the syndrome contains theerror pattern that allows the error to be located and cor-rected -e syndrome is calculated using the formula

syndromer mod2 Cnminusbits lowastHTrtimesn1113872 1113873 (5)

-e mathematical expression in (5) is essentially madeup of AND and XOR gates -e gategraphical expression isillustrated in Figure 6

27 Extended Hamming Code -e extended Hammingcode makes use of an additional parity bit -is extra bit isthe sum of all the codeword bits (Figure 7) which in-creases the Hamming code capabilities to SECDED -eextended Hamming code can be done in both systematicand nonsystematic forms Table 5 shows this in a graphicalmanner

P16 in this case is the added parity bit that allows doubleerror detection Bymonitoring this bit and checking whetherthe bit is odd or even allows the double bit error to bedetected which is shown in Table 5 by bold

3 Hamming [16 11 4]2

Hamming [16 11 4]2 is an extended version of Hammingcode With an additional parity bit the code is capable ofdouble error detection (DED) -is code was implementedin a nonsystematic manner which simplifies the detection ofdouble errors-e construction of the generated codeword isshown in Table 6 Using general formulas some perfor-mance aspect of the Hamming [16 11 4]2 can be calculated(Table 7)-is clearly proves that Hamming [16 11 4]2 has abetter code rate and bit overhead than Hamming [8 4 4]2with capabilities of SECSED

In order to implement the Hamming [16 11 4]2 agenerator matrix (G) and parity-check matrix (H) areneeded for the encoding decoding and the calculation of thesyndrome (S) -e following calculations were done in orderto implement the code

Submatrix (P) of 11 times 4 dimensions is shown as

P11times4

1 1 0 0

0 1 1 0

0 0 1 1

1 1 0 1

1 0 1 0

0 1 0 1

1 1 1 0

0 1 1 1

1 1 1 1

1 0 1 1

1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(6)

Identity matrix (I) of size 11 times 11 (7) is used whencalculating G

Iktimesk I11times11

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 0 0

0 0 0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(7)

Journal of Electrical and Computer Engineering 5

From (1) the generator matrix is calculated

G11times15 I11times11 P11times411138681113868111386811138681113960 1113961

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(8)

Following Hamming rules G should be of size k times n-erefore an additional column is needed to satisfy thiscondition for Hamming [16 11 4]2 An 8th parity column isadded to G -is is done by adding an odd or even parity bitto each row

Gktimesn G11times16

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(9)

By considering the nonsystematic Hamming bit layoutin Table 4 G calculated in (9) can be rearranged to form anonsystematic matrix G

G11times16

1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0

1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1

0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 1

0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1

1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(10)

Identity matrix (I) of size 4 times 4 is used to calculate HFrom (2) the parity-check matrix can be calculated Withthe additional parity bit the negative submatrix is not usedas the result is the same H is calculated in (11)

Message (k-bits)

Generator matrix (k times n)

AND gate amp

XOR gate Codeword (n-bits)

Figure 5 Gategraphical expression of hamming encoder formula

Codeword (n-bits)

Transposed parity-check matrix

(r times n)

AND gateamp

XOR gate Syndrome (r-bits)

Figure 6 Gategraphical expression of hamming decoder formula

P3

D2

P2

D1

P1

D4

D3

P4

Figure 7 Parity relationship to data extended Hamming (8 4)

6 Journal of Electrical and Computer Engineering

H4times15 PT11times4 I4times4

11138681113868111386811138681113960 11139614times15

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(11)

Hamming rules stateH should be of size r times n-ereforean additional column and row are needed to satisfy thiscondition for Hamming [16 11 4]2 Due to the fourth paritybit only being used for detection the entire row can be filledwith ones With a fourth row added an 8th parity column isadded toH -is is done by adding an oddeven parity bit toeach row

Hrtimesn H5times16

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(12)

By considering the nonsystematic Hamming bit layoutin Table 4 H calculated above can be rearranged to form anonsystematic matrix H

H5times16

1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1

0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1

0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0

0 0 0 1 1 1 0 0 1 0 1 1 1 1 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(13)

OnceG andH have been derived it is possible to encodeand decode the information data in a manner that is capable

of SECDED -e data is encoded using (4) -is wasimplemented in Matlab using mod-2 additions which areessentially exclusive-OR functions -e same equation wasused to encode the information data in VHDL howeverexclusive-OR gates where used to perform the operation

Hamming [16 11 4]2 makes use of syndrome decodingto locate and correct any errors that occurred in thecodeword during transmission or storage -e syndrome iscalculated according to (5) A for-loop or case statement canthen be used to locate the bit which is flipped within thecodeword Once located the bit is simply inverted returningit back to its original and correct state With the codewordnow error-free the information bits are separated andextracted returning an error-free 11-bit message to thereceiver

4 Implementation

Hamming code was implemented in both Matlab andVHDL -e approach taken to achieve the desired results isexplained with the help of detailed flow charts

41 Matlab For each variation of the Hamming codes aproof of concept model was designed in Matlab -e ap-proach is outlined in Figure 8

42 VHDL Once proof of concept was established usingMatlab Quartus was used to implement the working VHDLmodel -e Hamming code was programmed using VHDLas it allows the behaviour of the required system to bemodelled and simulated -is is a major advantage whenoptimization is required A working model of Hamming [84 4]2 and Hamming [16 11 4]2 was programmed in VHLDusing the approached detailed in Figure 9

5 VHDL Optimization of Hamming [16 11 4]2

In this section the optimization of Hamming [16 11 4]2 isdone -e aim of optimization is to reduce resource usagesreduce time delays improve efficiency etc

Table 5 Bit layout of extended Hamming code (16 11)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

Table 6 Construction of the Hamming [16 11 4] codeword

Codeword (n 16)Information data (k 11) Parity (r 5)

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 P1 P2 P3 P4 P5

Table 7 Calculated performance aspects of Hamming [16 11 4]

Scheme Ed Ec Code rate () Bit overhead ()Hamming [16 11 4]2 2 1 6875 4545

Journal of Electrical and Computer Engineering 7

51 Code Optimization -ere are many ways of optimizingVHDL code Some of the main topics when it comes tooptimization are [13]

(i) Efficient adder implementation(ii) State machines(iii) Signal selection(iv) Storage structure(v) Placement and Routing

In this paper the Quartus Prime package is used to codeanalyse compile and optimize the Hamming code

52 Register Transfer Level (RTL) Viewer of Hamming [16 114]2 Using the RTL viewer provided under tools inQuartus Prime an overview of the IO and VHDL codelayout can be seen in Figure 10 -e overview displays theinput and outputs as well as the components defined inhamming_11_16_mainvhd

Decoder

Forloop

If statement

Use syndrome decodingSyndrome = mod-2 (codeword lowast Hprime)

Run for the full length of codeword

Check for any errors by generating a ldquosearch syndromerdquo for each position in codeword

If statement Compares syndrome and ldquosearch syndromerdquo When equal the error is found and the program

exits the loop

Input

Define all parameters(i) Message bits (k)

(ii) Parity bits (r)(iii) Codeword bits (n)(iv) Generator matrix (G)(v) Parity-check matrix (H)

Start a new Matlab scripted file (m)

Input message (msg)

Use hammgen toolbox to generate and check

parameters

OutputInvert the bit at the found location

Extract message bits from codeword and print to screen location of error and the error free message

Error injector

Simply invert or flip the selected bit or bits

User-injected error

Encoder

Generate parity bits for msg

Generate codewordCodeword = mod-2 (msg lowast G)

Figure 8 Overview of Matlab code (flow chart)

8 Journal of Electrical and Computer Engineering

Using the RTL viewer tool it is possible to step into boththe encoder and decoder -e RTL viewer optimizes thenetlist in order to maximize readability -is allows a uniqueinsight into each VHDL code -e RTL view of the encoderand decoder is shown in Figures 11 and 12

53 Optimization of Hamming [16 11 4]2 -e followingsteps are taken to optimize the code

(i) Remove unnecessary and redundant code(ii) Reduce constants and variables where possible

MainVHD

Open a new VHDL file (vhd) in Quartus

IF statement

Else if

Checks for errors using syndrome

Checks for double bit errors using the added parity bit or syndrome (3)

Elsendashcase statement Searches syndrome value When equal the error is found and the identified bit is flip to

original state

Error injector

DecoderVHD

Input

EncoderVHD

Output

Define all variables(i) Data in (input msg-k)

(ii) Data out (output msg-k)(iii) No error (NE)(iv) Double error detected(DED)(v) Single error correction (SEC)

Input data (msg)

EncodervhdDecodervhd

ModelSim User-injected error

Simply invert or flip the selected bit or bits

Define generator matrix and signals

Generate codewordCodeword = mod-2 (msg lowast G)

Define all components

Call and port map components

Msg lowast G =gt AND Gate

Mod-2 =gt XOR Gate

Return an error free msg or raisean error flag

Output the following variables(i)

(ii)(iii)(iv)

Data out (output msg-k)No error (NE)Double error detected(DED)Single error correction (SEC)

Extract message bits from codeword

Define parity-check matrix and signals

Use syndrome decodingSyndrome = mod-2 (Codeword lowast H)

Codeword lowast H =gt AND Gate

Mod-2 =gt XOR Gate

Figure 9 Overview of VHDL code (flow chart)

Journal of Electrical and Computer Engineering 9

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

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whether or not the code is systematic or nonsystematic InTable 4 a typical codeword layout is shown Please note thatthis table only includes bit positions 1 to 16 but can continueindefinitely From Table 4 the following observations can bemade

(i) Bit position (codeword) is dependent on theamount of data bits protected

(ii) Parity bit positions are placed according to 2 to thepower of parity bit

(a) 20 1 21 2 22 4 23 8 and 24 16

(iii) Parity bitrsquos relationship to bit position and data bits(also shown using Figure 4)

(b) Parity bit 1 (P1) represents bit position 1 (P1)3 5 7 etc (all the odd numbers)

(c) Parity bit 2 (P2) represents bit position 2 (P2)3 6 7 10 11 etc (sets of 2)

(d) Parity bit 4 (P4) represents bit position 4 (P4)5 6 7 12 13 etc (sets of 4)

(e) Parity bit 8 (P8) represents bit position 8 (P8)9 10 11 12 13 etc (sets of 8)

(f ) Parity bit 16 (P16) represents bit position 16(P16) 17 18 19 etc (sets of 16)

(iv) -e position in between the parity bits are filled withdata bits

(v) -e layout makes each column have a unique paritybit combination for each bit position

Error control

Automatic repeat request (ARR)

Block code

Hybrid automatic repeat request

(HARR)

Forward error correction (FEC)

Block code

Nonbinary

ReedndashSolomon Codes

Systematic

Nonsystematic

Binary

Hamming codes

BCH codes

Convolutional code

Binary

Systematic

Turbo codes

Nonsystematic

Viterbi algorithm

Nonbinary

Error control

Forward error correction (FEC)

Block code

Binary

Hamming codes

Figure 1 Classification of Hamming code

Table 2 Systematic and nonsystematic codewordsSystematic [k0 k1 k2 k3 k4 k5 k6 k7 r0 r1 r2]Nonsystematic [r0 r1 k0 r2 k1 k2 k3 k4 k5 k6 k7]

Table 3 Memory errors that observed on Alsat-1 during a 7-yearperiod

Event upset observation for Alsat-1System monitored OBC 386 RAMDISK memoryEDAC code R-S (256252)Memory size 32MbytesHybrid SYS84000RKXLI-70 (4M times 8-bit)

Device Samsung SEC KM684000BLT-5L512K times 8-BIT SRAM

Observation period 2510 days November 292002ndashOctober 12 2009

Bits monitored 268435456No of single-bit errors 244150 (986)No of multiple-bit errors 217 (008)No of double-byte errors 2996 (121)No of severe errors 230 (009)

000

2000

4000

6000

8000

10000

008 121 009

Perc

enta

ge

Type of error ()

No of single-bit errors

No of double-byte errors

No of multiple-bit errors

No of severe errors

9860

Likelihood of error occurring in a day

Figure 2 Likelihood of error occurring in a day

Journal of Electrical and Computer Engineering 3

(vi) -is unique parity bit combination is known as thesyndrome value

22 Construction of GeneratorMatrix (G) Generator matrix(G) is used when encoding the information data to form thecodeword G forms one of the foundations on which theHamming code is based Due to the relationship between thegenerator matrix and parity-check matrix the Hammingcode is capable of SECSED

G(ktimesn) is defined as the combination of an identity matrix(I) of size k times k and a submatrix (P) of size k times r [12]

Gktimesn Iktimesk Pktimesr

11138681113868111386811138681113960 1113961 (1)

23 Construction of Parity-Check Matrix (H) Parity-checkmatrix (H) is used when decoding and correcting thecodeword in order to extract an error-free messageH formsone of the foundations on which the Hamming code is

Output

(i) Extracts information datafromerror-free codeword(k-bits long)

(ii) No errors

Decoder

(i) Uses a parity-check matrix to calculate the syndrome

(ii) Locates and correct any errors

(iii) Codeword of n-bits long

(iii) All errors corrected

Storage

(i) Errors due to space radation

(ii) Error in the form of SEU DEU and MEU

Encoder

(i) Uses a generator matrix to calculate the Hamming codeword

(ii) Codeword of n-bits long

(iii) No error

Input

(i) Information data (k-bits long)

(ii) No errors

Figure 3 General layout of Hamming code

Table 4 Bit layout of Hamming code (nonsystematic)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

-e syndrome allows errors to be located and corrected For example if parity bits P1 P4 and P8 show an error the location of the error can be found by1(P1) + 4(P4) + 8(P8) 13-erefore the error affected data bit 9 (D9) in position 13 shown in bold-e above explanation shows the general algorithm usedwhen implementing Hamming code

P3

D2

P2

D1

P1

D4

D3

(a)

P1

P2 P3

P4D1 D8D3

D11

D5

D2 D6

D4 D10

D9 D7

(b)

Figure 4 Parity vs data Hamming (7 3) (a) and Hamming (15 11) (b)

4 Journal of Electrical and Computer Engineering

based Due to the relationship between the parity-checkmatrix and generator matrix the Hamming code is capa-ble of SECSEC

H(rtimesn)is defined as the combination of a negativetransposed submatrix (P) of size k times r and an identity matrix(I) of size r times r [12]

Hrtimesn minusPTktimesr Irtimesr

11138681113868111386811138681113960 1113961 (2)

24 -e Relationship between G and H -e relationshipbetween G and H is shown as

GlowastHT 0 (3)

As a final note on G and H it is possible to manipulatethis matrix from systematic to an equivalent nonsystematicmatrix by using elementary matrix operations which are thefollowing

(i) Interchange two rows (or columns)(ii) Multiply each element in a row (or column) by a

nonzero number(iii) Multiply a row (or column) by a nonzero number

and add the result to another row (or column)

25 Hamming Encoder -e Hamming encoder is re-sponsible for generating the codeword (n-bits long) from themessage denoted by (M) and generator matrix (G) Oncegenerated the codeword contains both the message andparity bits -e codeword is calculated using the formula

codewordnminusbits mod2 Mkminusbits lowastGktimesn( 1113857 (4)

-e mathematical expression in (4) is essentially madeup of AND and XOR gates -e gategraphical expression isillustrated in (Figure 5)

26 Hamming Decoder -e Hamming decoder is re-sponsible for generating the syndrome (r-bits long) from thecodeword (n-bits long) denoted by C and parity-checkmatrix (H) Once generated the syndrome contains theerror pattern that allows the error to be located and cor-rected -e syndrome is calculated using the formula

syndromer mod2 Cnminusbits lowastHTrtimesn1113872 1113873 (5)

-e mathematical expression in (5) is essentially madeup of AND and XOR gates -e gategraphical expression isillustrated in Figure 6

27 Extended Hamming Code -e extended Hammingcode makes use of an additional parity bit -is extra bit isthe sum of all the codeword bits (Figure 7) which in-creases the Hamming code capabilities to SECDED -eextended Hamming code can be done in both systematicand nonsystematic forms Table 5 shows this in a graphicalmanner

P16 in this case is the added parity bit that allows doubleerror detection Bymonitoring this bit and checking whetherthe bit is odd or even allows the double bit error to bedetected which is shown in Table 5 by bold

3 Hamming [16 11 4]2

Hamming [16 11 4]2 is an extended version of Hammingcode With an additional parity bit the code is capable ofdouble error detection (DED) -is code was implementedin a nonsystematic manner which simplifies the detection ofdouble errors-e construction of the generated codeword isshown in Table 6 Using general formulas some perfor-mance aspect of the Hamming [16 11 4]2 can be calculated(Table 7)-is clearly proves that Hamming [16 11 4]2 has abetter code rate and bit overhead than Hamming [8 4 4]2with capabilities of SECSED

In order to implement the Hamming [16 11 4]2 agenerator matrix (G) and parity-check matrix (H) areneeded for the encoding decoding and the calculation of thesyndrome (S) -e following calculations were done in orderto implement the code

Submatrix (P) of 11 times 4 dimensions is shown as

P11times4

1 1 0 0

0 1 1 0

0 0 1 1

1 1 0 1

1 0 1 0

0 1 0 1

1 1 1 0

0 1 1 1

1 1 1 1

1 0 1 1

1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(6)

Identity matrix (I) of size 11 times 11 (7) is used whencalculating G

Iktimesk I11times11

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 0 0

0 0 0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(7)

Journal of Electrical and Computer Engineering 5

From (1) the generator matrix is calculated

G11times15 I11times11 P11times411138681113868111386811138681113960 1113961

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(8)

Following Hamming rules G should be of size k times n-erefore an additional column is needed to satisfy thiscondition for Hamming [16 11 4]2 An 8th parity column isadded to G -is is done by adding an odd or even parity bitto each row

Gktimesn G11times16

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(9)

By considering the nonsystematic Hamming bit layoutin Table 4 G calculated in (9) can be rearranged to form anonsystematic matrix G

G11times16

1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0

1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1

0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 1

0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1

1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(10)

Identity matrix (I) of size 4 times 4 is used to calculate HFrom (2) the parity-check matrix can be calculated Withthe additional parity bit the negative submatrix is not usedas the result is the same H is calculated in (11)

Message (k-bits)

Generator matrix (k times n)

AND gate amp

XOR gate Codeword (n-bits)

Figure 5 Gategraphical expression of hamming encoder formula

Codeword (n-bits)

Transposed parity-check matrix

(r times n)

AND gateamp

XOR gate Syndrome (r-bits)

Figure 6 Gategraphical expression of hamming decoder formula

P3

D2

P2

D1

P1

D4

D3

P4

Figure 7 Parity relationship to data extended Hamming (8 4)

6 Journal of Electrical and Computer Engineering

H4times15 PT11times4 I4times4

11138681113868111386811138681113960 11139614times15

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(11)

Hamming rules stateH should be of size r times n-ereforean additional column and row are needed to satisfy thiscondition for Hamming [16 11 4]2 Due to the fourth paritybit only being used for detection the entire row can be filledwith ones With a fourth row added an 8th parity column isadded toH -is is done by adding an oddeven parity bit toeach row

Hrtimesn H5times16

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(12)

By considering the nonsystematic Hamming bit layoutin Table 4 H calculated above can be rearranged to form anonsystematic matrix H

H5times16

1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1

0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1

0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0

0 0 0 1 1 1 0 0 1 0 1 1 1 1 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(13)

OnceG andH have been derived it is possible to encodeand decode the information data in a manner that is capable

of SECDED -e data is encoded using (4) -is wasimplemented in Matlab using mod-2 additions which areessentially exclusive-OR functions -e same equation wasused to encode the information data in VHDL howeverexclusive-OR gates where used to perform the operation

Hamming [16 11 4]2 makes use of syndrome decodingto locate and correct any errors that occurred in thecodeword during transmission or storage -e syndrome iscalculated according to (5) A for-loop or case statement canthen be used to locate the bit which is flipped within thecodeword Once located the bit is simply inverted returningit back to its original and correct state With the codewordnow error-free the information bits are separated andextracted returning an error-free 11-bit message to thereceiver

4 Implementation

Hamming code was implemented in both Matlab andVHDL -e approach taken to achieve the desired results isexplained with the help of detailed flow charts

41 Matlab For each variation of the Hamming codes aproof of concept model was designed in Matlab -e ap-proach is outlined in Figure 8

42 VHDL Once proof of concept was established usingMatlab Quartus was used to implement the working VHDLmodel -e Hamming code was programmed using VHDLas it allows the behaviour of the required system to bemodelled and simulated -is is a major advantage whenoptimization is required A working model of Hamming [84 4]2 and Hamming [16 11 4]2 was programmed in VHLDusing the approached detailed in Figure 9

5 VHDL Optimization of Hamming [16 11 4]2

In this section the optimization of Hamming [16 11 4]2 isdone -e aim of optimization is to reduce resource usagesreduce time delays improve efficiency etc

Table 5 Bit layout of extended Hamming code (16 11)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

Table 6 Construction of the Hamming [16 11 4] codeword

Codeword (n 16)Information data (k 11) Parity (r 5)

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 P1 P2 P3 P4 P5

Table 7 Calculated performance aspects of Hamming [16 11 4]

Scheme Ed Ec Code rate () Bit overhead ()Hamming [16 11 4]2 2 1 6875 4545

Journal of Electrical and Computer Engineering 7

51 Code Optimization -ere are many ways of optimizingVHDL code Some of the main topics when it comes tooptimization are [13]

(i) Efficient adder implementation(ii) State machines(iii) Signal selection(iv) Storage structure(v) Placement and Routing

In this paper the Quartus Prime package is used to codeanalyse compile and optimize the Hamming code

52 Register Transfer Level (RTL) Viewer of Hamming [16 114]2 Using the RTL viewer provided under tools inQuartus Prime an overview of the IO and VHDL codelayout can be seen in Figure 10 -e overview displays theinput and outputs as well as the components defined inhamming_11_16_mainvhd

Decoder

Forloop

If statement

Use syndrome decodingSyndrome = mod-2 (codeword lowast Hprime)

Run for the full length of codeword

Check for any errors by generating a ldquosearch syndromerdquo for each position in codeword

If statement Compares syndrome and ldquosearch syndromerdquo When equal the error is found and the program

exits the loop

Input

Define all parameters(i) Message bits (k)

(ii) Parity bits (r)(iii) Codeword bits (n)(iv) Generator matrix (G)(v) Parity-check matrix (H)

Start a new Matlab scripted file (m)

Input message (msg)

Use hammgen toolbox to generate and check

parameters

OutputInvert the bit at the found location

Extract message bits from codeword and print to screen location of error and the error free message

Error injector

Simply invert or flip the selected bit or bits

User-injected error

Encoder

Generate parity bits for msg

Generate codewordCodeword = mod-2 (msg lowast G)

Figure 8 Overview of Matlab code (flow chart)

8 Journal of Electrical and Computer Engineering

Using the RTL viewer tool it is possible to step into boththe encoder and decoder -e RTL viewer optimizes thenetlist in order to maximize readability -is allows a uniqueinsight into each VHDL code -e RTL view of the encoderand decoder is shown in Figures 11 and 12

53 Optimization of Hamming [16 11 4]2 -e followingsteps are taken to optimize the code

(i) Remove unnecessary and redundant code(ii) Reduce constants and variables where possible

MainVHD

Open a new VHDL file (vhd) in Quartus

IF statement

Else if

Checks for errors using syndrome

Checks for double bit errors using the added parity bit or syndrome (3)

Elsendashcase statement Searches syndrome value When equal the error is found and the identified bit is flip to

original state

Error injector

DecoderVHD

Input

EncoderVHD

Output

Define all variables(i) Data in (input msg-k)

(ii) Data out (output msg-k)(iii) No error (NE)(iv) Double error detected(DED)(v) Single error correction (SEC)

Input data (msg)

EncodervhdDecodervhd

ModelSim User-injected error

Simply invert or flip the selected bit or bits

Define generator matrix and signals

Generate codewordCodeword = mod-2 (msg lowast G)

Define all components

Call and port map components

Msg lowast G =gt AND Gate

Mod-2 =gt XOR Gate

Return an error free msg or raisean error flag

Output the following variables(i)

(ii)(iii)(iv)

Data out (output msg-k)No error (NE)Double error detected(DED)Single error correction (SEC)

Extract message bits from codeword

Define parity-check matrix and signals

Use syndrome decodingSyndrome = mod-2 (Codeword lowast H)

Codeword lowast H =gt AND Gate

Mod-2 =gt XOR Gate

Figure 9 Overview of VHDL code (flow chart)

Journal of Electrical and Computer Engineering 9

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

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(vi) -is unique parity bit combination is known as thesyndrome value

22 Construction of GeneratorMatrix (G) Generator matrix(G) is used when encoding the information data to form thecodeword G forms one of the foundations on which theHamming code is based Due to the relationship between thegenerator matrix and parity-check matrix the Hammingcode is capable of SECSED

G(ktimesn) is defined as the combination of an identity matrix(I) of size k times k and a submatrix (P) of size k times r [12]

Gktimesn Iktimesk Pktimesr

11138681113868111386811138681113960 1113961 (1)

23 Construction of Parity-Check Matrix (H) Parity-checkmatrix (H) is used when decoding and correcting thecodeword in order to extract an error-free messageH formsone of the foundations on which the Hamming code is

Output

(i) Extracts information datafromerror-free codeword(k-bits long)

(ii) No errors

Decoder

(i) Uses a parity-check matrix to calculate the syndrome

(ii) Locates and correct any errors

(iii) Codeword of n-bits long

(iii) All errors corrected

Storage

(i) Errors due to space radation

(ii) Error in the form of SEU DEU and MEU

Encoder

(i) Uses a generator matrix to calculate the Hamming codeword

(ii) Codeword of n-bits long

(iii) No error

Input

(i) Information data (k-bits long)

(ii) No errors

Figure 3 General layout of Hamming code

Table 4 Bit layout of Hamming code (nonsystematic)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

-e syndrome allows errors to be located and corrected For example if parity bits P1 P4 and P8 show an error the location of the error can be found by1(P1) + 4(P4) + 8(P8) 13-erefore the error affected data bit 9 (D9) in position 13 shown in bold-e above explanation shows the general algorithm usedwhen implementing Hamming code

P3

D2

P2

D1

P1

D4

D3

(a)

P1

P2 P3

P4D1 D8D3

D11

D5

D2 D6

D4 D10

D9 D7

(b)

Figure 4 Parity vs data Hamming (7 3) (a) and Hamming (15 11) (b)

4 Journal of Electrical and Computer Engineering

based Due to the relationship between the parity-checkmatrix and generator matrix the Hamming code is capa-ble of SECSEC

H(rtimesn)is defined as the combination of a negativetransposed submatrix (P) of size k times r and an identity matrix(I) of size r times r [12]

Hrtimesn minusPTktimesr Irtimesr

11138681113868111386811138681113960 1113961 (2)

24 -e Relationship between G and H -e relationshipbetween G and H is shown as

GlowastHT 0 (3)

As a final note on G and H it is possible to manipulatethis matrix from systematic to an equivalent nonsystematicmatrix by using elementary matrix operations which are thefollowing

(i) Interchange two rows (or columns)(ii) Multiply each element in a row (or column) by a

nonzero number(iii) Multiply a row (or column) by a nonzero number

and add the result to another row (or column)

25 Hamming Encoder -e Hamming encoder is re-sponsible for generating the codeword (n-bits long) from themessage denoted by (M) and generator matrix (G) Oncegenerated the codeword contains both the message andparity bits -e codeword is calculated using the formula

codewordnminusbits mod2 Mkminusbits lowastGktimesn( 1113857 (4)

-e mathematical expression in (4) is essentially madeup of AND and XOR gates -e gategraphical expression isillustrated in (Figure 5)

26 Hamming Decoder -e Hamming decoder is re-sponsible for generating the syndrome (r-bits long) from thecodeword (n-bits long) denoted by C and parity-checkmatrix (H) Once generated the syndrome contains theerror pattern that allows the error to be located and cor-rected -e syndrome is calculated using the formula

syndromer mod2 Cnminusbits lowastHTrtimesn1113872 1113873 (5)

-e mathematical expression in (5) is essentially madeup of AND and XOR gates -e gategraphical expression isillustrated in Figure 6

27 Extended Hamming Code -e extended Hammingcode makes use of an additional parity bit -is extra bit isthe sum of all the codeword bits (Figure 7) which in-creases the Hamming code capabilities to SECDED -eextended Hamming code can be done in both systematicand nonsystematic forms Table 5 shows this in a graphicalmanner

P16 in this case is the added parity bit that allows doubleerror detection Bymonitoring this bit and checking whetherthe bit is odd or even allows the double bit error to bedetected which is shown in Table 5 by bold

3 Hamming [16 11 4]2

Hamming [16 11 4]2 is an extended version of Hammingcode With an additional parity bit the code is capable ofdouble error detection (DED) -is code was implementedin a nonsystematic manner which simplifies the detection ofdouble errors-e construction of the generated codeword isshown in Table 6 Using general formulas some perfor-mance aspect of the Hamming [16 11 4]2 can be calculated(Table 7)-is clearly proves that Hamming [16 11 4]2 has abetter code rate and bit overhead than Hamming [8 4 4]2with capabilities of SECSED

In order to implement the Hamming [16 11 4]2 agenerator matrix (G) and parity-check matrix (H) areneeded for the encoding decoding and the calculation of thesyndrome (S) -e following calculations were done in orderto implement the code

Submatrix (P) of 11 times 4 dimensions is shown as

P11times4

1 1 0 0

0 1 1 0

0 0 1 1

1 1 0 1

1 0 1 0

0 1 0 1

1 1 1 0

0 1 1 1

1 1 1 1

1 0 1 1

1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(6)

Identity matrix (I) of size 11 times 11 (7) is used whencalculating G

Iktimesk I11times11

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 0 0

0 0 0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(7)

Journal of Electrical and Computer Engineering 5

From (1) the generator matrix is calculated

G11times15 I11times11 P11times411138681113868111386811138681113960 1113961

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(8)

Following Hamming rules G should be of size k times n-erefore an additional column is needed to satisfy thiscondition for Hamming [16 11 4]2 An 8th parity column isadded to G -is is done by adding an odd or even parity bitto each row

Gktimesn G11times16

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(9)

By considering the nonsystematic Hamming bit layoutin Table 4 G calculated in (9) can be rearranged to form anonsystematic matrix G

G11times16

1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0

1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1

0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 1

0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1

1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(10)

Identity matrix (I) of size 4 times 4 is used to calculate HFrom (2) the parity-check matrix can be calculated Withthe additional parity bit the negative submatrix is not usedas the result is the same H is calculated in (11)

Message (k-bits)

Generator matrix (k times n)

AND gate amp

XOR gate Codeword (n-bits)

Figure 5 Gategraphical expression of hamming encoder formula

Codeword (n-bits)

Transposed parity-check matrix

(r times n)

AND gateamp

XOR gate Syndrome (r-bits)

Figure 6 Gategraphical expression of hamming decoder formula

P3

D2

P2

D1

P1

D4

D3

P4

Figure 7 Parity relationship to data extended Hamming (8 4)

6 Journal of Electrical and Computer Engineering

H4times15 PT11times4 I4times4

11138681113868111386811138681113960 11139614times15

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(11)

Hamming rules stateH should be of size r times n-ereforean additional column and row are needed to satisfy thiscondition for Hamming [16 11 4]2 Due to the fourth paritybit only being used for detection the entire row can be filledwith ones With a fourth row added an 8th parity column isadded toH -is is done by adding an oddeven parity bit toeach row

Hrtimesn H5times16

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(12)

By considering the nonsystematic Hamming bit layoutin Table 4 H calculated above can be rearranged to form anonsystematic matrix H

H5times16

1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1

0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1

0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0

0 0 0 1 1 1 0 0 1 0 1 1 1 1 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(13)

OnceG andH have been derived it is possible to encodeand decode the information data in a manner that is capable

of SECDED -e data is encoded using (4) -is wasimplemented in Matlab using mod-2 additions which areessentially exclusive-OR functions -e same equation wasused to encode the information data in VHDL howeverexclusive-OR gates where used to perform the operation

Hamming [16 11 4]2 makes use of syndrome decodingto locate and correct any errors that occurred in thecodeword during transmission or storage -e syndrome iscalculated according to (5) A for-loop or case statement canthen be used to locate the bit which is flipped within thecodeword Once located the bit is simply inverted returningit back to its original and correct state With the codewordnow error-free the information bits are separated andextracted returning an error-free 11-bit message to thereceiver

4 Implementation

Hamming code was implemented in both Matlab andVHDL -e approach taken to achieve the desired results isexplained with the help of detailed flow charts

41 Matlab For each variation of the Hamming codes aproof of concept model was designed in Matlab -e ap-proach is outlined in Figure 8

42 VHDL Once proof of concept was established usingMatlab Quartus was used to implement the working VHDLmodel -e Hamming code was programmed using VHDLas it allows the behaviour of the required system to bemodelled and simulated -is is a major advantage whenoptimization is required A working model of Hamming [84 4]2 and Hamming [16 11 4]2 was programmed in VHLDusing the approached detailed in Figure 9

5 VHDL Optimization of Hamming [16 11 4]2

In this section the optimization of Hamming [16 11 4]2 isdone -e aim of optimization is to reduce resource usagesreduce time delays improve efficiency etc

Table 5 Bit layout of extended Hamming code (16 11)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

Table 6 Construction of the Hamming [16 11 4] codeword

Codeword (n 16)Information data (k 11) Parity (r 5)

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 P1 P2 P3 P4 P5

Table 7 Calculated performance aspects of Hamming [16 11 4]

Scheme Ed Ec Code rate () Bit overhead ()Hamming [16 11 4]2 2 1 6875 4545

Journal of Electrical and Computer Engineering 7

51 Code Optimization -ere are many ways of optimizingVHDL code Some of the main topics when it comes tooptimization are [13]

(i) Efficient adder implementation(ii) State machines(iii) Signal selection(iv) Storage structure(v) Placement and Routing

In this paper the Quartus Prime package is used to codeanalyse compile and optimize the Hamming code

52 Register Transfer Level (RTL) Viewer of Hamming [16 114]2 Using the RTL viewer provided under tools inQuartus Prime an overview of the IO and VHDL codelayout can be seen in Figure 10 -e overview displays theinput and outputs as well as the components defined inhamming_11_16_mainvhd

Decoder

Forloop

If statement

Use syndrome decodingSyndrome = mod-2 (codeword lowast Hprime)

Run for the full length of codeword

Check for any errors by generating a ldquosearch syndromerdquo for each position in codeword

If statement Compares syndrome and ldquosearch syndromerdquo When equal the error is found and the program

exits the loop

Input

Define all parameters(i) Message bits (k)

(ii) Parity bits (r)(iii) Codeword bits (n)(iv) Generator matrix (G)(v) Parity-check matrix (H)

Start a new Matlab scripted file (m)

Input message (msg)

Use hammgen toolbox to generate and check

parameters

OutputInvert the bit at the found location

Extract message bits from codeword and print to screen location of error and the error free message

Error injector

Simply invert or flip the selected bit or bits

User-injected error

Encoder

Generate parity bits for msg

Generate codewordCodeword = mod-2 (msg lowast G)

Figure 8 Overview of Matlab code (flow chart)

8 Journal of Electrical and Computer Engineering

Using the RTL viewer tool it is possible to step into boththe encoder and decoder -e RTL viewer optimizes thenetlist in order to maximize readability -is allows a uniqueinsight into each VHDL code -e RTL view of the encoderand decoder is shown in Figures 11 and 12

53 Optimization of Hamming [16 11 4]2 -e followingsteps are taken to optimize the code

(i) Remove unnecessary and redundant code(ii) Reduce constants and variables where possible

MainVHD

Open a new VHDL file (vhd) in Quartus

IF statement

Else if

Checks for errors using syndrome

Checks for double bit errors using the added parity bit or syndrome (3)

Elsendashcase statement Searches syndrome value When equal the error is found and the identified bit is flip to

original state

Error injector

DecoderVHD

Input

EncoderVHD

Output

Define all variables(i) Data in (input msg-k)

(ii) Data out (output msg-k)(iii) No error (NE)(iv) Double error detected(DED)(v) Single error correction (SEC)

Input data (msg)

EncodervhdDecodervhd

ModelSim User-injected error

Simply invert or flip the selected bit or bits

Define generator matrix and signals

Generate codewordCodeword = mod-2 (msg lowast G)

Define all components

Call and port map components

Msg lowast G =gt AND Gate

Mod-2 =gt XOR Gate

Return an error free msg or raisean error flag

Output the following variables(i)

(ii)(iii)(iv)

Data out (output msg-k)No error (NE)Double error detected(DED)Single error correction (SEC)

Extract message bits from codeword

Define parity-check matrix and signals

Use syndrome decodingSyndrome = mod-2 (Codeword lowast H)

Codeword lowast H =gt AND Gate

Mod-2 =gt XOR Gate

Figure 9 Overview of VHDL code (flow chart)

Journal of Electrical and Computer Engineering 9

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

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based Due to the relationship between the parity-checkmatrix and generator matrix the Hamming code is capa-ble of SECSEC

H(rtimesn)is defined as the combination of a negativetransposed submatrix (P) of size k times r and an identity matrix(I) of size r times r [12]

Hrtimesn minusPTktimesr Irtimesr

11138681113868111386811138681113960 1113961 (2)

24 -e Relationship between G and H -e relationshipbetween G and H is shown as

GlowastHT 0 (3)

As a final note on G and H it is possible to manipulatethis matrix from systematic to an equivalent nonsystematicmatrix by using elementary matrix operations which are thefollowing

(i) Interchange two rows (or columns)(ii) Multiply each element in a row (or column) by a

nonzero number(iii) Multiply a row (or column) by a nonzero number

and add the result to another row (or column)

25 Hamming Encoder -e Hamming encoder is re-sponsible for generating the codeword (n-bits long) from themessage denoted by (M) and generator matrix (G) Oncegenerated the codeword contains both the message andparity bits -e codeword is calculated using the formula

codewordnminusbits mod2 Mkminusbits lowastGktimesn( 1113857 (4)

-e mathematical expression in (4) is essentially madeup of AND and XOR gates -e gategraphical expression isillustrated in (Figure 5)

26 Hamming Decoder -e Hamming decoder is re-sponsible for generating the syndrome (r-bits long) from thecodeword (n-bits long) denoted by C and parity-checkmatrix (H) Once generated the syndrome contains theerror pattern that allows the error to be located and cor-rected -e syndrome is calculated using the formula

syndromer mod2 Cnminusbits lowastHTrtimesn1113872 1113873 (5)

-e mathematical expression in (5) is essentially madeup of AND and XOR gates -e gategraphical expression isillustrated in Figure 6

27 Extended Hamming Code -e extended Hammingcode makes use of an additional parity bit -is extra bit isthe sum of all the codeword bits (Figure 7) which in-creases the Hamming code capabilities to SECDED -eextended Hamming code can be done in both systematicand nonsystematic forms Table 5 shows this in a graphicalmanner

P16 in this case is the added parity bit that allows doubleerror detection Bymonitoring this bit and checking whetherthe bit is odd or even allows the double bit error to bedetected which is shown in Table 5 by bold

3 Hamming [16 11 4]2

Hamming [16 11 4]2 is an extended version of Hammingcode With an additional parity bit the code is capable ofdouble error detection (DED) -is code was implementedin a nonsystematic manner which simplifies the detection ofdouble errors-e construction of the generated codeword isshown in Table 6 Using general formulas some perfor-mance aspect of the Hamming [16 11 4]2 can be calculated(Table 7)-is clearly proves that Hamming [16 11 4]2 has abetter code rate and bit overhead than Hamming [8 4 4]2with capabilities of SECSED

In order to implement the Hamming [16 11 4]2 agenerator matrix (G) and parity-check matrix (H) areneeded for the encoding decoding and the calculation of thesyndrome (S) -e following calculations were done in orderto implement the code

Submatrix (P) of 11 times 4 dimensions is shown as

P11times4

1 1 0 0

0 1 1 0

0 0 1 1

1 1 0 1

1 0 1 0

0 1 0 1

1 1 1 0

0 1 1 1

1 1 1 1

1 0 1 1

1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(6)

Identity matrix (I) of size 11 times 11 (7) is used whencalculating G

Iktimesk I11times11

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0 0 0 0

0 0 0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 0

0 0 0 0 0 0 0 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(7)

Journal of Electrical and Computer Engineering 5

From (1) the generator matrix is calculated

G11times15 I11times11 P11times411138681113868111386811138681113960 1113961

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(8)

Following Hamming rules G should be of size k times n-erefore an additional column is needed to satisfy thiscondition for Hamming [16 11 4]2 An 8th parity column isadded to G -is is done by adding an odd or even parity bitto each row

Gktimesn G11times16

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(9)

By considering the nonsystematic Hamming bit layoutin Table 4 G calculated in (9) can be rearranged to form anonsystematic matrix G

G11times16

1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0

1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1

0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 1

0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1

1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(10)

Identity matrix (I) of size 4 times 4 is used to calculate HFrom (2) the parity-check matrix can be calculated Withthe additional parity bit the negative submatrix is not usedas the result is the same H is calculated in (11)

Message (k-bits)

Generator matrix (k times n)

AND gate amp

XOR gate Codeword (n-bits)

Figure 5 Gategraphical expression of hamming encoder formula

Codeword (n-bits)

Transposed parity-check matrix

(r times n)

AND gateamp

XOR gate Syndrome (r-bits)

Figure 6 Gategraphical expression of hamming decoder formula

P3

D2

P2

D1

P1

D4

D3

P4

Figure 7 Parity relationship to data extended Hamming (8 4)

6 Journal of Electrical and Computer Engineering

H4times15 PT11times4 I4times4

11138681113868111386811138681113960 11139614times15

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(11)

Hamming rules stateH should be of size r times n-ereforean additional column and row are needed to satisfy thiscondition for Hamming [16 11 4]2 Due to the fourth paritybit only being used for detection the entire row can be filledwith ones With a fourth row added an 8th parity column isadded toH -is is done by adding an oddeven parity bit toeach row

Hrtimesn H5times16

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(12)

By considering the nonsystematic Hamming bit layoutin Table 4 H calculated above can be rearranged to form anonsystematic matrix H

H5times16

1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1

0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1

0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0

0 0 0 1 1 1 0 0 1 0 1 1 1 1 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(13)

OnceG andH have been derived it is possible to encodeand decode the information data in a manner that is capable

of SECDED -e data is encoded using (4) -is wasimplemented in Matlab using mod-2 additions which areessentially exclusive-OR functions -e same equation wasused to encode the information data in VHDL howeverexclusive-OR gates where used to perform the operation

Hamming [16 11 4]2 makes use of syndrome decodingto locate and correct any errors that occurred in thecodeword during transmission or storage -e syndrome iscalculated according to (5) A for-loop or case statement canthen be used to locate the bit which is flipped within thecodeword Once located the bit is simply inverted returningit back to its original and correct state With the codewordnow error-free the information bits are separated andextracted returning an error-free 11-bit message to thereceiver

4 Implementation

Hamming code was implemented in both Matlab andVHDL -e approach taken to achieve the desired results isexplained with the help of detailed flow charts

41 Matlab For each variation of the Hamming codes aproof of concept model was designed in Matlab -e ap-proach is outlined in Figure 8

42 VHDL Once proof of concept was established usingMatlab Quartus was used to implement the working VHDLmodel -e Hamming code was programmed using VHDLas it allows the behaviour of the required system to bemodelled and simulated -is is a major advantage whenoptimization is required A working model of Hamming [84 4]2 and Hamming [16 11 4]2 was programmed in VHLDusing the approached detailed in Figure 9

5 VHDL Optimization of Hamming [16 11 4]2

In this section the optimization of Hamming [16 11 4]2 isdone -e aim of optimization is to reduce resource usagesreduce time delays improve efficiency etc

Table 5 Bit layout of extended Hamming code (16 11)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

Table 6 Construction of the Hamming [16 11 4] codeword

Codeword (n 16)Information data (k 11) Parity (r 5)

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 P1 P2 P3 P4 P5

Table 7 Calculated performance aspects of Hamming [16 11 4]

Scheme Ed Ec Code rate () Bit overhead ()Hamming [16 11 4]2 2 1 6875 4545

Journal of Electrical and Computer Engineering 7

51 Code Optimization -ere are many ways of optimizingVHDL code Some of the main topics when it comes tooptimization are [13]

(i) Efficient adder implementation(ii) State machines(iii) Signal selection(iv) Storage structure(v) Placement and Routing

In this paper the Quartus Prime package is used to codeanalyse compile and optimize the Hamming code

52 Register Transfer Level (RTL) Viewer of Hamming [16 114]2 Using the RTL viewer provided under tools inQuartus Prime an overview of the IO and VHDL codelayout can be seen in Figure 10 -e overview displays theinput and outputs as well as the components defined inhamming_11_16_mainvhd

Decoder

Forloop

If statement

Use syndrome decodingSyndrome = mod-2 (codeword lowast Hprime)

Run for the full length of codeword

Check for any errors by generating a ldquosearch syndromerdquo for each position in codeword

If statement Compares syndrome and ldquosearch syndromerdquo When equal the error is found and the program

exits the loop

Input

Define all parameters(i) Message bits (k)

(ii) Parity bits (r)(iii) Codeword bits (n)(iv) Generator matrix (G)(v) Parity-check matrix (H)

Start a new Matlab scripted file (m)

Input message (msg)

Use hammgen toolbox to generate and check

parameters

OutputInvert the bit at the found location

Extract message bits from codeword and print to screen location of error and the error free message

Error injector

Simply invert or flip the selected bit or bits

User-injected error

Encoder

Generate parity bits for msg

Generate codewordCodeword = mod-2 (msg lowast G)

Figure 8 Overview of Matlab code (flow chart)

8 Journal of Electrical and Computer Engineering

Using the RTL viewer tool it is possible to step into boththe encoder and decoder -e RTL viewer optimizes thenetlist in order to maximize readability -is allows a uniqueinsight into each VHDL code -e RTL view of the encoderand decoder is shown in Figures 11 and 12

53 Optimization of Hamming [16 11 4]2 -e followingsteps are taken to optimize the code

(i) Remove unnecessary and redundant code(ii) Reduce constants and variables where possible

MainVHD

Open a new VHDL file (vhd) in Quartus

IF statement

Else if

Checks for errors using syndrome

Checks for double bit errors using the added parity bit or syndrome (3)

Elsendashcase statement Searches syndrome value When equal the error is found and the identified bit is flip to

original state

Error injector

DecoderVHD

Input

EncoderVHD

Output

Define all variables(i) Data in (input msg-k)

(ii) Data out (output msg-k)(iii) No error (NE)(iv) Double error detected(DED)(v) Single error correction (SEC)

Input data (msg)

EncodervhdDecodervhd

ModelSim User-injected error

Simply invert or flip the selected bit or bits

Define generator matrix and signals

Generate codewordCodeword = mod-2 (msg lowast G)

Define all components

Call and port map components

Msg lowast G =gt AND Gate

Mod-2 =gt XOR Gate

Return an error free msg or raisean error flag

Output the following variables(i)

(ii)(iii)(iv)

Data out (output msg-k)No error (NE)Double error detected(DED)Single error correction (SEC)

Extract message bits from codeword

Define parity-check matrix and signals

Use syndrome decodingSyndrome = mod-2 (Codeword lowast H)

Codeword lowast H =gt AND Gate

Mod-2 =gt XOR Gate

Figure 9 Overview of VHDL code (flow chart)

Journal of Electrical and Computer Engineering 9

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

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From (1) the generator matrix is calculated

G11times15 I11times11 P11times411138681113868111386811138681113960 1113961

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(8)

Following Hamming rules G should be of size k times n-erefore an additional column is needed to satisfy thiscondition for Hamming [16 11 4]2 An 8th parity column isadded to G -is is done by adding an odd or even parity bitto each row

Gktimesn G11times16

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1

0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1

0 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0

0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 1

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0

0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1

0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 0

0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(9)

By considering the nonsystematic Hamming bit layoutin Table 4 G calculated in (9) can be rearranged to form anonsystematic matrix G

G11times16

1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0

1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0

1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1

1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1

0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0

0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1

1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 1

0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1

1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(10)

Identity matrix (I) of size 4 times 4 is used to calculate HFrom (2) the parity-check matrix can be calculated Withthe additional parity bit the negative submatrix is not usedas the result is the same H is calculated in (11)

Message (k-bits)

Generator matrix (k times n)

AND gate amp

XOR gate Codeword (n-bits)

Figure 5 Gategraphical expression of hamming encoder formula

Codeword (n-bits)

Transposed parity-check matrix

(r times n)

AND gateamp

XOR gate Syndrome (r-bits)

Figure 6 Gategraphical expression of hamming decoder formula

P3

D2

P2

D1

P1

D4

D3

P4

Figure 7 Parity relationship to data extended Hamming (8 4)

6 Journal of Electrical and Computer Engineering

H4times15 PT11times4 I4times4

11138681113868111386811138681113960 11139614times15

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(11)

Hamming rules stateH should be of size r times n-ereforean additional column and row are needed to satisfy thiscondition for Hamming [16 11 4]2 Due to the fourth paritybit only being used for detection the entire row can be filledwith ones With a fourth row added an 8th parity column isadded toH -is is done by adding an oddeven parity bit toeach row

Hrtimesn H5times16

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(12)

By considering the nonsystematic Hamming bit layoutin Table 4 H calculated above can be rearranged to form anonsystematic matrix H

H5times16

1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1

0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1

0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0

0 0 0 1 1 1 0 0 1 0 1 1 1 1 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(13)

OnceG andH have been derived it is possible to encodeand decode the information data in a manner that is capable

of SECDED -e data is encoded using (4) -is wasimplemented in Matlab using mod-2 additions which areessentially exclusive-OR functions -e same equation wasused to encode the information data in VHDL howeverexclusive-OR gates where used to perform the operation

Hamming [16 11 4]2 makes use of syndrome decodingto locate and correct any errors that occurred in thecodeword during transmission or storage -e syndrome iscalculated according to (5) A for-loop or case statement canthen be used to locate the bit which is flipped within thecodeword Once located the bit is simply inverted returningit back to its original and correct state With the codewordnow error-free the information bits are separated andextracted returning an error-free 11-bit message to thereceiver

4 Implementation

Hamming code was implemented in both Matlab andVHDL -e approach taken to achieve the desired results isexplained with the help of detailed flow charts

41 Matlab For each variation of the Hamming codes aproof of concept model was designed in Matlab -e ap-proach is outlined in Figure 8

42 VHDL Once proof of concept was established usingMatlab Quartus was used to implement the working VHDLmodel -e Hamming code was programmed using VHDLas it allows the behaviour of the required system to bemodelled and simulated -is is a major advantage whenoptimization is required A working model of Hamming [84 4]2 and Hamming [16 11 4]2 was programmed in VHLDusing the approached detailed in Figure 9

5 VHDL Optimization of Hamming [16 11 4]2

In this section the optimization of Hamming [16 11 4]2 isdone -e aim of optimization is to reduce resource usagesreduce time delays improve efficiency etc

Table 5 Bit layout of extended Hamming code (16 11)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

Table 6 Construction of the Hamming [16 11 4] codeword

Codeword (n 16)Information data (k 11) Parity (r 5)

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 P1 P2 P3 P4 P5

Table 7 Calculated performance aspects of Hamming [16 11 4]

Scheme Ed Ec Code rate () Bit overhead ()Hamming [16 11 4]2 2 1 6875 4545

Journal of Electrical and Computer Engineering 7

51 Code Optimization -ere are many ways of optimizingVHDL code Some of the main topics when it comes tooptimization are [13]

(i) Efficient adder implementation(ii) State machines(iii) Signal selection(iv) Storage structure(v) Placement and Routing

In this paper the Quartus Prime package is used to codeanalyse compile and optimize the Hamming code

52 Register Transfer Level (RTL) Viewer of Hamming [16 114]2 Using the RTL viewer provided under tools inQuartus Prime an overview of the IO and VHDL codelayout can be seen in Figure 10 -e overview displays theinput and outputs as well as the components defined inhamming_11_16_mainvhd

Decoder

Forloop

If statement

Use syndrome decodingSyndrome = mod-2 (codeword lowast Hprime)

Run for the full length of codeword

Check for any errors by generating a ldquosearch syndromerdquo for each position in codeword

If statement Compares syndrome and ldquosearch syndromerdquo When equal the error is found and the program

exits the loop

Input

Define all parameters(i) Message bits (k)

(ii) Parity bits (r)(iii) Codeword bits (n)(iv) Generator matrix (G)(v) Parity-check matrix (H)

Start a new Matlab scripted file (m)

Input message (msg)

Use hammgen toolbox to generate and check

parameters

OutputInvert the bit at the found location

Extract message bits from codeword and print to screen location of error and the error free message

Error injector

Simply invert or flip the selected bit or bits

User-injected error

Encoder

Generate parity bits for msg

Generate codewordCodeword = mod-2 (msg lowast G)

Figure 8 Overview of Matlab code (flow chart)

8 Journal of Electrical and Computer Engineering

Using the RTL viewer tool it is possible to step into boththe encoder and decoder -e RTL viewer optimizes thenetlist in order to maximize readability -is allows a uniqueinsight into each VHDL code -e RTL view of the encoderand decoder is shown in Figures 11 and 12

53 Optimization of Hamming [16 11 4]2 -e followingsteps are taken to optimize the code

(i) Remove unnecessary and redundant code(ii) Reduce constants and variables where possible

MainVHD

Open a new VHDL file (vhd) in Quartus

IF statement

Else if

Checks for errors using syndrome

Checks for double bit errors using the added parity bit or syndrome (3)

Elsendashcase statement Searches syndrome value When equal the error is found and the identified bit is flip to

original state

Error injector

DecoderVHD

Input

EncoderVHD

Output

Define all variables(i) Data in (input msg-k)

(ii) Data out (output msg-k)(iii) No error (NE)(iv) Double error detected(DED)(v) Single error correction (SEC)

Input data (msg)

EncodervhdDecodervhd

ModelSim User-injected error

Simply invert or flip the selected bit or bits

Define generator matrix and signals

Generate codewordCodeword = mod-2 (msg lowast G)

Define all components

Call and port map components

Msg lowast G =gt AND Gate

Mod-2 =gt XOR Gate

Return an error free msg or raisean error flag

Output the following variables(i)

(ii)(iii)(iv)

Data out (output msg-k)No error (NE)Double error detected(DED)Single error correction (SEC)

Extract message bits from codeword

Define parity-check matrix and signals

Use syndrome decodingSyndrome = mod-2 (Codeword lowast H)

Codeword lowast H =gt AND Gate

Mod-2 =gt XOR Gate

Figure 9 Overview of VHDL code (flow chart)

Journal of Electrical and Computer Engineering 9

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

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H4times15 PT11times4 I4times4

11138681113868111386811138681113960 11139614times15

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(11)

Hamming rules stateH should be of size r times n-ereforean additional column and row are needed to satisfy thiscondition for Hamming [16 11 4]2 Due to the fourth paritybit only being used for detection the entire row can be filledwith ones With a fourth row added an 8th parity column isadded toH -is is done by adding an oddeven parity bit toeach row

Hrtimesn H5times16

1 0 0 1 1 0 1 0 1 1 1 1 0 0 0 0

1 1 0 1 0 1 1 1 1 0 0 0 1 0 0 0

0 1 1 0 1 0 1 1 1 1 0 0 0 1 0 0

0 0 1 1 0 1 0 1 1 1 1 0 0 0 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(12)

By considering the nonsystematic Hamming bit layoutin Table 4 H calculated above can be rearranged to form anonsystematic matrix H

H5times16

1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 1

0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1

0 0 1 0 1 0 1 1 0 1 1 1 1 0 0 0

0 0 0 1 1 1 0 0 1 0 1 1 1 1 0 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣

⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦

(13)

OnceG andH have been derived it is possible to encodeand decode the information data in a manner that is capable

of SECDED -e data is encoded using (4) -is wasimplemented in Matlab using mod-2 additions which areessentially exclusive-OR functions -e same equation wasused to encode the information data in VHDL howeverexclusive-OR gates where used to perform the operation

Hamming [16 11 4]2 makes use of syndrome decodingto locate and correct any errors that occurred in thecodeword during transmission or storage -e syndrome iscalculated according to (5) A for-loop or case statement canthen be used to locate the bit which is flipped within thecodeword Once located the bit is simply inverted returningit back to its original and correct state With the codewordnow error-free the information bits are separated andextracted returning an error-free 11-bit message to thereceiver

4 Implementation

Hamming code was implemented in both Matlab andVHDL -e approach taken to achieve the desired results isexplained with the help of detailed flow charts

41 Matlab For each variation of the Hamming codes aproof of concept model was designed in Matlab -e ap-proach is outlined in Figure 8

42 VHDL Once proof of concept was established usingMatlab Quartus was used to implement the working VHDLmodel -e Hamming code was programmed using VHDLas it allows the behaviour of the required system to bemodelled and simulated -is is a major advantage whenoptimization is required A working model of Hamming [84 4]2 and Hamming [16 11 4]2 was programmed in VHLDusing the approached detailed in Figure 9

5 VHDL Optimization of Hamming [16 11 4]2

In this section the optimization of Hamming [16 11 4]2 isdone -e aim of optimization is to reduce resource usagesreduce time delays improve efficiency etc

Table 5 Bit layout of extended Hamming code (16 11)

Bit position 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16Encoded data bits P1 P2 D1 P4 D2 D3 D4 P8 D5 D6 D7 D8 D9 D10 D11 P16

Encoded data coverage (nonsystematic)syndrome

P1 7 7 7 7 7 7 7 7

P2 7 7 7 7 7 7 7 7

P4 7 7 7 7 7 7 7 7

P8 7 7 7 7 7 7 7 7

P16 7

Table 6 Construction of the Hamming [16 11 4] codeword

Codeword (n 16)Information data (k 11) Parity (r 5)

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 P1 P2 P3 P4 P5

Table 7 Calculated performance aspects of Hamming [16 11 4]

Scheme Ed Ec Code rate () Bit overhead ()Hamming [16 11 4]2 2 1 6875 4545

Journal of Electrical and Computer Engineering 7

51 Code Optimization -ere are many ways of optimizingVHDL code Some of the main topics when it comes tooptimization are [13]

(i) Efficient adder implementation(ii) State machines(iii) Signal selection(iv) Storage structure(v) Placement and Routing

In this paper the Quartus Prime package is used to codeanalyse compile and optimize the Hamming code

52 Register Transfer Level (RTL) Viewer of Hamming [16 114]2 Using the RTL viewer provided under tools inQuartus Prime an overview of the IO and VHDL codelayout can be seen in Figure 10 -e overview displays theinput and outputs as well as the components defined inhamming_11_16_mainvhd

Decoder

Forloop

If statement

Use syndrome decodingSyndrome = mod-2 (codeword lowast Hprime)

Run for the full length of codeword

Check for any errors by generating a ldquosearch syndromerdquo for each position in codeword

If statement Compares syndrome and ldquosearch syndromerdquo When equal the error is found and the program

exits the loop

Input

Define all parameters(i) Message bits (k)

(ii) Parity bits (r)(iii) Codeword bits (n)(iv) Generator matrix (G)(v) Parity-check matrix (H)

Start a new Matlab scripted file (m)

Input message (msg)

Use hammgen toolbox to generate and check

parameters

OutputInvert the bit at the found location

Extract message bits from codeword and print to screen location of error and the error free message

Error injector

Simply invert or flip the selected bit or bits

User-injected error

Encoder

Generate parity bits for msg

Generate codewordCodeword = mod-2 (msg lowast G)

Figure 8 Overview of Matlab code (flow chart)

8 Journal of Electrical and Computer Engineering

Using the RTL viewer tool it is possible to step into boththe encoder and decoder -e RTL viewer optimizes thenetlist in order to maximize readability -is allows a uniqueinsight into each VHDL code -e RTL view of the encoderand decoder is shown in Figures 11 and 12

53 Optimization of Hamming [16 11 4]2 -e followingsteps are taken to optimize the code

(i) Remove unnecessary and redundant code(ii) Reduce constants and variables where possible

MainVHD

Open a new VHDL file (vhd) in Quartus

IF statement

Else if

Checks for errors using syndrome

Checks for double bit errors using the added parity bit or syndrome (3)

Elsendashcase statement Searches syndrome value When equal the error is found and the identified bit is flip to

original state

Error injector

DecoderVHD

Input

EncoderVHD

Output

Define all variables(i) Data in (input msg-k)

(ii) Data out (output msg-k)(iii) No error (NE)(iv) Double error detected(DED)(v) Single error correction (SEC)

Input data (msg)

EncodervhdDecodervhd

ModelSim User-injected error

Simply invert or flip the selected bit or bits

Define generator matrix and signals

Generate codewordCodeword = mod-2 (msg lowast G)

Define all components

Call and port map components

Msg lowast G =gt AND Gate

Mod-2 =gt XOR Gate

Return an error free msg or raisean error flag

Output the following variables(i)

(ii)(iii)(iv)

Data out (output msg-k)No error (NE)Double error detected(DED)Single error correction (SEC)

Extract message bits from codeword

Define parity-check matrix and signals

Use syndrome decodingSyndrome = mod-2 (Codeword lowast H)

Codeword lowast H =gt AND Gate

Mod-2 =gt XOR Gate

Figure 9 Overview of VHDL code (flow chart)

Journal of Electrical and Computer Engineering 9

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

51 Code Optimization -ere are many ways of optimizingVHDL code Some of the main topics when it comes tooptimization are [13]

(i) Efficient adder implementation(ii) State machines(iii) Signal selection(iv) Storage structure(v) Placement and Routing

In this paper the Quartus Prime package is used to codeanalyse compile and optimize the Hamming code

52 Register Transfer Level (RTL) Viewer of Hamming [16 114]2 Using the RTL viewer provided under tools inQuartus Prime an overview of the IO and VHDL codelayout can be seen in Figure 10 -e overview displays theinput and outputs as well as the components defined inhamming_11_16_mainvhd

Decoder

Forloop

If statement

Use syndrome decodingSyndrome = mod-2 (codeword lowast Hprime)

Run for the full length of codeword

Check for any errors by generating a ldquosearch syndromerdquo for each position in codeword

If statement Compares syndrome and ldquosearch syndromerdquo When equal the error is found and the program

exits the loop

Input

Define all parameters(i) Message bits (k)

(ii) Parity bits (r)(iii) Codeword bits (n)(iv) Generator matrix (G)(v) Parity-check matrix (H)

Start a new Matlab scripted file (m)

Input message (msg)

Use hammgen toolbox to generate and check

parameters

OutputInvert the bit at the found location

Extract message bits from codeword and print to screen location of error and the error free message

Error injector

Simply invert or flip the selected bit or bits

User-injected error

Encoder

Generate parity bits for msg

Generate codewordCodeword = mod-2 (msg lowast G)

Figure 8 Overview of Matlab code (flow chart)

8 Journal of Electrical and Computer Engineering

Using the RTL viewer tool it is possible to step into boththe encoder and decoder -e RTL viewer optimizes thenetlist in order to maximize readability -is allows a uniqueinsight into each VHDL code -e RTL view of the encoderand decoder is shown in Figures 11 and 12

53 Optimization of Hamming [16 11 4]2 -e followingsteps are taken to optimize the code

(i) Remove unnecessary and redundant code(ii) Reduce constants and variables where possible

MainVHD

Open a new VHDL file (vhd) in Quartus

IF statement

Else if

Checks for errors using syndrome

Checks for double bit errors using the added parity bit or syndrome (3)

Elsendashcase statement Searches syndrome value When equal the error is found and the identified bit is flip to

original state

Error injector

DecoderVHD

Input

EncoderVHD

Output

Define all variables(i) Data in (input msg-k)

(ii) Data out (output msg-k)(iii) No error (NE)(iv) Double error detected(DED)(v) Single error correction (SEC)

Input data (msg)

EncodervhdDecodervhd

ModelSim User-injected error

Simply invert or flip the selected bit or bits

Define generator matrix and signals

Generate codewordCodeword = mod-2 (msg lowast G)

Define all components

Call and port map components

Msg lowast G =gt AND Gate

Mod-2 =gt XOR Gate

Return an error free msg or raisean error flag

Output the following variables(i)

(ii)(iii)(iv)

Data out (output msg-k)No error (NE)Double error detected(DED)Single error correction (SEC)

Extract message bits from codeword

Define parity-check matrix and signals

Use syndrome decodingSyndrome = mod-2 (Codeword lowast H)

Codeword lowast H =gt AND Gate

Mod-2 =gt XOR Gate

Figure 9 Overview of VHDL code (flow chart)

Journal of Electrical and Computer Engineering 9

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

Using the RTL viewer tool it is possible to step into boththe encoder and decoder -e RTL viewer optimizes thenetlist in order to maximize readability -is allows a uniqueinsight into each VHDL code -e RTL view of the encoderand decoder is shown in Figures 11 and 12

53 Optimization of Hamming [16 11 4]2 -e followingsteps are taken to optimize the code

(i) Remove unnecessary and redundant code(ii) Reduce constants and variables where possible

MainVHD

Open a new VHDL file (vhd) in Quartus

IF statement

Else if

Checks for errors using syndrome

Checks for double bit errors using the added parity bit or syndrome (3)

Elsendashcase statement Searches syndrome value When equal the error is found and the identified bit is flip to

original state

Error injector

DecoderVHD

Input

EncoderVHD

Output

Define all variables(i) Data in (input msg-k)

(ii) Data out (output msg-k)(iii) No error (NE)(iv) Double error detected(DED)(v) Single error correction (SEC)

Input data (msg)

EncodervhdDecodervhd

ModelSim User-injected error

Simply invert or flip the selected bit or bits

Define generator matrix and signals

Generate codewordCodeword = mod-2 (msg lowast G)

Define all components

Call and port map components

Msg lowast G =gt AND Gate

Mod-2 =gt XOR Gate

Return an error free msg or raisean error flag

Output the following variables(i)

(ii)(iii)(iv)

Data out (output msg-k)No error (NE)Double error detected(DED)Single error correction (SEC)

Extract message bits from codeword

Define parity-check matrix and signals

Use syndrome decodingSyndrome = mod-2 (Codeword lowast H)

Codeword lowast H =gt AND Gate

Mod-2 =gt XOR Gate

Figure 9 Overview of VHDL code (flow chart)

Journal of Electrical and Computer Engineering 9

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

(iii) Minimize the use of if statements and loops(iv) Convert code to structural level or gate level

-e Hamming [16 11 4]2 was reduced to structure orgate level which resulted that all redundant codes IFstatements loops constants and variables were either re-moved or reduced By reducing the code to gate level thefollowing changes occurred

(i) Encoder contains no constants or variables(ii) Encoder went from performing 320 logic (AND and

XOR) bit operations to only 30 XOR operations(iii) Decoder contains no constants(iv) Decoder contains a reduced amount of variables(v) Decoder went from 2 IF statements to none and

from 1 case statement to none

-e results of reducingHamming [16 11 4]2 to gate levelis shown for the decoder using Figure 13

6 Testing and Simulations

Hamming codes have many communication and memoryapplications -ey are extremely popular for their effec-tiveness when it comes to correction of single-bit flips andthe detection of double-bit flips

Hamming [16 11 4]2 allows SECDED while providing abetter code rate and bit overhead than standard Hammingcodes Hamming [16 11 4]2 generates a codeword ofdouble-byte size which is convenient as most memoryblocks work on a byte standard -e code was implemented

in VHDL on both a behaviourdataflow and gate level(optimized) during implementation Hamming [16 11 4]2code was optimized from a resource reduction and timingapproach after which it was tested thoroughly using soft-ware techniques

61 Top-Level Requirements -e top-level design in Fig-ure 14 shows a proposed EDAC system -e i386 micro-controller communicates using 11 bits of data over theD-Bus -e data bits together with the 5 bits parity allow adouble-byte codeword to be stored in the RAM -is layoutensures that SEUs are detected and corrected duringmemory read and write cycles

62 Software Tests and Reports Using software the de-veloped Hamming code is tested and analysed -is is doneon three levels namely functionality (ModelSim) resourceusage (compilation report) and timing analysis (Time-Quest) An overview of the tested VHDL code is shown inFigure 15 Figure 15 shows the inputs and outputs (IO) IOregisters clocking circuit and the components that make upthe Hamming [16 11 4]2 code

63 Functionality Hamming [16 11 4]2 is capable of single-error correction and double-error detection With the helpof ModelSim this is clearly shown in Figure 16 IO registersare triggered using the rising edge of clk and can be clearedusing clr -is will allow synchronisation and enables theOBC to do a full EDAC reset if necessary Datain (input)dataout (output) and data_to_memory (stored codeword)display the data in the system while NE (no error) DED(double error detection) and SEC (signal error correction)serve as indication flags In Figure 16 the functionality ofHamming [16 11 4]2 is proven In Figure 16 the followingshould be noted

(i) All registers are cleared using the clear signal ldquoclrrdquo(this is shown using )

(ii) Single-bit errors are introduced in memory using abit flip in data_to_memory (bits 0 to 15) and flaggedby SEC (this is shown using )

(iii) Double-bit errors are introduced in memory usingbit flips in data_to_memory (bits 0 to 15) andflagged by DED (this is shown using )

(iv) Note thanks to Hamming [16 11 4] dataout isunaffected by single-bit errors and only gets clearedupon the detection of double-bit errors

Figure 11 RTL overview of the encoder for Hamming [16 11 4]2

Figure 10 IO overview of VHDL code for Hamming [16 11 4]2

10 Journal of Electrical and Computer Engineering

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

In this paper EDAC schemes are extensively discussedZA-cube 2 nanosatellite was used as a case study whenconducting research on space radiation error correctioncodes and Hamming code All findings results and rec-ommendations are concluded in the sections to follow

64 Findings Space radiation has caused numerous missionfailures -rough research it became apparent that failurescaused by SEU and MEU are extremely common and SEEsare more frequent while the nanosatellite is in the SAA Itwas found that there are a number of EDAC schemes andtechniques currently used most commonly Hamming RScodes and TMR -e EDAC schemes are usually imple-mented using an FPGA From the literature survey it is clearthat there is a need for research in the area of EDACs Byconducting an in-depth literature review it was establishedthat Hamming code was capable of performing the func-tionality desired

In order to understand space radiation a study wasconducted using the orbital parameters of nanosatellite ZA-Cube 2 -is radiation study was conducted using OMERE

and TRIM software which allows the simulation of earthradiation belts (ERBs) galactic cosmic radiation (GCR)solar particle events (SPE) and shielding In the case ofERBs protons of a maximum integral flux of 165 times

e3degcmminus2middotsminus1 flux at energy plusmn100KeV were trapped whichdecays to a minimum integral flux of 155 cmminus2 sminus1 flux atenergy plusmn300MeV It was found that the common nano-satellite casing of 2mm Al is only effective as a shield againstprotons below 20MeV and heavy ions below 30MeV Inorder to ensure that SEE does not occur additional miti-gation techniques are needed to protect sensitivevulnerabledevices -ese techniques could be triple modular re-dundancy (TMR) software EDAC schemes and others

-ere are two types of ECC namely error detectioncodes and error correction codes For protection againstradiation nanosatellites use error correction codes likeHamming Hadamard Repetition Four DimensionalParity Golay BCH and Reed Solomon codes Using de-tection capabilities correction capabilities code rate andbit overhead each EDAC scheme is evaluated -e eval-uation of Hamming codes is shown in Table 8 Nano-satellites in SSO LEO of around 550 km experience on

Figure 12 RTL overview of the decoder for Hamming [16 11 4]2

Journal of Electrical and Computer Engineering 11

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

Figure 13 RTL overview of the optimized decoder for Hamming [16 11 4]2

11 11 16OBC80C386

DBUS DBUS

Loca

l bus

FPGAndashEDAC

RAM

Hamming [16 11 4]2

Figure 14 Functional block diagram of Hamming [16 11 4]2

12 Journal of Electrical and Computer Engineering

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

average plusmn97 SEU bit flips per day with an average of 986of all errors being SEU Around 80 of all errors occurwithin the SAA region

Hamming codes are classified as error detection andcorrection codes that are forward error correction blockbinary codes -ese codes are based on the use of parity bitswhich allows EDAC using a generator matrix and a parity-check matrix Normal Hamming codes make use of asyndrome decoder which ultimately allows the error to belocated Once located the error is corrected to its originalstate -ree variations of Hamming was designed and testedduring the completion of this paper A short summary ofthese codes is shown in Table 9

Hamming [16 11 4]2 was then converted to gate leveland optimized from a resource approach and timingapproach -e results of the optimized code are shown inTable 10 With the Hamming code design being completehardware tests were considered -e international JEDECstandards are recommended when conducting a proton(JESD234) and heavy ion test (JESD57A) -ese standards

Figure 15 Full RTL overview of VHDL code for Hamming [16 11 4]2

Figure 16 ModelSim simulation of Hamming [16 11 4] SECDED capabilities

Table 8 Evaluation of Hamming code

Schemes(n k Dmin)

Ed EcCode

rate ()Bit

overhead ()Hamming7 4 3 1 1 5714 750015 11 3 1 1 7333 363631 26 3 1 1 8387 192363 57 3 1 1 9048 1053Extended hamming8 4 4 2 1 5000 1000016 11 4 2 1 6875 454564 58 4 2 1 9063 10341024 1017 4 2 1 9932 069

Journal of Electrical and Computer Engineering 13

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

ensure reliable and accurate test results iTemba lab inCape Town houses an accelerator capable of proton (upto 200MeV) and heavy ion testing In order to conductSEE tests at a facility like iTemba lab detailed and ex-tensive planning is necessary -is planning and actualtesting are done by both the ion beam operators andsatellite engineers -is ensures cost and time is kept to aminimal

7 Conclusion

In this paper a detailed look at different EDAC schemestogether with a code comparison study was conducted -isstudy provides the reader with a good understanding of allcommon EDAC schemes which is extremely useful shoulddifferent EDAC capabilities be needed

Hamming code was extensively studied and imple-mented using different approaches languages and software-e final version of the Hamming code was Hamming [1611 4]2 -is code allows SECDED Using only 12 adaptivelogic modules (ALMs) the code is extremely small meaningthe selected FPGA will consume a minimal amount ofpower By optimizing the resource usage the average fan-outcan be reduced from 181 to 159 and runs on a period of18 ns with no violation and an arrival time of 5987 nsWhen optimized from a timing perspective the code can beoptimized to runs off a clock period of 18 with no violationsand an arrival time of 5394 ns

Due to Hamming [16 11 4]2 resource usage of theoriginal code already being so small the timing optimizationapproach is recommended it is 0593 ns faster -is impliesthat a Hamming code was developed capable of protecting11 bits of information against SEU and capable of DED -ecode is capable of reading and writing to memory within5394 ns using only 12 ALMs and 24 registers

-e data from Alsat-1 is considered as a worst casescenario -is means Hamming [16 11 4]2 is theoreticallycapable of preventing all single-bit errors (SBE) or plusmn986 ofall SEUs experienced onboard ZA-cube 2 Hamming [16 114]2 detection capability also allows the prevention of somemultiple-bit errors (MBE) Should the nanosatellite betraveling through the South Atlantic Anomaly (SAA) it ispossible to implement triple modular redundancy (or asimilar EDAC scheme) together with Hamming [16 11 4]2-is will equip the nanosatellite to deal with double-byteerrors and severe errors

-e field of nanosatellites is constantly evolving andgrowing at an astonishing pace -is is due to the fact that itprovides a platform from which the boundaries of space andtechnology are constantly being pushed As technologyadvances memory chip cell architecture is becoming moreand denser especially with the development of nanotech-nology -is creates a growing demand for a more advancedand reliable EDAC system that is capable of protecting allmemory aspects of satellites -e code developed in thispaper guarantees SECDED at fast speeds

Table 9 Summary of developed codes

Hamming scheme Variation Approach Capabilities Improvements Matlab model VHDLmodel

Hamming [7 4 3]2 Original Systematic SECSED None Yes YesHamming [8 4 4]2 Extended Nonsystematic SECDED Hamming distance Yes NoHamming [16 11 4]2 Extended Nonsystematic SECDED Hamming distance overhead and code rate Yes Yes

Table 10 Original vs optimized Hamming compression

Hamming [16 11 4]2Description Original Resource reduction Timing reduction

Resource summary

ALM 12 12 12ALUT 13 13 137-input 0 0 06-input 7 2 75-input 0 0 04-input 0 0 0le3-input 6 22 6

Dedicated logic registers 24 24 24IO pins 27 27 27

Max fan-out 24 24 24Total fan-out 165 145 165

Average fan-out 181 159 181

Timing analysis

Clock period 1 ns 225 ns 18 nsFrom node Datain_s[5] Datain_s[2] Datain_s[8]To node Dataout_s[10]simreg0 Dataout[1]simreg0 Dataout[8]simreg0

Data arrival time 5624 ns 5987 ns 5394 nsData required time 4827 ns 6076 ns 5491 ns

Slack minus0797 ns (violation) 0089 ns 0097 ns

14 Journal of Electrical and Computer Engineering

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

In this paper EDAC schemes with a focus on Hammingcodes are extensively discussed and studied -e ZA-cube 2nanosatellite was used as a case study when conductingresearch on error correction codes Hamming codes and theoptimizing of Hamming codes

Data Availability

-e data wherever required is referenced in the paper

Conflicts of Interest

-e authors declare that they have no conflicts of interest

References

[1] R Banu and T Vladimirova ldquoOn-board encryption in earthobservation small satellitesrdquo in Proceedings 40th Annual 2006International Carnahan Conference on Security Technologypp 203ndash208 Lexington KY USA October 2006

[2] J Daemen and R Rijmen -e Design of Rijndael AES - -eAdvanced Encryption Standard Spriger-Verlag publicationBerlin Germany 1st edition 2002

[3] W Sun J P S Mba and PM Sweeting ldquoMicro-minisatellitesfor affordable EO constellations RapidEye and DMCrdquo inProceedings of IAA Symposium on Small Satellites for EarthObservation Berlin Germany April 2001

[4] W E Burr ldquoSelecting the advanced encryption standardrdquoIEEE Security amp Privacy Magazine vol 1 no 2 pp 43ndash522003

[5] S P Bain ldquo-e increasing threat to satellite communicationsrdquoOnline Journal of Space Communication vol 6 no 6 2003

[6] G Bertoni L Breveglieri I Koren P Maistri and V PiurildquoError analysis and detection procedures for a hardwareimplementation of the advanced encryption standardrdquo IEEETransactions on Computers vol 52 no 4 pp 492ndash505 2003

[7] RW Hamming ldquoError detecting and error correcting codesrdquoBell System Technical Journal vol 29 no 2 pp 147ndash160 1950

[8] L-J Saiz-Adalid P Gil J-C Baraza-Calvo J-C Ruiz D Gil-Tomas and J Gracia-Moran ldquoModified hamming codes toenhance short burst error detection in semiconductormemoriesrdquo in Proceedings of the Tenth European DependableComputing Conference pp 62ndash65 Newcastle UK May 2014

[9] F Cput Zacube-1 French South African Institute of Tech-nology Bellville South Africa 2017

[10] D De Villiers and R Van Zyl ZACube-2 the Successor toAfricarsquos First Nanosatellite French South African Institute ofTechnology Bellville South Africa 2018

[11] Y Bentoutou ldquoA real time EDAC system for applicationsonboard earth observation small satellitesrdquo IEEE Transactionson Aerospace and Electronic Systems vol 48 no 1 pp 648ndash657 2012

[12] J s Chitode Analog And Digital Communication TechnicalPublication Pune India 2nd edition 2009

[13] M Gschwind and V Salapura Optimizing VHDL Code forFPGA Targets University of Sussex Brighton UK 2014

Journal of Electrical and Computer Engineering 15

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom

International Journal of

AerospaceEngineeringHindawiwwwhindawicom Volume 2018

RoboticsJournal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Active and Passive Electronic Components

VLSI Design

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Shock and Vibration

Hindawiwwwhindawicom Volume 2018

Civil EngineeringAdvances in

Acoustics and VibrationAdvances in

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Electrical and Computer Engineering

Journal of

Advances inOptoElectronics

Hindawiwwwhindawicom

Volume 2018

Hindawi Publishing Corporation httpwwwhindawicom Volume 2013Hindawiwwwhindawicom

The Scientific World Journal

Volume 2018

Control Scienceand Engineering

Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom

Journal ofEngineeringVolume 2018

SensorsJournal of

Hindawiwwwhindawicom Volume 2018

International Journal of

RotatingMachinery

Hindawiwwwhindawicom Volume 2018

Modelling ampSimulationin EngineeringHindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Chemical EngineeringInternational Journal of Antennas and

Propagation

International Journal of

Hindawiwwwhindawicom Volume 2018

Hindawiwwwhindawicom Volume 2018

Navigation and Observation

International Journal of

Hindawi

wwwhindawicom Volume 2018

Advances in

Multimedia

Submit your manuscripts atwwwhindawicom