Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 1 of part 2

Schematic Task Execution Example

time

EA B C D F (Deadline)

Execution i Execution i+1

KeyAD: Task execution timeAF: Task periodAE: JitterBC: Transport lag

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 2 of part 2

More About Deadlines

Usually defined as: Hard

If missed, usually result in some sort of system catastrophic failure

FirmIf missed, usually cause the system to produce useless (or senseless) results

SoftIf missed, usually deter from the usefulness of the results in direct proportion to the extent by which the soft deadline is missed

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 3 of part 2

Performance of R-T SystemsMain players are: Response time

Context switching Interrupt latency Computation speed Data storage access speed

Data transfer rate Loads of hardware stats (I/O

throughput, bus inertia, disk performance, memory/buffer size, controller performance, etc.)

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 4 of part 2

Interrupt Handling

In non-R-T systems interrupts may be handled whenever deemed appropriate by the system

In R-T systems it’s the external world which dictates when the system is to respond.

Interrupts need not be sequential - meaning the allocation of priorities to different interrupts

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 5 of part 2

Multi-priority Interrupts

time

Inte

rru

pt p

riori

ty le

vel

3

2

1

0

Key Level 3 interrupt execution Level 2 “ “ Level 1 “ “ Normal computation priority

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 6 of part 2

Important Interrupt Modelling Facts More than one real-world interrupt

can arrive at any time Interrupts can be interrupted by

others with a higher priority Too many interrupts can hinder

overall R-T system performance Devise ways by which to minimise

the impact of multiple interrupts on the system

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 7 of part 2

Dynamic performance calculationTake into account: Average interrupt frequency Average time required to service a

serviceable interrupt Other parts of the software that

can interrupt their servicing

It is of system-vital importance that thesystem remains capable of meeting all itstime constraints even in the face of“interrupt onslaught”. Failure to do so willresult in system collapse.

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 8 of part 2

Part 1 of your assignment

PLEASE SEE SEPARATE DOCUMENT, THE

NAME OF WHICH WILL BE ANNOUNCED IN

DUE COURSE, FROM WEBSITE

DOWNLOAD OR ANNOUNCMENTS AREAS

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 9 of part 2

R-T Task Classification

PeriodicExecution starts at pre-defined intervals

AperiodicRandom execution start times

ServerResource sharing and synchronisation

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 10 of part 2

Task Class Properties

Rate

Jitter Deadline

Executiontime

PERIODIC

Exceptions

Priority

Executiontime

Deadline

Activation &executionconditions

Priority APERIODIC

Timingconstraints

Activation &executionconditions

Usageconstraints

SERVER

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 11 of part 2

Example of R-T System Requirements(Based on example in “Software Engineering Fundamentals” by A. Behforooz et al.)

Execution time = 20 msPeriod = 100 ms

Execution time = 40 msPeriod = 150 msDeadline = 130 ms

Execution time = 100 msPeriod = 350 ms

Periodic Task 1

Periodic Task 2

Periodic Task 3

Usage:1(2 ms), 2(20 ms)

Usage:1(10 ms), 3(10 ms)

Server Task 1

Server Task 2

Mean arrival time = 50 msExecution time = 3 msDeadline = 5 ms

Aperiodic Task 1

Mean arrival time = 40 msExecution time = 2 msDeadline = 4 ms

Aperiodic Task 2

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 12 of part 2

Execution Time Estimation

Values required for calculation are:

Average instruction execution time Interrupt latency Very detailed description of task I/O instruction execution time

Interrupt latency is analysed in the following slide ...

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 13 of part 2

Interrupt Latency Composition

Interrupt latency

Interrupt occurs

Save state of current task

Decode interrupt

Start and complete interrupt actions

Save state of interrupt

Restore state of interrupted task

Continue execution of interrupted task

1

2

3

4

5

6

7

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 14 of part 2

Execution Time Estimation Example (1)

Known quantities are:

Task rate (30 s-1) period of 33.33 ms

Longest exec. path (2900 sloc) HLL-to-assembly expansion (6:1) Interrupt latency (0.1 ms) Av. int. trans. delay (0.85 ms) Av. instruction exec. time (300 ns) Assume a “cushioning” of 20%

Ernest CachiaUniversity of Malta“Real-Time System Development”Slide No. 15 of part 2

Max task execution time:2900 sloc x 6 = 17,400 tloc

1 tloc execution time: 0.0003 ms

Total tloc execution time:17,400 tloc x 0.0003 ms = 5.22 ms

Total execution time for 1 task:(total tloc exe. + int. trans. delay + int. latency)5.22 ms + 0.85 ms + 0.1 ms = 6.17 ms

Total periodic execution time:6.17 ms x 30 tasks/s = 185.1 ms

Include cushioning (20%):185.1 ms + 10.8 ms = 196 ms

Execution Time Estimation Example (2)