EREF RM, EREF: A Programmer's Reference Manual for Freescale Power … · EREF: A Programmer’s...

EREF: A Programmer’s Reference Manualfor Freescale Power Architecture Processors

Supportse500 core family

(e500v1, e500v2, e500mc, e5500, e6500)e200 core family

EREF_RMRev. 1 (EIS 2.1)

06/2014

EREF: A Programmer’s Reference Manual for Freescale Power Architecture Processors, Rev. 1 (EIS 2.1)

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ContentsParagraphNumber Title

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Contents

About This Book

How to Use this Book................................................................................................. xxxviiAudience .................................................................................................................... xxxviiiOrganization............................................................................................................... xxxviiiSuggested Reading....................................................................................................... xxxix

Documentation Set................................................................................................... xxxixGeneral Information....................................................................................................... xl

Conventions ....................................................................................................................... xlAcronyms and Abbreviations ........................................................................................... xliTerminology Conventions................................................................................................ xlii

Chapter 1 Overview

1.1 Power Architecture® Technology and the Freescale Embedded Implementation Standards (EIS)................................................................ 1-1

1.1.1 EIS Architecture Version ............................................................................................. 1-11.1.2 Understanding Differences in the Book E and EIS or

EREF Specification Structures ................................................................................ 1-21.1.3 Introducing the Power ISA Category........................................................................... 1-21.1.3.1 Understanding the Base Category ........................................................................... 1-31.1.3.2 Understanding the Embedded and Server Categories ............................................. 1-31.1.3.3 Benefits of Categories.............................................................................................. 1-31.1.4 Power Architecture Evolution ..................................................................................... 1-31.1.5 Freescale Embedded Implementation Standards (EIS) ............................................... 1-41.1.6 EIS Use of Power ISA Categories ............................................................................... 1-51.1.6.1 Category Designations in EIS.................................................................................. 1-61.1.6.1.1 Category Designation Considerations ................................................................. 1-61.1.6.2 Categories Supported by All Freescale EIS Processors .......................................... 1-71.1.6.3 Categories Supported by Some Freescale EIS Processors ...................................... 1-71.1.6.3.1 PowerISA Category Abbreviations and Acronyms............................................. 1-71.1.6.3.2 EIS Category Abbreviations and Acronyms ....................................................... 1-81.1.6.4 Categories Not Supported by Freescale EIS Processors.......................................... 1-91.1.7 Special Instruction Differences Between Book E and EREF ...................................... 1-91.2 EREF Programming Model ........................................................................................... 1-101.2.1 RISC Architecture Overview..................................................................................... 1-101.2.2 EIS Architecture Overview........................................................................................ 1-10


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1.2.3 Privilege Model.......................................................................................................... 1-101.2.3.1 Hypervisor State Considerations ........................................................................... 1-111.2.3.2 Guest Supervisor State Considerations.................................................................. 1-111.2.3.3 User State Considerations...................................................................................... 1-111.2.4 Instruction Model....................................................................................................... 1-121.2.4.1 VLE Instruction Set Overview .............................................................................. 1-121.2.4.2 VLE Instruction Set Features................................................................................. 1-121.2.5 Register Model........................................................................................................... 1-131.2.6 Exceptions and Interrupt Handling ............................................................................ 1-141.2.6.1 Understanding Exceptions ..................................................................................... 1-141.2.6.2 Interrupts Overview............................................................................................... 1-151.2.6.2.1 Understanding the Four Levels of Interrupts..................................................... 1-151.2.6.2.2 Interrupt Handling ............................................................................................. 1-161.2.7 Memory (Storage) Model .......................................................................................... 1-161.2.7.1 Memory Addresses ................................................................................................ 1-161.2.7.2 Weakly Ordered Memory ...................................................................................... 1-171.2.7.3 Memory Management............................................................................................ 1-171.2.7.3.1 Optional TLB Properties ................................................................................... 1-171.2.7.3.2 How the Architecture Benefits Memory Management...................................... 1-181.2.7.4 Caches.................................................................................................................... 1-181.3 Timers ............................................................................................................................ 1-181.4 Debug............................................................................................................................. 1-191.5 Performance Monitoring................................................................................................ 1-191.6 Major Additions to EIS.................................................................................................. 1-19

Chapter 2 Multi-Threading

2.1 Definitions ....................................................................................................................... 2-12.2 Multi-threading Model..................................................................................................... 2-12.2.1 Logical Partitioning and Multi-Threading .................................................... 2-22.3 Sharing of Multi-Threaded Resources ............................................................................. 2-22.3.1 Synchronizing Changes to Shared State ...................................................................... 2-22.3.1.1 Enabling and Disabling Threads.............................................................................. 2-22.4 Thread Management ........................................................................................................ 2-32.5 Interrupts .......................................................................................................................... 2-3

Chapter 3 Computation Modes

3.1 Computation Modes......................................................................................................... 3-1


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3.2 64-bit Implementations ........................................................................................... 3-13.3 32-bit Implementations .................................................................................................... 3-2

Chapter 4 Register Model

4.1 Register Model Overview................................................................................................ 4-14.1.1 Registers Accessed as Part of an Instruction Execution .............................................. 4-14.1.1.1 Registers Used for Integer Operations..................................................................... 4-14.1.1.2 Registers Used for Floating-Point Operations ............................................... 4-24.1.1.3 Registers Used for Vector Operations ............................................................. 4-24.1.1.4 Condition Register (CR) .......................................................................................... 4-24.1.1.5 Machine State Register (MSR)................................................................................ 4-24.1.2 Special-Purpose Registers (SPRs) ............................................................................... 4-24.1.3 Memory Mapped Registers (MMRs)........................................................................... 4-34.1.4 Thread Management Registers (TMRs) .................................................... 4-34.1.5 Performance Monitor Registers .................................................................... 4-34.1.6 Device Control Registers .............................................................................. 4-34.2 Register Model................................................................................................................. 4-34.2.1 Understanding How the Registers are Accessed ......................................................... 4-34.2.2 Special-Purpose Registers (SPRs) ............................................................................... 4-54.2.2.1 SPR Register Mapping ............................................................................ 4-154.2.3 Memory Mapped Registers........................................................................................ 4-174.2.4 Thread Management Registers (TMRs) .................................................. 4-204.3 Registers for Integer Operations .................................................................................... 4-264.3.1 General-Purpose Registers (GPRs)............................................................................ 4-264.3.2 Integer Exception Register (XER)............................................................................. 4-264.4 Registers for Floating-Point Operations .............................................................. 4-284.4.1 Floating-Point Registers (FPR0–FPR31) .................................................................. 4-284.4.2 Floating-Point Status and Control Register (FPSCR)................................................ 4-284.4.3 Floating-Point Data.................................................................................................... 4-314.4.3.1 Data Format ........................................................................................................... 4-324.4.3.2 Value Representation ............................................................................................. 4-334.4.3.2.1 Numeric and Non-Numeric Values.................................................................... 4-334.4.3.2.2 Floating-Point Values ........................................................................................ 4-334.4.3.3 Sign of Result ........................................................................................................ 4-354.4.3.4 Normalization and Denormalization...................................................................... 4-364.4.3.5 Data Handling and Precision ................................................................................. 4-364.4.3.5.1 Single-Precision Operands ................................................................................ 4-364.4.3.5.2 Integer-Valued Operands ................................................................................... 4-384.4.3.6 Rounding................................................................................................................ 4-38


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4.4.3.6.1 Arithmetic, Rounding, and Conversion Instructions ......................................... 4-384.4.3.6.2 Rounding Modes................................................................................................ 4-394.5 Registers for Branch Operations.................................................................................... 4-404.5.1 Condition Register (CR) ............................................................................................ 4-404.5.1.1 CR Setting for Integer Instructions........................................................................ 4-414.5.1.2 CR Setting for Store Conditional Instructions....................................................... 4-424.5.1.3 CR Setting for Floating-Point Instructions ............................................................ 4-424.5.1.4 CR Setting for Compare Instructions .................................................................... 4-424.5.1.5 CR Bit Settings in VLE Mode .................................................................. 4-434.5.1.5.1 CR Settings for Integer Instructions in VLE ........................................ 4-444.5.1.5.2 CR Setting for Compare Instructions in VLE ...................................... 4-444.5.1.5.3 CR Setting for the VLE Bit Test Instruction ........................................ 4-454.5.2 Link Register (LR)..................................................................................................... 4-454.5.2.1 Link Register Usage in VLE Mode .......................................................... 4-454.5.3 Count Register (CTR)................................................................................................ 4-464.5.3.1 Count Register Usage in VLE Mode ........................................................ 4-464.5.4 Branch Unit Control and Status Register (BUCSR).................................................. 4-474.6 Processor Control Registers........................................................................................... 4-474.6.1 Machine State Register (MSR) .................................................................................. 4-474.6.1.1 Interrupt Handling and the MSR ........................................................................... 4-474.6.1.2 Using the mfmsr Instruction .................................................................................. 4-484.6.1.3 Using the mtmsr Instruction .................................................................................. 4-484.6.1.4 Changing MSR Content in Guest Supervisor State ............................................... 4-484.6.2 Machine State Register Protect Register (MSRP) ...................................... 4-514.6.2.1 Using the MSRP .................................................................................................... 4-524.6.2.2 Behavior of Cache Locking Instructions in Guest Supervisor State ..................... 4-524.6.2.3 Behavior of Performance Monitor Instructions in Guest Supervisor State ........... 4-524.6.3 Embedded Processor Control Register (EPCR) ............................... 4-534.6.4 Hardware Implementation-Dependent Registers....................................................... 4-554.6.4.1 Hardware Implementation-Dependent Register 0 (HID0) .................................... 4-554.6.4.2 Hardware Implementation-Dependent Register 1 (HID1) .................................... 4-584.6.5 Processor ID Register (PIR) ...................................................................................... 4-584.6.6 Guest Processor ID Register (GPIR) .......................................................... 4-604.6.7 Processor Version Register (PVR)............................................................................. 4-614.6.8 System Version Register (SVR)................................................................................. 4-624.6.9 Shifted CCSRBAR Register (SCCSRBAR).............................................................. 4-624.6.10 Chip Identification Register (CIR) ............................................................................ 4-634.6.11 Thread Management and Control Registers ................................................... 4-634.6.11.1 Thread Management Configuration Register 0 (TMCFG0) ............... 4-634.6.11.2 Thread Initial Next Instruction Address Register n (INIAn) .............. 4-634.6.11.3 Thread Initial Machine State Register n (IMSRn) .............................. 4-64


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4.6.11.4 Thread Priority Register n (TPRIn) ..................................................... 4-644.6.11.5 Thread Identification Register (TIR) ......................................................... 4-654.6.11.6 Thread Enable Register (TEN) ................................................................... 4-654.6.11.7 Thread Enable Set Register (TENS) .......................................................... 4-664.6.11.8 Thread Enable Clear Register (TENC) ...................................................... 4-674.6.11.9 Thread Enable Status Register (TENSR) ................................................... 4-684.6.11.10 Processor Priority Register (PPR32) .......................................................... 4-684.7 Timer Registers .............................................................................................................. 4-694.7.1 Timer Control Register (TCR)................................................................................... 4-704.7.2 Timer Status Register (TSR)...................................................................................... 4-714.7.3 Time Base (TB).......................................................................................................... 4-734.7.4 Decrementer Register (DEC)..................................................................................... 4-754.7.5 Decrementer Auto-Reload Register (DECAR).......................................................... 4-754.7.6 Alternate Time Base Registers (ATB) ....................................................................... 4-764.8 Interrupt Registers.......................................................................................................... 4-764.8.1 Save/Restore Registers 0 (SRR0, GSRR0, CSRR0, DSRR0, MCSRR0) ................. 4-764.8.2 Save/Restore Register 1 (SRR1, GSRR1, CSRR1, DSRR1, MCSRR1)................... 4-774.8.3 Interrupt Vector Prefix Register (IVPR) .................................................................... 4-784.8.4 Guest Interrupt Vector Prefix Register (GIVPR) ........................................ 4-794.8.5 Interrupt Vector Offset Registers (IVORs) ................................................................ 4-794.8.6 Guest Interrupt Vector Offset Registers (GIVORs) .................................... 4-814.8.7 Exception Syndrome Register (ESR) ........................................................................ 4-824.8.8 Guest Exception Syndrome Register (GESR) ............................................ 4-844.8.9 Data Exception Address Register (DEAR)................................................................ 4-854.8.10 Guest Data Exception Address Register (GDEAR) .................................... 4-854.8.11 Logical Page Exception Register (LPER) ............................... 4-864.8.12 Machine Check Syndrome Register (MCSR)............................................................ 4-874.8.13 Machine Check Address Register (MCAR/MCARU)............................................... 4-884.8.14 External Proxy Register (EPR) ..................................................................... 4-894.8.15 Guest External Proxy Register (GEPR) .............................................. 4-904.9 Software-Use SPRs (SPRGs, GSPRGs, and USPRGs) ................................... 4-904.10 L1 Cache Registers ........................................................................................................ 4-914.10.1 L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 4-914.10.2 L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 4-954.10.3 L1 Cache Control and Status Register 2 (L1CSR2) .................................................. 4-984.10.4 L1 Cache Control and Status Register 3 (L1CSR3) .................................................. 4-994.10.5 L1 Cache Control and Status Register 4 (L1CSR4) ................................................ 4-1004.10.6 L1 Cache Configuration Register 0 (L1CFG0) ....................................................... 4-1014.10.7 L1 Cache Configuration Register 1 (L1CFG1) ....................................................... 4-1024.10.8 L1 Flush and Invalidate Control Register 0 (L1FINV0) ............................ 4-1034.10.9 L1 Flush and Invalidate Control Register 1 (L1FINV1) ............................ 4-104


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4.11 L2 Cache Registers ...................................................................................................... 4-1054.11.1 L2 Configuration Register (L2CFG0) ..................................................................... 4-1054.11.2 L2 Cache Control and Status Register (L2CSR0) ................................................... 4-1064.11.3 L2 Cache Control and Status Register 1 (L2CSR1) ................................................ 4-1104.11.4 L2 Cache Partitioning Registers .............................................................................. 4-1104.11.4.1 L2 Cache Partitioning Identification Registers (L2PIRn) ....................................4-1114.11.4.2 L2 Cache Partitioning Allocation Registers (L2PARn)....................................... 4-1124.11.4.3 L2 Cache Partitioning Way Registers (L2PWRn) ............................................... 4-1144.11.5 L2 Error Registers.................................................................................................... 4-1154.11.5.1 L2 Error Control and Reporting .......................................................................... 4-1154.11.5.2 Error Capture ....................................................................................................... 4-1154.11.5.3 Error Injection...................................................................................................... 4-1164.11.5.4 L2 Cache Error Disable Register (L2ERRDIS)................................................... 4-1164.11.5.5 L2 Cache Error Detect Register (L2ERRDET) ................................................... 4-1174.11.5.6 L2 Cache Error Interrupt Enable Register (L2ERRINTEN) ............................... 4-1184.11.5.7 L2 Cache Error Control Register (L2ERRCTL) ................................................. 4-1194.11.5.8 L2 Cache Error Attribute Register (L2ERRATTR)............................................. 4-1204.11.5.9 L2 Cache Error Address Capture Registers (L2ERRADDR, L2ERREADDR).. 4-1214.11.5.10 L2 Cache Error Capture Data Registers (L2ECAPTDATALO,

L2ECAPTDATAHI) ........................................................................................ 4-1214.11.5.11 L2 Cache Error Capture ECC Syndrome Register (L2CAPTECC) .................... 4-1224.11.5.12 L2 Cache Error Injection Control Register (L2ERRINJCTL) ............................ 4-1234.11.5.13 L2 Cache Error Injection Mask Low and High Registers (L2ERRINJLO,

L2ERRINJHI).................................................................................................. 4-1234.12 MMU Registers............................................................................................................ 4-1244.12.1 Logical Partition ID Register (LPIDR) ..................................................... 4-1244.12.2 Process ID Register (PID)........................................................................................ 4-1254.12.3 MMU Control and Status Register 0 (MMUCSR0) ................................................ 4-1264.12.4 MMU Configuration Register (MMUCFG) ............................................................ 4-1274.12.5 TLB Configuration Registers (TLBnCFG).............................................................. 4-1284.12.6 TLB Page Size Registers (TLBnPS)........................................................................ 4-1314.12.7 Embedded Page Table Configuration Register (EPTCFG) ........................ 4-1314.12.8 Logical to Real Address Translation Configuration Register (LRATCFG)

..................................................................................................... 4-1334.12.9 Logical to Real Address Translation Page Size Register

(LRATPS) ................................................................................... 4-1344.12.10 MMU Assist Registers (MASn) .............................................................................. 4-1354.12.10.1 MAS Register 0 (MAS0) ..................................................................................... 4-1354.12.10.2 MAS Register 1 (MAS1) ..................................................................................... 4-1374.12.10.3 MAS Register 2 (MAS2) ..................................................................................... 4-1384.12.10.4 MAS Register 3 (MAS3) ..................................................................................... 4-140


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4.12.10.5 MAS Register 4 (MAS4) ..................................................................................... 4-1414.12.10.6 MAS Register 5 (MAS5) ...................................................................... 4-1434.12.10.7 MAS Register 6 (MAS6) ..................................................................................... 4-1444.12.10.8 MAS Register 7 (MAS7) ..................................................................................... 4-1454.12.10.9 MAS Register 8 (MAS8) ...................................................................... 4-1464.12.10.10 64-bit Access to MAS Register Pairs ........................................ 4-1474.12.11 External PID Registers .............................................................................. 4-1484.12.11.1 External PID Load Context Register (EPLC) ........................................ 4-1484.12.11.2 External PID Store Context (EPSC) Register ........................................ 4-1494.13 Debug Registers ........................................................................................................... 4-1504.13.1 Internal and External Debug Facility Control Registers.......................................... 4-1504.13.1.1 Debug Resource Request Register 0 (DBRR0) ................................................... 4-1514.13.1.2 External Debug Resource Allocation Register 0 (EDBRAC0) ........................... 4-1534.13.2 Debug Control Registers (DBCR0–DBCR6) .......................................................... 4-1564.13.2.1 Debug Control Register 0 (DBCR0).................................................................... 4-1564.13.2.2 Debug Control Register 1 (DBCR1).................................................................... 4-1584.13.2.3 Debug Control Register 2 (DBCR2).................................................................... 4-1614.13.2.4 Debug Control Register 3 (DBCR3).................................................................... 4-1634.13.2.5 Debug Control Register 4 (DBCR4).................................................................... 4-1634.13.2.6 Debug Control Register 5 (DBCR5).................................................................... 4-1644.13.2.7 Debug Control Register 6 (DBCR6).................................................................... 4-1664.13.2.8 Debug External Control Register 0 (DBECR0)................................................... 4-1674.13.3 Debug Counter Register (DBCNT) ......................................................................... 4-1674.13.4 Debug Status Register (DBSR/DBSRWR).............................................................. 4-1684.13.5 Instruction Address Compare Registers (IACn)...................................................... 4-1714.13.6 Data Address Compare Registers (DACn) .............................................................. 4-1724.13.7 Data Value Compare Registers (DVC1 and DVC2)................................................ 4-1724.13.8 Nexus and External Debug Related Registers ......................................................... 4-1734.13.8.1 Nexus SPR Access Registers............................................................................... 4-1734.13.8.1.1 Nexus SPR Configuration Register (NSPC) ................................................... 4-1734.13.8.1.2 Nexus SPR Data Register (NSPD) .................................................................. 4-1744.13.8.2 Debug Event Select Register (DEVENT)............................................................ 4-1744.13.8.3 Debug Data Acquisition Message (DDAM)........................................................ 4-1754.13.8.4 Nexus Process ID Register (NPIDR)................................................................... 4-1754.14 Processor Management Registers ................................................................................ 4-1754.14.1 Power Management Control Register 0 (PWRMGTCR0)....................................... 4-1754.14.2 Core Device Control and Status Register 0 (CDCSR0) .......................................... 4-1774.15 Performance Monitor Registers (PMRs) ....................................................... 4-1804.15.1 Global Control Register 0 (PMGC0/UPMGC0)...................................................... 4-1874.15.2 Local Control A Registers (PMLCan/UPMLCan) .................................................. 4-1874.15.3 Local Control B Registers (PMLCbn/UPMLCbn) .................................................. 4-189


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4.15.4 Performance Monitor Counter Registers (PMCn/UPMCn)..................................... 4-1904.16 SPE Registers............................................................................................................... 4-1914.17 AltiVec Registers ......................................................................................................... 4-1924.18 Device Control Registers (DCRs)................................................................................ 4-192

Chapter 5 Instruction Model

5.1 Operand Conventions ...................................................................................................... 5-15.1.1 Data Organization in Memory and Data Transfers...................................................... 5-15.1.2 Alignment and Misaligned Accesses........................................................................... 5-15.1.3 Storage Ordering of I/O Accesses ............................................................................... 5-25.1.4 Atomic Accesses.......................................................................................................... 5-25.2 Instruction Set Characteristics ......................................................................................... 5-45.3 Classes of Instructions ..................................................................................................... 5-55.3.1 Defined Instruction Class............................................................................................. 5-65.3.2 Illegal Instruction Class ............................................................................................... 5-65.3.3 Reserved Instruction Class........................................................................................... 5-65.3.4 Reserved Fields and Reserved Values ......................................................................... 5-75.4 Forms of Defined Instructions ......................................................................................... 5-85.4.1 Preferred Instruction Forms ......................................................................................... 5-85.4.2 Invalid Instruction Forms............................................................................................. 5-85.5 Instruction-Related Exceptions........................................................................................ 5-85.5.1 Boundedly Undefined................................................................................................ 5-105.5.2 Instruction Forms....................................................................................................... 5-105.5.2.1 Preferred Instruction Forms (no-op)...................................................................... 5-105.5.2.2 Invalid Instruction Forms ...................................................................................... 5-115.5.3 Addressing Modes ..................................................................................................... 5-115.5.3.1 Memory Addressing .............................................................................................. 5-115.5.3.2 Memory Operands ................................................................................................. 5-115.5.3.3 Effective Address Calculation ............................................................................... 5-125.5.3.3.1 Data Memory Addressing Modes...................................................................... 5-125.5.3.3.2 Instruction Memory Addressing Modes ............................................................ 5-135.5.3.4 Byte Ordering ........................................................................................................ 5-135.5.4 Synchronization ......................................................................................................... 5-145.5.4.1 Memory Synchronization ...................................................................................... 5-145.5.4.2 Instruction Synchronization................................................................................... 5-155.5.4.2.1 Self-Modifying Code......................................................................................... 5-165.5.4.3 Synchronization Requirements.............................................................................. 5-175.5.4.4 Context Synchronization ....................................................................................... 5-225.5.4.5 Execution Synchronization.................................................................................... 5-22


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5.6 Instruction Summary...................................................................................................... 5-225.6.1 User-Level Instructions.............................................................................................. 5-235.6.1.1 Integer Instructions ................................................................................................ 5-235.6.1.1.1 Integer Arithmetic Instructions.......................................................................... 5-245.6.1.1.2 Integer Saturating Instructions ............................................................. 5-265.6.1.1.3 Integer Compare Instructions ............................................................................ 5-265.6.1.1.4 Integer Logical Instructions............................................................................... 5-275.6.1.1.5 Integer Rotate and Shift Instructions ................................................................. 5-285.6.1.2 Load and Store Instructions ................................................................................... 5-295.6.1.2.1 Load and Store Address Generation .................................................................. 5-295.6.1.2.2 Update Forms of Load and Store Instructions ................................................... 5-325.6.1.2.3 Integer Load Instructions................................................................................... 5-325.6.1.2.4 Integer Store Instructions................................................................................... 5-335.6.1.2.5 Integer Load and Store with Byte-Reverse Instructions.................................... 5-335.6.1.2.6 Integer Load and Store Multiple Instructions.................................................... 5-345.6.1.2.7 Floating-Point Load and Store Instructions ............................................. 5-345.6.1.2.8 Load and Reserve and Store Conditional Instructions ...................................... 5-375.6.1.2.9 Decorated Load and Store Instructions ................................................... 5-385.6.1.3 Floating-Point Instructions .......................................................................... 5-395.6.1.3.1 Floating-Point Move Instructions...................................................................... 5-405.6.1.3.2 Floating-Point Arithmetic Instructions.............................................................. 5-415.6.1.3.3 Floating-Point Multiply-Add Instructions ......................................................... 5-415.6.1.4 Floating-Point Rounding and Conversion Instructions ......................................... 5-425.6.1.5 Floating-Point Compare Instructions..................................................................... 5-435.6.1.6 Floating-Point Status and Control Register Instructions ....................................... 5-445.6.1.7 Floating-Point Exceptions ..................................................................................... 5-445.6.1.7.1 Invalid Operation Exception.............................................................................. 5-485.6.1.7.2 Zero Divide Exception....................................................................................... 5-505.6.1.7.3 Overflow Exception........................................................................................... 5-505.6.1.7.4 Underflow Exception......................................................................................... 5-515.6.1.7.5 Inexact Exception .............................................................................................. 5-525.6.1.8 Branch and Flow Control Instructions................................................................... 5-525.6.1.8.1 Branch Instruction Address Calculation............................................................ 5-535.6.1.8.2 Branch Relative Addressing Mode.................................................................... 5-535.6.1.8.3 Branch Conditional to Relative Addressing Mode............................................ 5-535.6.1.8.4 Branch to Absolute Addressing Mode............................................................... 5-545.6.1.8.5 Branch Conditional to Absolute Addressing Mode........................................... 5-555.6.1.8.6 Branch Conditional to Link Register Addressing Mode ................................... 5-555.6.1.8.7 Branch Conditional to Count Register Addressing Mode ................................. 5-565.6.1.9 Conditional Branch Control................................................................................... 5-565.6.1.9.1 Using a Link Register Stack .............................................................................. 5-58


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5.6.1.9.2 Branch Instructions............................................................................................ 5-595.6.1.9.3 Condition Register (CR) Logical Instructions................................................... 5-605.6.1.9.4 Trap Instructions ................................................................................................ 5-605.6.1.9.5 Integer Select Instruction................................................................................... 5-605.6.1.10 System Linkage Instruction ................................................................................... 5-625.6.1.11 Embedded Hypervisor Privilege Instruction ........................................... 5-625.6.1.12 Debug Instructions................................................................................................. 5-635.6.1.13 Processor Control Instructions............................................................................... 5-635.6.1.13.1 Move to/from Condition Register Instructions.................................................. 5-635.6.1.13.2 Move to/from Special-Purpose Register Instructions........................................ 5-645.6.1.13.3 Wait for Interrupt Instruction............................................................................. 5-645.6.1.14 Performance Monitor Instructions ......................................................................... 5-645.6.1.15 Memory Synchronization Instructions .................................................................. 5-645.6.1.16 Atomic Update Primitives Using Load and Reserve and

Store Conditional instructions ........................................................................... 5-665.6.1.16.1 Reservations....................................................................................................... 5-675.6.1.16.2 Forward Progress ............................................................................................... 5-685.6.1.16.3 Reservation Loss Due to Granularity ................................................................ 5-695.6.1.17 Cache Management Instructions............................................................................ 5-695.6.1.17.1 Cache Target Identifiers..................................................................................... 5-695.6.1.17.2 User-Level Cache Management Instructions..................................................... 5-715.6.1.17.3 Cache Locking Instructions ................................................................. 5-735.6.2 Hypervisor- and Supervisor-Level Instructions......................................................... 5-745.6.2.1 System Linkage and MSR Access Instructions ..................................................... 5-745.6.2.2 Supervisor-Level Memory Control Instructions.................................................... 5-765.6.2.2.1 Supervisor-Level Cache Management Instructions........................................... 5-765.6.2.2.2 TLB Management Instructions.......................................................................... 5-775.6.2.3 External PID Instructions ........................................................................ 5-805.6.2.4 Hypervisor-Level Messaging Instructions ............................................... 5-815.6.2.4.1 Sending and Receiving Messages...................................................................... 5-815.6.2.5 Performance Monitor Instructions ......................................................................... 5-835.6.2.6 Supervisor Thread Management Instructions ..................................... 5-845.6.2.7 Supervisor Level Device Control Register Instructions .......................... 5-845.6.3 Recommended Simplified Mnemonics...................................................................... 5-845.7 Instruction Listing.......................................................................................................... 5-85

Chapter 6 Instruction Set

6.1 Notation ........................................................................................................................... 6-16.1.1 Instruction Bit Numbering ........................................................................................... 6-2


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6.2 Instruction Fields ............................................................................................................. 6-36.3 Description of Instruction Operations.............................................................................. 6-56.4 Instruction Set ................................................................................................................ 6-11

Chapter 7 Cache and MMU Architecture

7.1 Cache and MMU Architecture Overview........................................................................ 7-27.2 Cache Model .................................................................................................................... 7-37.2.1 Storage Attributes and Coherency ............................................................................... 7-47.2.2 Cache Identifiers and CT Values ................................................................................. 7-47.2.3 Cache Control Instructions .......................................................................................... 7-57.3 Special Cache Management Functionality ...................................................................... 7-67.3.1 Cache Line Locking ....................................................................................... 7-67.3.1.1 Cache Line Lock Set, Query, and Clear Instructions............................................... 7-67.3.1.2 Error Conditions ...................................................................................................... 7-87.3.1.2.1 Overlocking ......................................................................................................... 7-87.3.1.2.2 Unable to Lock Conditions.................................................................................. 7-97.3.1.2.3 Mode Restricted Cache Locking Exceptions....................................................... 7-97.3.2 Direct Cache Flushing .................................................................................. 7-107.3.3 Cache Way Partitioning ............................................................................... 7-107.3.3.1 Interaction with Cache Locking Operations .......................................................... 7-117.4 Memory and Cache Coherency...................................................................................... 7-117.4.1 Memory/Cache Access Attributes (WIMGE Bits) .................................................... 7-117.4.2 Write-Through-Required Attribute (W) .................................................................... 7-137.4.3 Caching-Inhibited Attribute (I).................................................................................. 7-137.4.4 Memory Coherence–Required Attribute (M) ............................................................ 7-147.4.5 Guarded Attribute (G)................................................................................................ 7-157.4.5.1 Definition of Speculative and Out-of-Order Memory Accesses ........................... 7-157.4.5.2 Performing Operations Speculatively.................................................................... 7-167.4.5.2.1 Speculative Accesses to Guarded Memory ....................................................... 7-167.4.5.2.2 Instruction Accesses: Guarded Memory and No-Execute Memory .................. 7-177.4.6 Byte-Ordering (Endianness) Attribute (E)................................................................. 7-177.4.6.1 Big-Endian Pages and Multiple-Byte Scalars........................................................ 7-177.4.6.2 Little-Endian Pages and Multiple-Byte Scalars..................................................... 7-177.4.6.3 Structure Mapping Examples................................................................................. 7-177.4.7 Mismatched Memory Cache Attributes..................................................................... 7-197.4.7.1 Coherency Paradoxes and WIMGE....................................................................... 7-197.4.7.2 Self-Modifying Code ............................................................................................. 7-207.4.8 Shared Memory.......................................................................................................... 7-207.4.8.1 Memory Access Ordering...................................................................................... 7-20


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7.4.8.2 Architecture Ordering Requirements..................................................................... 7-217.4.8.3 Forcing Load and Store Ordering (Memory Barriers)........................................... 7-237.4.8.4 Architectural Memory Access Ordering................................................................ 7-247.4.8.5 Memory Barrier Example ...................................................................................... 7-257.4.8.5.1 Programming Considerations ............................................................................ 7-267.4.8.5.2 Programming Examples .................................................................................... 7-287.4.8.6 Lock Acquisition and Import Barriers ................................................................... 7-287.4.8.6.1 Acquire Lock and Import Shared Memory........................................................ 7-287.4.8.6.2 Acquire Lock and Import Shared Memory Using sync and mbar..................... 7-297.4.8.6.3 Obtain Pointer and Import Shared Memory ...................................................... 7-307.4.8.7 Lock Release and Export Barriers ......................................................................... 7-307.4.8.7.1 Export Shared Memory and Release Lock ........................................................ 7-317.4.8.7.2 Export Shared Memory and Release Lock Using sync or mbar........................ 7-317.4.9 Cache Stashing Memory Attributes and Ordering..................................................... 7-317.5 MMU Architecture ........................................................................................................ 7-327.5.1 MMU Programming Model ....................................................................................... 7-347.5.2 Virtual Address (VA) ................................................................................................. 7-367.5.2.1 Address Space (AS) Value..................................................................................... 7-377.5.2.2 Process ID (PID) Value.......................................................................................... 7-387.5.2.3 GS Value ................................................................................................. 7-397.5.2.4 LPID Value .............................................................................................. 7-407.5.3 TLB Concept.............................................................................................................. 7-407.5.3.1 TLB Entries ........................................................................................................... 7-447.5.3.2 TLB Entry Page Size ............................................................................................. 7-447.5.3.3 Reading and Writing TLB Entries ......................................................................... 7-467.5.3.4 TLB Management using the MAS Registers......................................................... 7-467.5.3.4.1 MAS Registers................................................................................................... 7-477.5.3.5 Reading TLB Entries ............................................................................................. 7-477.5.3.6 Writing TLB Entries .............................................................................................. 7-487.5.3.7 Searching TLB Entries .......................................................................................... 7-497.5.3.8 Invalidating TLB Entries ....................................................................................... 7-507.5.3.8.1 Invalidation of a Single TLB Entry by Clearing MAS1[V] .............................. 7-507.5.3.8.2 Invalidations Using tlbivax ............................................................................... 7-507.5.3.8.3 Invalidations Using tlbilx ................................................................... 7-527.5.3.8.4 Invalidate all Using MMUCSR0 ....................................................................... 7-537.5.3.8.5 Generous Invalidates and Invalidation Protection............................................. 7-537.5.4 Hardware Page Table Concept ..................................................................... 7-547.5.4.1 Definitions ............................................................................................................. 7-547.5.4.2 Page Table Translation........................................................................................... 7-557.5.4.2.1 Locating a Hardware Page Table and PTE ........................................................ 7-557.5.4.2.2 Translation and TLB Update Using a PTE ........................................................ 7-59


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7.5.4.3 Page Table Entry (PTE) ......................................................................................... 7-617.5.4.4 Software Synchronization Requirements for PTE Updates................................... 7-627.5.4.5 Page Table Updates................................................................................................ 7-627.5.4.6 Adding a Page Table Entry .................................................................................... 7-637.5.4.7 Deleting a Page Table Entry .................................................................................. 7-647.5.4.8 Modifying a Page Table Entry ............................................................................... 7-647.5.4.8.1 General Case...................................................................................................... 7-647.5.4.8.2 Modifying the SW0 and SW1 fields.................................................................. 7-647.5.4.8.3 Modifying a Reference or Change Bit............................................................... 7-647.5.4.8.4 Modifying the Virtual Address .......................................................................... 7-657.5.4.9 Invalidating an Indirect TLB Entry ....................................................................... 7-657.5.5 LRAT Concept .................................................................................. 7-657.5.5.1 LRAT Entries ......................................................................................................... 7-667.5.5.2 LRAT Entry Page Size........................................................................................... 7-677.5.5.3 Reading and Writing LRAT Entries....................................................................... 7-687.5.5.4 Invalidating LRAT Entries..................................................................................... 7-697.5.5.5 LRAT Translation .................................................................................................. 7-697.5.5.5.1 LRAT Translation During tlbwe........................................................................ 7-697.5.5.5.2 LRAT Translation During Page Table Translation ............................... 7-697.5.6 Address Translation ................................................................................................... 7-707.5.6.1 Match Criteria for TLB Entries ............................................................................. 7-727.5.6.2 Real Address Generation after a TLB Match ........................................................ 7-747.5.6.3 Page Size and Effective Address Bits Compared .................................................. 7-757.5.6.4 Permission Attribute Comparison.......................................................................... 7-767.5.6.5 Translation Algorithms .......................................................................................... 7-777.5.7 Access Control........................................................................................................... 7-787.5.7.1 Page Size and Real Address Generation................................................................ 7-787.5.8 Permission Attributes................................................................................................. 7-807.5.8.1 Execute Access Permission ................................................................................... 7-807.5.8.2 Read Access Permission ........................................................................................ 7-817.5.8.3 Write Access Permission ....................................................................................... 7-817.5.8.4 Permission Control and Cache Management Instructions..................................... 7-817.5.8.5 Use of Permissions to Maintain Page History ....................................................... 7-827.5.8.5.1 Page Referenced and Changed Bits in PTEs ........................................ 7-837.5.9 Crossing Page Boundaries ......................................................................................... 7-837.5.10 MMU Exception Handling ........................................................................................ 7-837.5.10.1 TLB Miss Exception Types ................................................................................... 7-837.5.10.1.1 Instruction TLB Error Interrupt Settings ........................................................... 7-847.5.10.1.2 Data TLB Error Interrupt Settings..................................................................... 7-847.5.10.1.3 TLB Miss Exception MAS Register Settings.................................................... 7-847.5.10.2 Permissions Violation Exception Types ................................................................ 7-85


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7.5.10.2.1 Virtualization Fault Exceptions ........................................................... 7-857.5.10.2.2 Page Table Fault Exceptions ................................................................ 7-857.5.10.2.3 Instruction Storage Interrupt Settings................................................................ 7-867.5.10.2.4 Data Storage Interrupt Settings.......................................................................... 7-867.5.10.3 MAS Register Updates for Exceptions, tlbsx, and tlbre....................................... 7-877.5.10.4 LRAT Error Exception and Interrupt ............................................ 7-917.5.11 MMU Configuration Information.............................................................................. 7-91

Chapter 8 Interrupts and Exceptions

8.1 Overview.......................................................................................................................... 8-18.2 Interrupt Classes .............................................................................................................. 8-28.2.1 Recoverability from Interrupts..................................................................................... 8-28.3 Interrupt Registers............................................................................................................ 8-38.3.1 Save/Restore Registers ................................................................................................ 8-58.3.2 Other Registers that Help Service the Interrupt........................................................... 8-68.4 Directed Interrupts ............................................................................................ 8-78.5 Exceptions........................................................................................................................ 8-88.6 Synchronous and Asynchronous Interrupts ................................................................... 8-108.6.1 Requirements for System Reset Generation .............................................................. 8-118.7 Interrupt Processing ....................................................................................................... 8-118.8 Interrupt Definitions ...................................................................................................... 8-138.8.1 Critical Input Interrupt ............................................................................................... 8-188.8.2 Machine Check, NMI, and Error Report Interrupts................................................... 8-198.8.2.1 General Machine Check, Error Report, and NMI Mechanism.............................. 8-198.8.2.1.1 Error Detection and Reporting Overview.......................................................... 8-208.8.2.1.2 Machine Check and Non-Maskable Interrupts Considerations......................... 8-218.8.2.2 NMI Interrupts ....................................................................................................... 8-228.8.2.3 Error Report Synchronous Interrupts..................................................................... 8-228.8.2.4 Asynchronous Machine Check Interrupts ............................................................. 8-238.8.3 Data Storage Interrupt................................................................................................ 8-238.8.4 Instruction Storage Interrupt ...................................................................................... 8-278.8.5 External Input Interrupt ............................................................................................. 8-308.8.5.1 External Proxy .......................................................................................... 8-318.8.6 Alignment Interrupt ................................................................................................... 8-328.8.7 Program Interrupt....................................................................................................... 8-338.8.8 Floating-Point Unavailable Interrupt ............................................................... 8-358.8.9 System Call Interrupt ................................................................................................. 8-358.8.10 Decrementer Interrupt................................................................................................ 8-368.8.11 Fixed-Interval Timer Interrupt ................................................................................... 8-37


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8.8.12 Watchdog Timer Interrupt.......................................................................................... 8-388.8.13 Data TLB Error Interrupt ........................................................................................... 8-418.8.14 Instruction TLB Error Interrupt ................................................................................. 8-438.8.15 Debug Interrupt.......................................................................................................... 8-448.8.16 SPE/Embedded Floating-Point/AltiVec Unavailable Interrupt ............... 8-458.8.17 Embedded Floating-Point Data Interrupt ........................... 8-468.8.18 AltiVec Assist Interrupt ..................................................................................... 8-478.8.19 Embedded Floating-Point Round Interrupt ........................ 8-488.8.20 Performance Monitor Interrupt ................................................................... 8-498.8.21 Processor Doorbell Interrupt ........................................................................ 8-508.8.22 Processor Doorbell Critical Interrupt ........................................................... 8-518.8.23 Guest Processor Doorbell Interrupt ............................................................. 8-518.8.24 Guest Processor Doorbell Critical Interrupt ................................................ 8-528.8.25 Guest Processor Doorbell Machine Check Interrupt .................................. 8-538.8.26 Embedded Hypervisor System Call Interrupt ............................................. 8-548.8.27 Embedded Hypervisor Privilege Interrupt .................................................. 8-548.8.28 LRAT Error Interrupt ........................................................................ 8-558.9 Partially Executed Instructions ...................................................................................... 8-568.10 Interrupt Ordering and Masking .................................................................................... 8-578.10.1 Guidelines for System Software ................................................................................ 8-598.11 Exception Priorities........................................................................................................ 8-608.12 Processor Signaling (msgsnd and msgclr) ....................................................... 8-648.12.1 Sending Messages...................................................................................................... 8-648.12.2 Receiving, Filtering, and Accepting Messages.......................................................... 8-668.12.3 Message Types and Definitions ................................................................................. 8-67

Chapter 9 Timer Facilities

9.1 Timer Facilities ................................................................................................................ 9-19.2 Timer Registers ................................................................................................................ 9-29.3 Time Base Operation ....................................................................................................... 9-39.3.1 Writing the TB ............................................................................................................. 9-39.3.2 Reading the TB ............................................................................................................ 9-49.3.3 Computing Time of Day from the Time Base ............................................................. 9-49.3.4 Nonconstant Update Frequency................................................................................... 9-69.4 Decrementer Operation.................................................................................................... 9-69.5 Fixed-Interval Timer ........................................................................................................ 9-79.6 Watchdog Timer............................................................................................................... 9-89.7 Alternate Time Base....................................................................................................... 9-109.8 Freezing the Timer Facilities ......................................................................................... 9-10


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Chapter 10 Debug Facilities

10.1 Debug Facilities Overview ............................................................................................ 10-110.2 Internal and External Debug .......................................................................................... 10-110.3 Programming Model ...................................................................................................... 10-210.3.1 Debug Registers......................................................................................................... 10-210.3.2 Debug Instructions..................................................................................................... 10-210.3.3 Debug Interrupt.......................................................................................................... 10-210.4 Enabling Internal Debug Mode...................................................................................... 10-310.5 External Debug Mode.................................................................................................... 10-310.6 Dealing with Debug Resources...................................................................................... 10-310.6.1 Synchronizing Changes to Debug Facility Registers ................................................ 10-410.6.2 Pre-Completion and Post-Completion Interrupts ...................................................... 10-410.6.2.1 Synchronous Pre-Completion Debug Interrupts.................................................... 10-410.6.2.2 Synchronous Post-Completion Debug Interrupts .................................................. 10-510.6.2.3 Asynchronous Debug Interrupts ............................................................................ 10-510.7 Debug Conditions and Debug Events ............................................................................ 10-510.7.1 Suppressing Debug Events in Hypervisor Mode....................................................... 10-710.7.2 Instruction Address Compare Debug Event .............................................................. 10-710.7.2.1 Instruction Address Compare User/Supervisor Mode ........................................... 10-710.7.2.2 Effective/Real Address Mode................................................................................ 10-710.7.2.3 Instruction Address Compare Mode...................................................................... 10-710.7.2.4 Instruction Address Compare Debug Event Considerations ................................. 10-810.7.3 Data Address Compare Debug Event ........................................................................ 10-910.7.3.1 Data Address Compare Read/Write Enable........................................................... 10-910.7.3.2 Data Address Compare User/Supervisor Mode................................................... 10-1010.7.3.3 Effective/Real Address Mode.............................................................................. 10-1010.7.3.4 Data Address Compare Mode.............................................................................. 10-1010.7.3.5 Data Value Compare Mode.................................................................................. 10-1110.7.3.6 Data Address Compare Debug Event Considerations ......................................... 10-1110.7.4 Trap Debug Event .................................................................................................... 10-1210.7.5 Branch Taken Debug Event ..................................................................................... 10-1310.7.6 Instruction Complete Debug Event.......................................................................... 10-1310.7.7 Interrupt Taken Debug Event................................................................................... 10-1410.7.8 Critical Interrupt Taken Debug Event ....................................................... 10-1510.7.9 Return Debug Event................................................................................................. 10-1510.7.10 Critical Interrupt Return Debug Event ...................................................... 10-1610.7.11 Unconditional Debug Event (UDE)......................................................................... 10-1610.7.12 DAC and IAC Linking............................................................................................. 10-17


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Chapter 11 Performance Monitor

11.1 Performance Monitor Overview .................................................................................... 11-111.2 Performance Monitor Features ...................................................................................... 11-111.3 Performance Monitor Programming Model .................................................................. 11-211.3.1 Performance Monitor Registers Overview ................................................................ 11-211.3.2 Using PMRs to Control and Access Performance Monitoring.................................. 11-311.3.3 Performance Monitor Interrupt Model ...................................................................... 11-411.4 Performance Monitor Use Case ..................................................................................... 11-411.4.1 Event Counting .......................................................................................................... 11-511.4.2 Processor Context Configurability............................................................................. 11-511.4.2.1 Enabling the Monitor of Processor States.............................................................. 11-511.4.2.2 Specifying Unconditional Counting Modes .......................................................... 11-611.4.3 Event Selection .......................................................................................................... 11-611.4.4 Chaining Counters ..................................................................................................... 11-611.4.5 Thresholds.................................................................................................................. 11-7

Appendix A Instruction Set Listings

A.1 Instructions Sorted by Mnemonic (Decimal).................................................................. A-2A.2 Instructions Sorted by Opcodes (Decimal) ................................................................... A-31A.3 Instructions Sorted by Mnemonic (Binary) .................................................................. A-58A.4 Instructions Sorted by Opcode (Binary) ....................................................................... A-85A.5 Instruction Set Sorted by Form (Decimal)...................................................................A-112

Appendix B Simplified Mnemonics

B.1 Simplified Mnemonics Overview....................................................................................B-1B.2 Subtract Simplified Mnemonics ......................................................................................B-1B.2.1 Subtract Immediate ......................................................................................................B-1B.2.2 Subtract ........................................................................................................................B-2B.3 Rotate and Shift Simplified Mnemonics..........................................................................B-2B.3.1 Operations on Words ...................................................................................................B-3B.3.2 Operations on Double-words .......................................................................................B-3B.4 Branch Instruction Simplified Mnemonics......................................................................B-4B.4.1 Key Facts about Simplified Branch Mnemonics .........................................................B-5B.4.2 Eliminating the BO Operand .......................................................................................B-6B.4.3 Incorporating the BO Branch Prediction .....................................................................B-7


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B.4.4 The BI Operand—CR Bit and Field Representations..................................................B-8B.4.4.1 BI Operand Instruction Encoding............................................................................B-9B.4.5 Simplified Mnemonics that Incorporate the BO Operand .........................................B-11B.4.5.1 Examples that Eliminate the BO Operand.............................................................B-12B.4.6 Simplified Mnemonics that Incorporate CR Conditions (Eliminates

BO and Replaces BI with crS) ..............................................................................B-15B.4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions:

Examples ...........................................................................................................B-17B.4.6.2 Branch Simplified Mnemonics that Incorporate CR Conditions:

Listings ..............................................................................................................B-17B.5 Compare Word Simplified Mnemonics .........................................................................B-19B.6 Compare Double-word Simplified Mnemonics.............................................................B-20B.7 Condition Register Logical Simplified Mnemonics ......................................................B-21B.8 Trap Instructions Simplified Mnemonics ......................................................................B-21B.9 Simplified Mnemonics for Accessing SPRs ..................................................................B-23B.10 Recommended Simplified Mnemonics..........................................................................B-24B.10.1 No-Op (nop) ..............................................................................................................B-24B.10.2 Load Immediate (li) ...................................................................................................B-24B.10.3 Load Address (la) ......................................................................................................B-24B.10.4 Move Register (mr) ...................................................................................................B-25B.10.5 Complement Register (not) .......................................................................................B-25B.10.6 Move to Condition Register (mtcr)...........................................................................B-25B.10.7 Sync (sync) ................................................................................................................B-26B.10.8 Integer Select (isel) ....................................................................................................B-26B.10.9 System Call (sc) .........................................................................................................B-26B.10.10 Wait for Interrupt (wait) ............................................................................................B-26B.10.11 TLB Invalidate Local Indexed...................................................................................B-27

Appendix C Programming Examples

C.1 Synchronization ...............................................................................................................C-1C.1.1 Synchronization Primitives..........................................................................................C-2C.1.1.1 Memory Barriers......................................................................................................C-2C.1.1.2 Fetch and No-op ......................................................................................................C-2C.1.1.3 Fetch and Store ........................................................................................................C-3C.1.1.4 Fetch and Add..........................................................................................................C-3C.1.1.5 Fetch and AND........................................................................................................C-3C.1.1.6 Test and Set ..............................................................................................................C-3C.1.1.7 Compare and Swap ..................................................................................................C-4C.1.2 Lock Acquisition and Release .....................................................................................C-4


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C.1.2.1 More Efficient Locking Primitives ..........................................................................C-5C.1.3 List Insertion ................................................................................................................C-7C.1.4 Synchronization Notes.................................................................................................C-7C.2 Multiple-Precision Shifts .................................................................................................C-8C.3 Floating-Point Conversions .................................................................................C-10C.3.1 Conversion from a Floating-Point Number to Floating-Point Integer.......................C-10C.3.2 Conversion from Floating-Point Number to Signed Integer Doubleword .......C-11C.3.3 Conversion from Floating-Point Number to Unsigned Integer Doubleword ...C-11C.3.4 Conversion from Floating-Point Number to Signed Integer Word............................C-11C.3.5 Conversion from Floating-Point Number to Unsigned Integer Word .......................C-11C.3.6 Conversion from Signed Integer Doubleword to Floating-Point Number .......C-12C.3.7 Conversion from Unsigned Integer Doubleword to Floating-Point Number ...C-12C.3.8 Conversion from Signed Integer Word to Floating-Point Number ..................C-13C.3.9 Conversion from Unsigned Integer Word to Floating-Point Number ..............C-13C.4 Floating-Point Selection ................................................................................................C-13C.4.1 Floating-Point Selection Notes ..................................................................................C-14

Appendix D Floating-Point Models

D.1 Execution Model for IEEE-754 Operations.................................................................... D-1D.2 Multiply-Add Type Instruction Execution Model .......................................................... D-3D.3 Floating-Point Conversions ............................................................................................ D-4D.3.1 Conversion from Floating-Point Number to Floating-Point Integer .......................... D-5D.3.2 Conversion from Floating-Point Number to Signed

Fixed-Point Integer Double Word........................................................................... D-5D.3.3 Conversion from Floating-Point Number to Unsigned

Fixed-Point Integer Double Word........................................................................... D-5D.3.4 Conversion from Floating-Point Number to Signed

Fixed-Point Integer Word ....................................................................................... D-6D.3.5 Conversion from Floating-Point Number to Unsigned

Fixed-Point Integer Word ....................................................................................... D-6D.3.6 Conversion from Signed Fixed-Point Integer Double Word to

Floating-Point Number ........................................................................................... D-6D.3.7 Conversion from Unsigned Fixed-Point Integer Double Word to

Floating-Point Number ........................................................................................... D-7D.3.8 Conversion from Signed Fixed-Point Integer Word to

Floating-Point Number ........................................................................................... D-7D.3.9 Conversion from Unsigned Fixed-Point Integer Word to

Floating-Point Number ........................................................................................... D-8D.4 Floating-Point Models .................................................................................................... D-8


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D.4.1 Floating-Point Round to Single-Precision Model....................................................... D-8D.4.2 Floating-Point Convert to Integer Model.................................................................. D-12D.4.3 Floating-Point Convert from Integer Model............................................................. D-15D.5 Floating-Point Selection ............................................................................................... D-16D.5.1 Comparison to Zero .................................................................................................. D-16D.5.2 Minimum and Maximum.......................................................................................... D-16D.5.3 Simple If-Then-Else Constructions .......................................................................... D-17D.5.4 Notes ......................................................................................................................... D-17D.6 Floating-Point Load Instructions .................................................................................. D-17D.7 Floating-Point Store Instructions .................................................................................. D-18


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Figures

1-1 Power ISA ............................................................................................................................... 1-21-2 Power Architecture Relationships........................................................................................... 1-41-3 Extended GPRs as Implemented to Support SPE Instructions ............................................... 1-64-1 Integer Exception Register (XER) ..................

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Transcript of EREF RM, EREF: A Programmer's Reference Manual for Freescale Power … · EREF: A Programmer’s...