ERD Logic Section for 2009

ITRS Logic Workshop

San Francisco, Ca. Dec 14, 2008

George Bourianoff facilitating

Agenda

Determine content for 2009 ERD logic section – Section structure

– Transition table– Table 1 – “CMOS Extension” – Table 2 – “Beyond CMOS”– Potential solutions table

– Determine Technology Entries (TEs) for 2009– Determine transition table entries for 2009– Solicit writing volunteers for 2009

Add Potential Solutions table for Carbon Based Electronics Discuss linkage to materials and architecture sections

– How can we improve the integration? (better links to key materials properties table, …)

Approximate timeline for 2009

Proposed Chapter Structure

• Transition table - same structure 2007

• Table 1 - “CMOS Extension”– Include (devices with FET functionality)

• Low dimensional structures• III-V and Ge channel replacement structures• Carbon-based material channel replacement

structures• BTBT devices ?• ??????

Proposed Chapter structure (Cont)

• Table 2 “Beyond CMOS” devices– Category A “Digital Functionality”

• Spin Devices• NEMS switches• Atomic and molecular switches• ?????

– Category B “Non Digital Functionality”• Spin devices• Multi-ferroic devices• Molecular devices• ???

Proposed Chapter structure (Cont)

• Proposed solution table for carbon based Nanoelectronics

Discussion of Section Structure

• Transition table– discussion

• CMOS extension Table– discussion

• Beyond CMOS Table– Discussion

• Potential solution table

• Architectural linkage paragraph

High performance logic table 2007

FET Extension

Device

FET [A] 1D structures Channel replacement

SET Molecular Ferromagnetic logic

Spin transistor

Typical example devices Si CMOS CNT FET

NW FET

NW hetero-structures

Nanoribbon transistors with

graphene

III-V compound semiconductor and

Ge channel replacement

SET Crossbar latch

Molecular transistor

Molecular QCA

Moving domain wall

M: QCA

Spin Gain transistor

Spin FET

Spin Torque Transistor

Projected 100 nm 100 nm [D] 300 nm [I] 40 nm [O] 10 nm [U] 140 nm [Y] 100 nm [C] Cell Size (spatial

pitch) [B] Demonstrated 590 nm ~1.5 m [E] 1700 nm [J] ~200 nm [K, L] ~2 m [V] 250 nm [Z, AA] 100 m [AB]

Projected 1E10 4.5E9 6.1E9 6E10 1E12 5E9 4.5E9 Density (device/cm

2) Demonstrated 2.8E8 4E7 3.5E7 ~2E9 2E7 1.6E9 1E4

Projected 12 THz 6.3 THz [F] >1 THz 10 THz [Q] 1 THz [W] 1 GHz [Y] 40 GHz [AC] Switch Speed

Demonstrated 1.5 THz 200 MHz [G] >300 GHz 2 THz [R] 100 Hz [V] 30 Hz [Z, AA] Not known

Projected 61 GHz 61 GHz [C] 61 GHz [C] 1 GHz [O] 1 GHz [U] 10 MHz [Y] Not known Circuit Speed

Demonstrated 5.6 GHz 220 Hz [H] Data not available 1 MHz [P] 100 Hz [V] 30 Hz [Z] Not known

Projected 3E-18 3E-18 3.00E-18 1×10–18 [O]

[>1.5×10–17 ] [S] 5E-17 [X] ~1E-17 [Z] 3E-18

Switching Energy, J

Demonstrated 1E-16 1E-11 [H] 1E-16 [J] 8×10

–17 [T]

[>1.3×10–14

] [S] 3E-7 [V] 6E-18 [AA] Not known

Projected 238 238 61 10 1000 5E-2 Not known Binary Throughput, GBit/ns/cm

2 Demonstrated 1.6 1E-8 Data not available 2E-4 2E-9 5E-8 Not known

Operational Temperature RT RT RT RT [M, N] RT RT RT

Materials System Si

CNT,

Si, Ge, III-V,

In2O3, ZnO, TiO2, SiC,

InGaAs, InAs, InSb

III-V, Si, Ge, Organic

molecules Ferromagnetic

alloys

Si, III-V, complex metals oxides

Research Activity [AD] 379 62 91 244 32 122

Table 1 Proposed changes – “High Performance” >”CMOS Extension”

• Low dimensional structures :Carbon Nanotube FETs, nanowire FETs, Nanowire heterostructures, GNR FETS.

• High mobility channel replacement FETs including III-V and Ge

• Single electron devices - Move to table 2• Molecular devices including atomic switches- focus on

molecule on CMOS architecture (CMOL) concept - Move to table 2

• Ferromagnetic and coherent spin devices – Move to table 2

• Add Band to Band Tunneling Devices ??

Proposed CMOS Extension Entries

• Low dimensional structures (nanowires)

• III-V and Ge channel replacement structures

• Carbon-based material channel replacement structures (CNT and GNR)

• BTBT devices ?

• ??????

2007 Alternative Device Table

Resonant Tunneling Diodes

Multi-ferroic Tunnel Junctions

Single Electron Transistors

Molecular Devices Ferro-Magnetic Devices

Frequency Coherent Spin Devices

State Variable

Charge Dielectric and magnetic domain polarization

Charge Molecular conformation

Ferromagnetic polarization

Precession frequency

Response Function

Negative differential resistance

Four resistive states Staircase I/V from Coulomb blockade

Hysteretic Nonlinear Nonlinear

Class—Example

Mobile Multi-ferroic tunnel junction

Voltage tunable transfer function

CMOL, cross bar latch

Amplifiers, buses, switches

Spin torque oscillator

Architecture Heterogeneous Morphic Heterogeneous, morphic

MQCA, morphic Morphic

Application Elements in hybrid magneto electric circuits

Analog pattern matching

Associative processing , NP complete,

Elements in hybrid magneto-electric circuits

Microwave power, tunable rectifiers

Comments Additional functionality

Density, functionality

Density, cost functionality

Radiation hard, environmental rugged

RF functionality

Status Demo Demo Demo Demo Simulation

Material Issues

Stray charge RT DMS

Table 2 proposed changes “Alternative

Information Processing” > “Beyond CMOS”

• Resonant Tunneling Diodes – Move to transition table • Digital Functionality

– Multi-ferroic devices– Spin devices – Single Electron devices

• Non digital functionality – Molecular Devices – CMOL – Bi-layer graphene devices– MQCA– Frequency Coherent Spin Devices– RF devices

• Do we want to include some “architecture driven” device?

Proposed “Beyond CMOS” entries

• Category A “Digital Functionality”– Spin Devices– NEMS switches– Atomic and molecular switches– ?????

• Category B “Non Digital Functionality”– Spin devices– Multi-ferroic devices– Molecular devices– ???

2007 Transition table IN/OUT Reason for IN/OUT Comment

Rapid Single Flux Quanta (RSFQ) OUT

RSFQ devices, systems and circuits have been developed,

prototyped, and fabricated. They could become an

important technology if the correct market driver emerges

Design and fabrication lines for RSFQ systems exist.

Cryogenic operation, cost and material integration issues

limit application space

CMOS extension-III-V channel replacements IN

Low bandgap, compound III-V semiconductors can

potentially improve transistor performance

Research on compound III-V semiconductors on SI

substrates has increased significantly over the last 2

years

Impact Ionization MOS Possible Future

Simulation results showing very low sub threshold slopes

indicate potential for low power operation

Reliability remains an issue may be included in future

editions

Nano Electro Mechanical Systems (NEMS)

Possible Future Potential for ultra low leakage device based on nano relay

operation

Issues associated with stiction, speed, active power

and reliability are being studied –may be included in

future editions

Lateral interband tunneling transistor

Possible Future

Potential to utilize gate modulated interband tunneling to reduce subthreshold slope

May be included in future editions

Floating gate MOS devices Possible Future

Devices with nanocrystals embedded in gate allow circuits with tuneable

thresholds. Potential for low power circuits

May be included in future editions

2009 Transition table proposed

Technology Status Reason Comment

RTD out No viable logic functionality

Has been tracked for multiple revisions

Bi-layer tunneling devices

In Significant theoretical work in NRI

Band to band tunneling devices

In

NEMS In

RSFQ Possible future device

New topics for discussion

– Should we broaden the “CMOS extension” table to include Low Power” and “Low Standby Power” entries?

– Pros • Would align better with ITRS System Drivers• Would reflect motivation of much research

– Con• Would significantly complicate chapter organization • Would be orthogonal to the historical “tracking”

function of the Table

Technology Entries(1)

• FET extensions– Low dimension Channel replacement

category• CNTFETS and Nanowire FETS• Discuss CNTFETs with PIDs

– High mobility channel replacements• Send III-V and Ge to PIDs• Graphene Nanoribbon devices

SETs

• Move to Table 2– Some recent work still suggests logic

applications – Emphasize non logic applications

(recognition)– SETs have been around for a long time– Stray charge will always be problem

Nature of Nanotechnology advance online

Molecular devices

• Move to table 2

• Emphasize potential applications in crossbar architectures, CMOL

• Recent progress will be reviewed

• Some people believe strongly that the technology has great potential

Ferromagnetic and spin transistor

• Merge categories and move to table 2

• Emphasize non volatile functionality

• Include MQCA and domain wall applications

• STTRAM research is driving progress in materials and process

Band to band tunneling devices

• Include as a category in table 1 ???

• Include other steep SS devices

• Most devices suffer from low Isat or high Vd

• CNT tunnel FETs

Resonant Tunnel Diodes

• Recommend moving to transition table

• Pros– Not much recent progress for any logic

application

• Cons– It is an interesting device with NDR– Many people feel strongly about it

Multiferroic and magnetoelectric devices

• Include multiferroic tunnel junctions, magnetoelectric amplifiers, magnetoelectric drivers and detectors

• Significant progress in RT mutiferroic and magnetoelectric materials e.g. BFO

Single Electron devices

• Remove from table 1 -keep in table 2– Active research for Boolean applications

quantum dots– Potential Non Boolean logic applications such

as image recognition still receiving attention– Stray charge still an issue

Potential solution table for carbon based nanoelectronics

• Build on ITRS “potential solution” format

• Separate into material driven requirements and novel device driven requirements

• Tie closely and directly to ERM

ERM table of applications Table ERM2 Applications of Emerging Research Materials

MATERIALS ERD MEMORY ERD LOGIC LITHOGRAPHY FEP INTERCONNECTS ASSEMBLY AND

PACKAGE

Low Dimensional Materials

Nano-mechanical Memory

Nanotube

Nanowire

Graphene and graphitic structures

High-index immersion liquids

Nanotubes

Metal nanowires

Electrical applications

Thermal applications

Mechanical applications

Macromolecules Molecular memory Molecular devices Resists

Imprint polymers

Novel cleans

Selective etches

Selective depositions

Low-κ ILD

Polymer electrical and thermal/ mechanical property control

Self Assembled Materials

Sub- lithographic patterns

Enhanced dimensional control

Selective etch

Selective deposition

Deterministic doping

Selective etch

Selective deposition

High performance capacitors

Spin Materials MRAM by spin injection

Semiconductor spin transport

Ferromagnetic (FM) semiconductors

FM metals

Tunnel dielectrics

Passivation dielectrics

Complex Metal Oxides

1T Fe FET

Fuse-anti-fuse

Multiferroics (Spin materials)

Novel phase change

High performance capacitors

Interfaces and Heterointerfaces

Electrical and spin contacts and interfaces

Electrical and spin contacts and interfaces

Contacts and interfaces

Proposed structure - table 1First Year available for Production 2009 2010

45nm2011 2012 2013

32nm2014 2015 2016

22nm2017 2018 2019

16nm2020 2021 2022

11nm2023 2024

Materials & Processes for Carbon-based Nanoelectronics

CNTsdensity (pitch)growth control (type)dopingcontactingalignmentvariability

GrapheneManufacturable deposition patterningedge effectscontactingdielectricsbilayersvariability

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.

Research Required

Development Underway

Qualification / Pre-Production

Continuous Improvement

Proposed structure –table 2Carbon-based Nanoelectronics Devics

Digital CNTFET

Analog CNTFET

digital GNRFET

Analog GNRFET

bilayer devices

Quantum interference devices

This legend indicates the time during which research, development, and qualification/pre-production should be taking place for the solution.

Research Required

Development Underway

Qualification / Pre-Production

Continuous Improvement

Coupling to ERMERM Key Challenges 2007 Status Progress

-Control of bandgap and metallic versus semiconducting

Dai: >90% Semiconducting

CNT pitch needs to be ~30nm to achieve high current

-Control of carrier type and concentration

Control with ion adsorption

-Electrical properties must not degrade when embedded in a dielectric

“small” degradation reported

-Control of location

Dai: Control location with catalyst

-Control of orientation Control with E-Field, Quartz steps self assembly (Poor)

Carbon Nanotubes

Control of contact resistance High Variability Contact resistance must be reduced below 1 KΩ

-Control of location and orientation

Catalyst location & 111 growth for large diameter NW

-Performance exceeding patterned materials

Nanowires

-Catalyst and processing temperatures compatible with CMOS

Ti is compatible

CMOS Compatibility Not in 2007 Surface passivation Gate electrode & dielectric compatibility and control

III-V Alternate Channel Materials

Contact resistance No viable for contacting.. No

Gate electrode & dielectric compatibility and control

Contact resistance No viable for contacting.. No clear advantage over scaled Si

CMOS Compatibility Not in 2007 Surface passivation Gate electrode & dielectric compatibility and control

High resistivity of N type Ge – huge problem for CMOS

Contact resistance Compatibility with CMOS Processing Patterning for bandgap control (<2nm width

Poor: SiC decomposition, exfoliation

-Edge passivation

-Deposition of dielectrics

HfO2 demonstrated

-Low contact barrier for transport -Repeatability of switching mechanisms

-FM semiconductors with Tc>350K & carrier mediated exchange

-Low spin decoherence interfaces Bulk: 195K, GeMn Nanostructure reports >350K; carrier mediated exchange not verified

-Semiconductors with long spin coherence times

-Materials and interfaces to allow efficient spin injection from FM materials to semiconductors

-CMOS Compatibility

-Control of defects and interfaces

-Control of defects and interfaces during fabrication

Complex Metal Oxides (FE FET) Applications (FERAM, Spin memory, Spin Logic, Fuse-anti-Fuse)

-Degradation of materials properties during use

-Reliability of the fuse mechanism Complex Metal Oxides (Fuse-anti-fuse)

-Identification of dynamic properties compatible with logic applications

Coupled electronic and ferromagnetic states reported at heterointerfaces

-Co

Control of stoichiometry, vacancy concentration, and stress

Strongly Correlated Electron Materials (Novel Logic)

-Material compatibility with CMOS processing

-Surface Passivation

-High K compatibility and interface property control

-Demonstration of high mobility n& p channel devices

III-V and Ge Alternate Channel Materials New for 2009

-Strategy for integration of n & p channel devices

Writing volunteers

• People or groups to research and write text for one or more of the technology entries– Need informed but unbiased contributors

332. More Than Moore

Bulk

FD-SOIStrain Si

3D

Year

Ge

（ 110）

BallisticGOI

S-S/D

CNT GNR

2005 2035?

VariationsDFM High yield

Nanowire

2020?

High-k/metal-G

CMOS-based

Charge-based Other than charges

III-V

1. More Moore

3. Beyond CMOS

Should we include Future Integrated Nanoelectronics chart?

Spin

Atom molecularNanowire

(CMOS Extension)

Top-down Bottom-up

Optical Int.

Sub-60mV/dec

Main stream Si Fusion, No boundary

AlgorithmERD Working group Japan

34year

Beyond CMOS

Elements

ERD-WG in Japan

Existing technologies

New technologies

Evolution of Extended CMOS

CNT

III-V

Sub-60

Opt. Int.

Spin

Spin

Atom

Atom

Work in Progress --- Not for Publication35 ERD WG 12/06/08 & 12/14/08

2009 ITRS/ERD Major Deliverables and Timeline

ERD Chapter due August 21, 2009Major Tasks and Time Line Outlines for Memory, Logic, Architecture, Mat’l March 18 Technology Requirements Tables April 6 Guiding Principles Section June 1 Draft Text Completed

Memory, Logic, Architecture, Material July 6 Functional Organization & Critical Review July 20 Scope, Difficult Challenges, etc. July 27 Chapter Completed August 21 Chapter Frozen Sept. 15

Major Face-to-Face Meetings in 2009 ITRS/ERD Meeting near Brussels, Belgium March 18 ITRS/ERD Meeting at Semicon West (SF, CA) July 12 ITRS/ERD Meeting near Hsinchu, Taiwan Nov. 30