EPFL% Lausanne,Switzerland...Source:Intel Source:Intel Process variation...
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Hassan Ghasemzadeh Mohammadi, PierreEmmanuel Gaillardon, Giovanni De Micheli Integrated Systems Laboratory (LSI) EPFL Lausanne, Switzerland
Transcript of EPFL% Lausanne,Switzerland...Source:Intel Source:Intel Process variation...
Hassan Ghasemzadeh Mohammadi, Pierre-‐Emmanuel Gaillardon, Giovanni De Micheli
Integrated Systems Laboratory (LSI) EPFL
Lausanne, Switzerland
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Semiconductor technology trend
Single-‐gate devices
Mul@-‐gate de
vices
Nano-‐devices Silicon nanowires,
Carbon nano-‐tubes, … Source: Infineon
▲ Dimension shrinkage towards Moore’s law
▲ Short-‐channel effect immunity , Lower leakage, … Complex fabricaGon process, Process varia@on
Source: Intel
Source: Intel
Process variation
▲ The device parameters are not determinisGc anymore
▲ Affect yield and performance 3
Average tapeout delay due to variation issue: 2 month!
Source: LaunchM Survey, 2011
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▲ StaGsGcal informaGon from fabricated device ▽ Costly cross-‐secGon analysis
▲ StaGsGcal analysis by simulaGons ▽ Compact models ● Developing CMs for nano-‐devices is a costly procedure
▽ TCAD simulaGon ● ComputaGonal complexity
Curse of dimensionality!
PV analysis challenges for emerging technologies
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▲ Requirements: ▽ Fast (make Monte Carlo simulaGon possible,…)
▽ High precision
▲ SoluGon: ▽ Parameter reducGon ● Reducing computaGonal complexity
● Reasonable setup Gme
Fast PV analysis
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▲ Principal Component Analysis (PCA): C. Binjie et al., IEEE Design & Test of Computers, 27(2):26-‐35, 2010.
▽ Does not consider the input and out set correlaGons
▲ Independent Component Analysis (ICA): L. Cheng, P. Gupta, and L. He, ASP-‐DAC Tech. Dig., 2009.
▽ De-‐correlate non-‐Gaussian parameters
▲ Reduced Rank Regression (RRR): H. Feng and P. Li, IEEE TVLSI, 17(1):137-‐150, 2009.
▽ Does not consider the correlaGons within input set
State of art
Need for efficient parameter reduc@on method to address the limita@ons
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▲ Parameter reducGon ▽ The new parameters have different meaning ● Modifying the simulator-‐ actually is not possible ● Reconstruct input samples using reverse transformaGon
– Not possible for non-‐linear method
▲ Parameter selecGon ▽ Finding the most important parameters ● Straighaorward generaGon of input samples
PV analysis: Parameter selection or reduction?
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General methodology for Parameter selection
Full parameter set as input set Output set
Learning target model by nonlinear regression
Most important parameters
Reconstruct the model with “Reduced Parameter Set”
Apply sparsity to discard insignificant parameters
…
… …
…
TCAD model Compact Model
Dev
ice
Log
ic C
ell
Full
Chi
p
or
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▲ Performing non-‐linear regression to find the relaGon between input parameters and output ▽ Regression model
▽ Loss funcGon
▲ Applying sparsity to remove redundant parameters ▽ RegularizaGon term
Proposed method
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How does the regularization works?
Applying norm-p
Full parameter set
Reduced parameter set
Column-wise sparse weight matrix using norm-1
00
0
Finding the maximum element of each column
00
0
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Parameter selection algorithm
ObjecGve funcGon = MSE + RegularizaGon
Compute the error value (MSE)
Gradient-‐based opGmizaGon to update
Find the important parameters from The weight matrix
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Target device ▲ DG-‐SiNWFETs?
Tri-gate FinFET Current Technology
Scaling
Nanowire FETs Improved ElectrostaGc
In-‐field reconfigurability
Controllable-Polarity FETs Increase the funcGonality
Area = 4 Area = 18
Less transistors stacked Less delay 13
▲ The controllable polarity FET at circuit level
Compact realization of arithmetic function
CG
PG
S
D
CG S
D
PG = 0
p-‐FET
PG = 1 CG
S
D n-‐FET
CP-‐FET logic
CMOS logic
Control Gate
Polarity Gate
Device level PV effects N
umbe
r of d
evic
es
Num
ber o
f dev
ices
Num
ber o
f dev
ices
▲ Non-‐Gaussian variaGon
▲ Gaussian variaGon
Methodology have to deal with the both types of distribuGon
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Circuit level PV analysis
Applying parameter selecGon
Circuit simulaGon with and without parameter selecGon
StaGsGcal Gming analysis flow
▲ 30% Gaussian variaGon is applied on each geometrical parameters
Input set: geometrical parameters of transistors
Output set: Delay of the circuit
▲ Benchmark: ISCAS89-‐s27 (30 transistors)
ISCAS89-‐S27
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Performance enhancement
2.5 X speed up
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Comparison with other techniques
Methods Average error on
delay predic@on (%) σ error (%)
PCA 26.2 13.5
ICA 25.1 13.1
RRR 20.4 12.3
Proposed Method 16.5 11.7
Circuit level parameter reducGon with a desired performance
▲ 20% of parameters were selected according to their highest eigenvalues
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Summary
▲ PV analysis of emerging nano-‐devices: ▽ ComputaGonal Complexity, cost, and needs for accuracy, …
▲ Propose a new methodology: ▽ Based on non-‐linear mulGvariate regression + Sparsity ▽ DistribuGon free (Gaussian and non-‐Gaussian) ▽ Parameter selecGon in the input space
● Preserves the meaning of the parameters in the reduced space
▽ High precision ● Considering linear and non-‐linear dependencies for inter-‐set and intra-‐set parameters
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▲ Thank you for your amenGon!
Q&A
