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JOURNAL OF ELECfRONIC TESTING: Theory and Applications, 4, 315-329 (1993) © 1993 KJuwer Academic Publishers, BosLOn. Manufactured in The Netherlands. Enhancing Design-far-Test for Active Analog Filters by Using CLP(CR) FRANC NOVAK loief Stefan Institute, Jamova 39, 61111 Ljubljana, Slovenia [email protected] IGOR MOZETIC Austrian Research Institute for Artificial Intelligence, SchOITengasse 3, A-JOJO Vienna, Austria [email protected] MARINA SANlD-ZARNIK Iskra HIPOT, Sentjernej, Slovenia ANlDN BIASIZZO lozef Stefan Institute, lamova 39, 61111 Ljubljana, Slovenia Received April 19, 1993; Revised May 13, 1993. Editor: M. Soma Abstract. We describe a computer-aided approach to automatic fault isolation in active analog filters which enhances the design-for-test (DFT) methodology proposed by Soma (1990). His primary concern was in increased con- trollability and observability while the fault isolation procedure was sketched only in general terms. We opera- tionalize and extend the DFT methodology by using CLP(CR) to model analog circuits and by a model-based diagnosis approach to implement a diagnostic algorithm. CLP(CR) is a logic programming language which combines sym- bolic and numeric computation. The diagnostic algorithm uses different DFT test modes and results of voltage measurements for different frequencies and computes a set of suspected components. Ranking of suspected com- ponents is based on a measure of (normalized) standard deviations from predicted mean values of component parameters. The diagnosis is performed incrementally, in each step reducing the set of potential candidates for the detected fault. Case studies show encouraging results in isolation of soft faults of a given low-pass biquad filter. 1. Introduction (SAT) [2]. SBT techniques, based on fault dictionary, find limited applications in practice due to the high cost Fault diagnosis of analog circuits has been a research of analog simulation needed for the large number of area for more than two decades. A survey of methods potential fault modes. These techniques are more con- on this subject can be found in [1, 2]. Although venient for the isolation of hard faults. SAT techniques numerous, the results are not satisfactory in practice, use measurements to compute parameters of the net- and, according to [3], a breakthrough is needed to work (parameter identification techniques) or locate the develop test strategies for analog and mixed analogi faulty components without computing parameter values digital Ie. (fault verification techniques). They are suitable for In-circuit test and functional testing are established diagnosing soft faults (i .e., deviations of element techniques for testing both analog and digital circuits. parameters from the specified tolerance range). De- However, guarded test configuration as the basis of in- pending on the excitation source arrangement that is circuit test is limited in its capacity to operate at high used for test measurements, SAT techniques are char- frequencies. Moreover, the technique becomes very dif- acterized as single vector or multiple vector [5]. In the ficult for complex circuits where hundreds of test pins first case the measurement is implemented with a single and driver-sensor amplifiers are required, [4]. Conse- test frequency while the multiple-vector technique uses quently, functional testing of analog circuits is pre- multiple test frequencies for the solution of fault ferred. diagnosis equations. Two general methods of analog fault diagnosis are In recent years, artificial intelligence (AI) systems simulation before test (SBT) and simulation after test for fault diagnosis have gained considerable interest [6].

Transcript of Enhancing Design-far-Test for Active Analog Filters by ... fileEnhancing Design-far-Test for Active...

JOURNAL OF ELECfRONIC TESTING: Theory and Applications, 4, 315-329 (1993) © 1993 KJuwer Academic Publishers, BosLOn. Manufactured in The Netherlands.

Enhancing Design-far-Test for Active Analog Filters by Using CLP(CR)

FRANC NOVAK loief Stefan Institute, Jamova 39, 61111 Ljubljana, Slovenia [email protected]

IGOR MOZETIC Austrian Research Institute for Artificial Intelligence, SchOITengasse 3, A-JOJO Vienna, Austria [email protected]

MARINA SANlD-ZARNIK Iskra HIPOT, Sentjernej, Slovenia

ANlDN BIASIZZO lozef Stefan Institute, lamova 39, 61111 Ljubljana, Slovenia

Received April 19, 1993; Revised May 13, 1993.

Editor: M. Soma

Abstract. We describe a computer-aided approach to automatic fault isolation in active analog filters which enhances the design-for-test (DFT) methodology proposed by Soma (1990). His primary concern was in increased con­trollability and observability while the fault isolation procedure was sketched only in general terms. We opera­tionalize and extend the DFT methodology by using CLP(CR) to model analog circuits and by a model-based diagnosis approach to implement a diagnostic algorithm. CLP(CR) is a logic programming language which combines sym­bolic and numeric computation. The diagnostic algorithm uses different DFT test modes and results of voltage measurements for different frequencies and computes a set of suspected components. Ranking of suspected com­ponents is based on a measure of (normalized) standard deviations from predicted mean values of component parameters. The diagnosis is performed incrementally, in each step reducing the set of potential candidates for the detected fault. Case studies show encouraging results in isolation of soft faults of a given low-pass biquad filter.

1. Introduction (SAT) [2]. SBT techniques, based on fault dictionary, find limited applications in practice due to the high cost

Fault diagnosis of analog circuits has been a research of analog simulation needed for the large number of area for more than two decades. A survey of methods potential fault modes. These techniques are more con­on this subject can be found in [1, 2]. Although venient for the isolation of hard faults. SAT techniques numerous, the results are not satisfactory in practice, use measurements to compute parameters of the net­and, according to [3], a breakthrough is needed to work (parameter identification techniques) or locate the develop test strategies for analog and mixed analogi faulty components without computing parameter values digital Ie. (fault verification techniques). They are suitable for

In-circuit test and functional testing are established diagnosing soft faults (i .e., deviations of element techniques for testing both analog and digital circuits. parameters from the specified tolerance range). De­However, guarded test configuration as the basis of in­ pending on the excitation source arrangement that is circuit test is limited in its capacity to operate at high used for test measurements, SAT techniques are char­frequencies. Moreover, the technique becomes very dif­ acterized as single vector or multiple vector [5]. In the ficult for complex circuits where hundreds of test pins first case the measurement is implemented with a single and driver-sensor amplifiers are required, [4]. Conse­ test frequency while the multiple-vector technique uses quently, functional testing of analog circuits is pre­ multiple test frequencies for the solution of fault ferred. diagnosis equations.

Two general methods of analog fault diagnosis are In recent years, artificial intelligence (AI) systems simulation before test (SBT) and simulation after test for fault diagnosis have gained considerable interest [6].

316 Novak, et al.

Employed methods are a subclass of SAT techniques and can be further split into two distinct methodologies: shallow reasoning and deep reasoning. A typical shallow reasoning system builds a decision tree im­plemented by production rules. The approach has many limitations (e.g., production rules are not transferable to other UUT types, failure rate data necessary for the construction of a decision tree may be in some cases difficult to obtain, etc.). On the other hand, deep reasoning approach (also called model-based diagnosis) uses behavioral circuit models in fault diagnosis and is therefore transferable. Promising results of this ap­proach have been reported recently, [7, 8, 9].

The complexity of analog test fostered investigation of the design-for-test (OFT) principles for analog and mixed analog/digital circuits, [10-15]. As noticed in [10], the general problem of OFT for analog circuits is almost certainly intractable. Hence it is more rea­sonable to expect partial solutions suitable for specific classes of circuits. Another aspect is to establish some general OFT strategy for mixed analog/digital circuits. In this approach, individual analog and digital parts are replaced by functional blocks and OFT is investigated at the functional level [12-15].

The motivation for this work was the idea to use CLP(CR) for the simulation and diagnosis of analog cir­cuits. CLP(CR) is a logic programming system extended with a solver for systems of linear equations and ine­qualities. It is well suited to model real-valued system parameters with tolerances and feedback loops. First experiments (Mozetie et al. 1990) [9] showed that CLP(CR) has some advantages over classical simulation tools (like SPICE or Micro-CAP) since the same model can be used for both, simulation and diagnosis. CLP(CR) can locate potential soft faults, i.e., parameter values (resistors, capacitors) deviating from nominal values.

In this article we combine CLP(CR) with the OFT methodology proposed by Soma [10] in order to be able to distinguish between previously indistinguishable faults. Diagnostic algorithm implemented in CLP(CR) uses the results of measurements of magnitude and phase characteristics as a function of a real frequency variable in the normal mode and in the test modes. The diagnosis is performed incrementally, in each step reducing the set of potential candidates for the detected fault. The CLP(CR) system and measurement instrumen­tation have been integrated in an experimental system for automatic fault isolation. Experimental results are given to assess the efficiency of the proposed solution.

The article is organized as follows. In Section 2 we give a brief overview of the CLP(CR) language and illus­

trate how it can be used for diagnosis. The application of the node-analysis method for the justification of the CLP(CR) model is discussed. In Section 3 the main points of the OFT methodology for active analog ftIters are reviewed and the fault isolation procedure is described. In Section 4 experimental results are given together with the computed diagnoses. Finally, some concluding remarks are drawn. In the appendix, the CLP(CR) model of the filter circuit from the case study is presented.

2. Modeling Analog Circuits with CLP(CR)

2.1. The CLP(CR) Language

Constraint logic programming [16, 17] is a generaliza­tion of logic programming. Unification, the basic opera­tion in logic programs, is replaced by a more general mechanism of constraint satisfaction over a specific computation domain. An instance of the general CLP scheme is obtained by selecting a computation domain, a set of allowed constraints and designing a solver for the constraints. CLP combines the advantages of logic programming (declarative semantics, nondeterminism, partial answers) with the efficiency of specialized con­straint satisfaction algorithms. CLP(CR) is an instance of the CLP scheme wh.ich extends logic programs with interpreted arithmetic functions and a solver for systems of linear equations and inequalities over the domain of CReals.

A CLP(CR) program is a set of clauses of the form

and a CLP(CR) query is a clause without head:

where H is an atom and Ci are negated or nonnegated atoms or arithmetic constraints. Arithmetic constraints are equations or inequalities, built up from real con­stants, variables, +, -, *, / and =, ~, ::S, >, < where all of these symbols have the usual meaning and parentheses may be used. An atom is a predicate sym­bol applied to a number of terms. A term is a constant, a variable, an uninterpreted functor applied to a number of terms, or an arithmetic term. Variables start with capitals and are implicitly universally quantified in front of a clause, and constants start with lowercase letters.

We illustrate the CLP(CR) language by specifying ad­dition and multiplication of complex numbers. A com­plex number Z = Re+j*Im is represented by a pair c(Re,Im).

Enhancing Design-for-Test for Active Analog Filters 317

add( c(Rel,lml) , c(Re2,lm2), c(Rel +Re2, 1m1 +1m2) ). mutt( c(Rel,lml), c(Re2,lm2), c(Re,lm) ) <­

Re = Re1*Re2 - Im1*lm2, 1m = Rel*lm2 + Iml*Re2.

The above program allows for queries involving not only addition and multiplication, but subtraction and division of two complex numbers as well. For example:

<- mult( c(l,2), c(3,4), Z ). Z = c(-5,1O) <- mutt( X, c(3,4), c(-5,1O) ). X = c(l,2)

Answering the second query actually requires to solve the following system of equations:

3*Rel - 4*lml = -5, 4*Rel + 3*lml = 10.

which yields the solution Rel=l, Iml=2.

2.2. Modeling Analog Circuits

The purpose of this subsection is to show how analog circuits can be modeled by CLP(CR). We take a simple example of two resistors in a series (from McKeon and Wakeling [8]). First we show how the CLP(CR) capabil­ity to solve systems of inequations can be used to model parameter tolerances. Then we illustrate how the same CLP(CR) model is used not only for prediction, but also for diagnosis. When the measured voltage is out of the expected range, CLP(CR) computes values of suspected resistors which differ from the nominal values. This forms the basis for the isolation of soft faults in more complicated analog circuits.

A model of a system is a triple (SD, COMPS, OES) where

1. SD, the system description, is a CLP(CR) program with a distinguished top-level binary predicate model(COMPS, OES) which relates states of the system components to observations.

2. COMPS, states of the system components, is an n­tuple (SI' ... , Sn) where n is the number of com­ponents, and variables Si denote states (e.g., nor­mal or abnormal) of components.

3. OES, observations, is an m-tuple (PI, ... , Pi, 1ni+l' ... , Inj' Outj+l , •.• , Outm ) where P are the model parameters, and In and Out denote inputs and outputs of the model, respectively. We consider a model of two resistors in a series,

with voltages of 12.5 and 10 V applied at the ends (an

example from McKeon and Wakeling [8]). Both resistances are within the range i(JOOO, 20(0) n. The first question is: what is the voltage range at the node between the two resistors?

SD of the model consists of the following CLP(CR) program. COMPS is a pair comps(Rl,R2), where Ri denote states of resistors: ok when the resistance is within the nominal range, and ab(R) otherwise. OES is a pair obs(V,l), where V is the voltage at the node between the two resistors and I is the current through the resistors.

modele comps(Rl,R2), obs(V,l) ) <­

VI = 12.5, V2 = 10, resistor( Rl, i(I000,2000), VI, V, 1 ), resistor( R2, i (1000,2000) , V, V2, I).

resistor( ok, R, VI, V2, I) <- R*I = VI-V2. resisLOr( ab(R), _, VI, V2, I ) +- R*I = Vl- V2.

The model relates states of the resistors to the voltage and the current. Atoms in the body of the first clause represent models of resistors which enforce local con­straints between voltages and currents (Ohm's law). Shared variables represent connections between the components and enforce global constraints, e.g., Kirch­hoffs law for voltages. The last two clauses define behavior of a resistor for the case when it is normal, and when it is out of tolerances, respectively.

The following query asks for the voltage and cur­rent, under the assumption that both resistors are ok, i.e., within the allowed tolerances:

+- modele comps(ok,ok), obs(V,I) ), inf(V, Vmin) , sup (VYmax).

V ::; 10.0 + 2000.0*1, V ::; 12.5 - 1000.0*1, V ~ 12.5 - 2000.0*1, V ~ 10.0 + 1000.0*1, Vmin = 10.833333333333334, Vmax = 11. 666666666666666

CLP(CR) returns a set of inequalities as an answer, and also computes infimum and supremum of the voltage between the two resistors. In contrast to our, symbolic approach, McKeon and Wakeling use an iterative, numeric approach to compute the voltage range.

Now assume that the actual, measured voltage is 12 V, i.e., it is outside of the predicted range. This in­dicates that at least one of the resistors is faulty, i.e., its resistance must be out of the allowed tolerances. We make a single fault assumption and use the same

318 Novak, et al.

CLP(CR) model to compute the resistance of a suspected resistor. The following two queries return lower and upper bounds for resistances of suspected faulty resistors. Note that each query has two possible answers, corresponding to two possible faults:

+- modele comps(Rl,R2), obs(12,I) ), maximizer/).

I = 0.0005, Rl = ok, R2 = ab(40oo.0) ; I = 0.002, Rl = ab(250.0), R2 = ok

+- modele comps(Rl,R2), obs(12,I) ), minimizer/).

I = 0.00025, Rl = ok, R2 = ab(8000.0) ; I = 0.001, Rl = ab(500.0) R2 = ok

Table I summarizes the results of diagnosis. The ex­ample illustrates the basic idea of using CLP(CR) to diagnose soft faults. In our experiments with filters we do not take parameter tolerances into account. However, instead of one we take several measurements, and com­bine the computed values of suspected faulty com­ponents in order to rank them in decreasing likelihood of being faulty.

Table J. Computed actual values of poten­tially faulty resistors.

Suspected Computed Component Value (0)

Rl 250-500 K2 4000-8000

CLP(CR) is restricted to systems of linear equations and inequalities. Nonlinear constraints are accepted but not resolved-they are just delayed until (if) they even­tually become linear. In order to make CLP(CR) ap­plicable to the diagnosis of analog circuits we have to make some assumptions. We have to restrict models to linear or piecewise linear circuits, and assume that there are no multiple faults (a single-fault assumption). In the next subsection we give a formal argument which shows that under those assumptions, linear CLP(CR) is indeed sufficient for the diagnosis of soft faults.

2.3. Application of the Node-Analysis Method

In our approach, the CLP(CR) model is based on the node-analysis method. Thus the unknown quantities are node potentials. Let an electric circuit have n nodes and b branches. One of the nodes of the circuit may be grounded without affecting any potential differences across the nodes bounding the branch. The node­analysis method represents the circuit by three indepen­dent matrix equations:

Aj = 0

v = ATe

j = Yv

where the variables denote

• j current vector • e vector of the node potentials • v voltage vector • Y admittance matrix

The first matrix equation represents the Kirchhoffs cur­rent law. The second equatioD determines voltages across the branches of the circuit and is implicitly con­tained in the CLP(CR) model. The last equation represents the Ohm's law for all the branches.

2.3.1. Simulation of a Circuit with Voltage Input. Assume that an external voltage source is added to the circuit (see figure 1). The Kirchhoffs current law equa­tion must be modified to include the source current, which is an additional unknown quantity. The system gets an additional equation related to the input voltage.

iin iout ep e+ r

j Zj ek~el u~l

+

iu," + ~ -U j

eq e,

Fig. J. Electric circuit including suspected component Zj.

Aj + Biin = 0

V = ATe

j = Yv

BTe = uin

Enhancing Design-for-Test for Active Analog Filters 319

The system of equations can be rearranged to

AY ATe + Biniin = 0

where iin represents the source current, and Uin the source voltage, respectively. The matrix Bin specifies the nodes to which the source is connected. The resulting system is a system of n linear equations with n unknown quantities. The output voltage can be easily calculated from the resulting node potential by

Uout = B~ul!

2.3.2. Determining the Value of a Component in Terms of the Known System Input and Output Voltages. We have shown how to determine the system output voltage in terms of the known voltage input. In diagnosis of soft faults, however, is our main interest in determining the value of particular component in terms of the known voltage input (stimulus) and the out­put voltage (measurement) (see Figure 2). We have to show that this problem can be described by a system of linear equations which yield a unique solution. Let Ai be the ith column of A.

til

loutiin e e ++ p r

e. e,1u

," uo·1 e q e,

Fig. 2. Electric circuit with suspected component Zj separated.

A = (AI> Az, ... , Ab)

Accordingly, the admittance matrix is

Y=

Let the unknown component be Zj. The component Zj is first taken out of the circuit and considered separately from the rest of it. Now the circuit has n

nodes (no node deleted) and b - 1 branches (branch i was drawn out). The new matrix A* is

A* = (AI> Az, ... , Ai-I> Aj+1> ... , Ab)

and the new admittance matrix is

Y1 0 0 0 0 0 Yz 0 0 0

Y= 0 0 Yi- 1 0 0 0 0 0 Y;+l 0

0 0 0 0 Yb

The new curent vector J* does not contain the current };.

Two additional currents must be added to the Kirch­hoffs current law: the source current and the current through the unknown component. The output current is O.

A* J* + AiJi + Biniin = 0

J* = y* v*

v* = A*Te

The system has two additional equations corresponding to the source voltage and to the output voltage. The resulting equations are

A*Y* A*T e + A;}; + Biniin = 0

BTn e = Uin

B~ute = UOUI

This is a system of linear equations and can be solved by CLP(CR). The value of the unknown component can be easily calculated by

ATeZj = _,_ Ji

3. DFf Methodology for Active Analog Filters

In our earlier work [9] we made an introductory study of automated fault diagnosis of analog circuits by means of CLP(CR). Promising initial results on a rela­tively simple analog circuit have been obtained. Next we have tried to apply the approach to more complex circuits, in particular in the domain of active ana­log filters in which we have gathered most practical

320 Novak, et al.

experiences. We have found that the DFT methodology for active analog filters proposed by Soma [10] can be enhanced and operationalized by using CLP(<R). In other words, CLP(<R) provides means for automatic fault diagnosis of active analog filters designed in ac­cordance with the proposed DFT methodology.

The main idea of the referred DFT methodology is to introduce MOS switches to individual stages of a filter circuit in order to increase its controlIability and observability. The modified filter circuit can be tested in the following modes of operation:

• Normal mode (switches initialized such that all DFT transformations are disabled)

• Individual stage test (switches set to increase con­trollability and observability of each individual stage-under-test)

• All-test mode (switches set to disconnect all the capacitors in the circuit)

10k

ilL

Fig. 3. Low-pass biquad filler designed for testability.

As an example, consider, th~filter circuit shown in figure 3. Switches T j , Tz, and Tz have been introduced for the DFT purposes. Their states in individual opera­tion modes are as follows:

• Normal mode: T1 ON, Tz ON • First-stage test: Tz OFF (Cz disconnected), T) ON,

Tz ON • Second-stage test: T) OFF (C j disconnected), Tz

ON, Tz OFF • All-test mode: T1 OFF, Tz OFF, Tz ON

The fault isolation procedure described in [10] in­cludes a variety of techniques that may prove useful in achieving the goal. However, given examples and case studies do not offer a unique way toward fault isola­tion. They are rather used to illustrate the rich set of possibilities available to the designer when trouble­shooting a filter circuit that has been designed for testability.

In our approach, we use the same modes of opera­tion of the DDT as proposed by Soma [10], yet we restrict the measurements to the case where measure­ment results can be fed directly to the CLP(<R) system in order to perform the fault isolation process automatically.

3.1. Fault Isolation

After satisfactory simulation results for the fault-free circuit operation in the normal mode are obtained, (i.e., correctness of the model is confirmed) the process of deriving diagnoses proceeds in the following way.

For a given fault situation, measurements of gain and phase at seleced test frequencies are performed on the experimental filter circuit. The results are compared to the simulated fault-free circuit output under the same input stimuli. If a fault is detected, a list of suspected faulty circuit components is given to the CLP(<R) system which computes the deviating values of the sus­pected components that might have caused the mea­sured faulty circuit output. The values are computed for the normal mode, all-test mode, and each individual stage test mode, respectively. The mean value x and coefficient of variation V (i.e., normalized standard deviation, six) are computed for each suspected com­ponent in each operation mode, and for the composite case.

The next step is to reduce the list of suspected components.

• Components with computed negative values are ruled out.

• Components with large value of V are ruled out. • Analysis of the all-test mode is performed in order

to find out if the faulty component is a resistor or a capacitor.

• In the remaining list, the components with minimum value of V are declared as potentially faulty.

In the next section we describe some typical fault situations and show how the conclusions of the circuit diagnosis are drawn from the results of computation of the CLP(<R) system.

4. Experimental Results

The low pass biquad filter, shown in figure 3, has been implemented for experimental purposes in thick-film hybrid technology. LS404C operational amplifiers and

Enhancing Design-for-Test for Active Analog Filters 321

HEF4066B MOS switches were employed. HP4192 LF Impedance Analyzer was used for measuring gain and phase values in the range of 5 Hz-lO kHz (see figure 4). CLP(CR) simulations were performed on a SUN SPARCstation IPC. The CLP(CR) model of the filter is given in the appendix.

Comparison with the measurements has shown that simulated values are close to the measured within less than 5%.

Faull-Frc:t 20~----

secund stage ltSIO~_.~·20 .

<lll-lesl mode~ ...... J-40 - .

j . firs! stage lest

·60­

'0' Frequency IHzJ

180----==------_.._-.... -"~-""-", . all-lest mode

160 \ "" second ~lage It;:SI

'40

120 \ .............. "J

first slilge It:st 100 It t

£ 80

\60 I

40, \ 20e ~ normo) mock __---~

~--,,:;;;O'-~--.:::-=--IU'-','b\ Frequency 1Hz)

Fig. 4. Gain and phase characteristics for the tour operation modes.

4.1. Example 1: C, Faulty

In this example we have inserted a capacitor C j with I of instead of the correct 100 of into the circuit. Table 2 gives the measured values of gain and phase at selected frequencies of 100 Hz and 200 Hz for the four possible modes of circuit operation with C, = 1 nF. Table 3 presents the computed mean values i of suspected faulty components together with the cor­responding coefficients of variation V for the given operation modes.

Inspection of coefficients of variation V for the nor­mal mode immediately points to C t as being faulty

because it has minimum V and its value differs by an order of magnitude from the others. Although the result is achieved in the first step we proceed by the other three in order to illustrate the process of deriving the diagnosis as well as to confirm the initial result.

Resistor R4 can be ruled out as a fault candidate due to the large value of V in the normal mode. Simula­tion results of the fault-free circuit in the all-test mode are close to the measured values (table 2), hence no further element can be ruled out at this step. The situa­tion implicitly indicates that fault can be expected in C j or C2 since the circuit operates correctly in the all­test mode where the capacitors are inactive.

Computed values for the first stage test mode in­dicate that R3 is no longer a candidate of being faulty due to its large value of V.

The results of computation for the second stage test mode show equal values of V for the remaining suspected elements, except for C t which is excluded at this specific measurement situation. Again, the measured values are close to the simulated fault-free circuit (table 2), which implicitly indicates that C t is the probable faulty element.

Table 4 gives the composite average values for the four circuit modes. Here again is the coefficient of variation Vof C, by an order of magnitude lower than the other values which confirms previously stated diagnosis. Notice also, that the computed value of C t

closely resembles the actual value of the inserted fault in the experimental circuit.

4.2. Example 2: R3 Faulty

For the second experiment the circuit is modified so that R3 is 1 ldl instead of correct 10 ldl. The measured values for this case are given in table 5, computed values of the potentially faulty components in table 6, and final average values in table 7, respectively.

Due to the negative values computed for the nor­mal mode, R2, Rs, R6, C" and C2 are ruled out. From the remaining candidates, R3 seems to be the most probable fault because it has the smallest value of V. At the same time, computed value of R3 = 1001 n matches the actual value in the modified circuit.

In order to confirm the diagnosis we proceed with the remaining test modes.

Measurement results of the all-test mode indicate that the faulty element is one of the resistors. Com­puted values V for the all-test mode are all close to zero and no further conclusion can be drawn. Likewise,

322 Novak, et at.

Table 2. Measured gain and phase for C. 1 nF.

Gain Phase Frequency Gain Phase Difference Difference

Modes (Hz) (dB) (deg) (dB) (deg)

Normal 100 -13.957 176.34 -4.29 2.53 mode 200 -13.904 172.65 -4.40 158.20

All-test 100 -40.40 -178.92 -1.48 0.11 mode 200 -40.43 179.9 -1.50 -0.02

1st-stage 100 -40.45 176.57 14.05 76.80 test 200 -40.52 176.57 19.91 77.71

2nd-stage 100 -13.993 176.36 0.00 -0.04 test 200 -14.049 172.79 0.00 0.05

Table 3. Computed values of suspected components for C1 = I nF.

Suspected Normal Mode All-Test Mode First-Stage Test Second-Stage Test

Components n,nF V n,nF V n,nF V n,nF V

R1 1546 0.876 83435 0.002 1832 0.862 99083 0.003 R2 277 0.497 11985 0.002 313 0.483 10092 0.003 R3 5548 0.419 2323 0.011 1 1.388 10006 0.000

14 2369 41.420 59352 0.002 1668 0.504 49970 0.000 Rs 277 0.495 11985 0.002 313 0.483 10092 0.003 R6 21202 0.431 8343 0.002 16974 0.435 9908 0.003 C1 1.16 0.063 x x 1.21 0.021 x x C2 2.71 0.507 x x x x 1.01 0.003

Table 4. Average values for C, I nF.

Suspected Faulty Component Computed Mean Value Coefficient of Variation

1.19 14107 4470 5667 5667

46474 5.18

28340

0.045 0.506 0920 1.021 1.021 1.039 1.094 1.801

Table 5. Measured gain and phase for R) = 1 kn.

Gain Phase Frequency Gain Phase Difference Difference

Modes (Hz) (dB) (deg) (dB) (deg)

Normal 100 -33.627 179.60 -23.94 5.80 mode 200 -32.47 179.0 -22.97 164.55

All-test 100 -43.52 179.86 -4.59 -0.10 mode 200 -43.54 179.63 -4.61 -0.293

1st-stage 100 -56.37 104.34 -1.86 4.56 test 200 -61.63 79.09 -1.19 1.86

2nd-stage 100 -33.983 179.23 -20.00 3.22 test 200 -33.98 172.79 -19.92 6.39

Enhancing Design-for-Test for Active Analog Filters 323

Table 6. Computed values of suspected components for R3 = I HI.

Normal Mode AlI-Test Mode First-Stage Test Second-Stage Test Suspected

Components O,nF V O,nF V O,nF V O,nF V

R 1 18 0.837 57422 0.001 31224 0.160 19 0.860 R2 -129030 0.905 17413 0.001 11904 0.052 1496 0.018 R3 1001 0.0004 749 0.003 161 0.392 999 0.000 R4 52706 19.615 84954 0.001 59541 0.052 495708 0.008 Rs -129201 0.905 17413 0.001 11904 0.052 15032 0.017 R6 -1292 0.912 5742 0.001 8379 0.056 1.8 0.860 C1 -1316 0.910 x x 118 0.045 x x

~ -1315 0.911 x x x x 450 0.027

computed values for the first- and the second-stage test modes do not contribute to the final diagnosis. The average values of V given in table 7 indicate that R3

is the most probable cause of malfunctioning. The mean value of R3 is equal to 728 O. Although less precise, the calculated value closely resembles the ac­tual situation in the circuit.

So far, experimental results and CLP(ffi) computa­tions were made only for two selected frequencies. While it is desirable to keep the amount of experimental and computational work at minimum, more complex circuits would clearly require more measurements in order to compute reliable diagnosis. Implementation of an algorithm for choosing proper measurement fre­quencies for a given UUT remains one of the future directions of our work. Just to get the impression how the measurements at the two selected frequencies reflect the situation for a successful fault isolation, ad­ditional measurements were made at 160 Hz. Com­puted results for the three frequencies are given in table 8. In this particular case the results are only slightly improved.

4. 3. Example 3: Rs Faulty

In the last experiment, we inserted a deviation fault of Rs (100 kO instead of correct 10 kO) into the circuit. Like in previous examples, measurement results (table 9), computed values of the assumed components for

Table 7. Average values for R3 = I kO.

the four modes of operation (table 10), and computed average values (table 11) are given.

From the computed values of components for the normal mode, R3 can be eliminated due to its negative value. R I and ~ are the next candidates to be ruled out because of higher values of V.

The difference between the measurement results and the simulated values of gain and phase in the all-test mode indicate that the faulty element is one of the resistors.

Computed values of V in the first-stage test mode confirm that R) can be eliminated as well as R3.

R2, Rs, and R6 remain candidates also after inspect­ing the values in table 11. The explanation can be found in the expression of the transfer function of the filter circuit, where the three resistors always appear in the same subexpression.

5. Conclusion

Achieved results show that the model-based diagnosis with CLP(ffi) can be used in automatic fault isolation of active analog filters designed in accordance with the proposed DFT methodology [10]. Although the results refer to a narrow problem domain, the applicability of the model-based approach to more general cases is by no means excluded. From the presented examples, der­ivation of a formal fault diagnosis algorithm is straight­forward. So far, test frequencies were determined by the designer, and nominal values of the components of

Suspected Faulty Component Computed Mean Value Coefficient of Variation

728 22171

3207 -599

173227 -432

-21186 -21167

0.504 1.160 1.338 1.801 2.532 2.850 3.771 3.775

324 Novak, et at.

Table 8. Average values (at three selected frequencies) for R3 = I kn.

Suspected Faulty Component Computed Mean Value Coefficient of Variation

729 21946

3214 -510

142714 -349

-16981 -16963

0.492 1.142 1.302 1.750 2.750 2.963 4.030 4.034

Table 9. Measured gain and phase for Rs = 100 kn.

Gain Pbase Frequency Gain Phase Difference Difference

Modes (Hz) (dB) (deg) (dB) (deg)

Normal 100 -17.987 52.27 - 8.31 -121.53 mode 200 -37.57 5.87 -28.06 -8.57

All-test 100 -58.49 -179.33 -19.56 -359.29 mode 200 -58.49 179.82 -19.56 -0.10

1st-stage 100 -74.47 103.27 -19.89 3.49 test 200 -77.98 80.24 -17.54 -14.98

2nd-stage 100 -15.448 J47.63 -1.450 -28.77 test 200 -18.161 128.47 -4.106 -44.37

Table 10. Computed values of suspected components for Rs = 100 kn.

Normal Mode All-Test Mode First-Stage Test Second-Stage Test Suspected

Components n,nF V n,nF V n,nF V n,nF V

RJ 1008 1.296 9975 0.000 104 4.637 9914 0.000 R2 77702 0.436 100229 0.000 85783 0.212 100854 0.000 R3 -2017 0.900 66 0.000 0.6 4.786 5942 0.380 R4 591867 1.577 475525 0.000 428429 0.212 54560 0.072 Rs 77699 0.436 100230 0.000 85783 0.212 100849 0.000 R6 1280 0.327 998 0.000 1145 0.169 991 0.000 C, 767 0.471 x x 859 0.215 x x C2 779 0.423 x x x x 1005 0.002

Table 11. Average values for Rs = 100 kn.

Suspected Faulty Component Computed Mean Value Coefficient of Variation

1103 91140 91142

892 813

5250 387595

997

0.195 0.196 0.196 0.258 0.296 0.963 1.0698 3.371

Enhancing Design-far-Test for Active Analog Fillers 325

the DDT were taken in the CLP(CR) model instead of 5, A, Walker and W,E. Alexander, "Fault diagnosis in analog cir­

more realistic tolerance intervals. Implementation of cuits using element modulation," Design Test Comput" Vol. 9, No, I, pp, 19-29, 1992. an algorithm for selection of test frequencies and

6, K, Sierzega and R. Rastogi, "Model-based reasoning finds development of the CLP(CR) model including tolerance analog PCB faults," Electron. Test, pp. 26-30, March 1990, intervals are our current research work. 7, A, McKeon and A. Wakeling, "Fault diagnosis in analogue cir­

cuits using Al techniques," in Proc. lTC, pp. 118-123, 1989, 8, A. McKeon and A. Wakeling, "Model-based analogue circuit

Acknowledgments fault diagnosis," in Proc. TEST90, pp, 1-14, 1990. 9, 1. Mozeti::', C. Holzbaur, F. Novak, and M. Santo-Zarnik,

"Model-based analogue circuit diagnosis with CLP(CR)," in Franc Novak, Marina Santo-Zarnik, and Anton Bia­ Proc. 4th Int. GI Congress, Munich (W, Brauer, ed.), Springer­sizzo are supported by the Slovenian Ministry of Verlag: Berlin and New York, pp. 343-353, 1990.

Research and Technology under grants C2-1521-106 and 10. M. Soma, "A design-for-test methodology for active analog filters," Proc. lTC, pp. 183-192, 1990. Z2-0378-106. Igor Mozetic is supported by the Austrian

II. H. Veiling and M. Viktil, "Test of mixed analog/digital com­"Fonds zur Forderung der wissenschaftlichen For­ ponents by boundary scan methods," Esprit project 2478, report schung" under grant P9426-PHY. Austrian Research R8.E5. Institute for Artificial Intelligence is supported by the 12. P,P, Fasang, "Analog/digital ASIC design for testability," IEEE

Trans, Indus/, Elec/., Vol. 36, No .. 2, pp, 219-226, 1989.Austrian Federal Ministry of Science and Research. 13, K,D, Eagner and T,W, Williams, "Design for testability of

analog/digital networks," IEEE TraIlS. Indust. Elect., Vol, 36, No.2, pp, 227-230, 1989,

References 14, M, Jarwala and SJ. Tsai, "A framework fortestability of mixed

analog/digital circuits," in Proc. IEEE 1991 Cus/om Integrated I, Special issue on automatic fault diagnosis, IEEE Trans, Circuits Circuit Con!, pp. 13.5.1-13,5.4, 1991.

Syst., Vol. CAS-26, 1979, 15, M.J, Ohletz, "Hybrid built-in self-test for mixed analogue/digital 2, J,W. Bandler and A,E, Salama, "Fault diagnosis of analog cir­ integrated circuits," in Proc. ETC91, Munich, pp. 307-316,

cuits," Proc. IEEE, Vol. 73, No, 8, pp, 1279-1327, 1985. 1991. 3. RJ, Cavin and J,L. Hilbert, "Design of integrated circuits: 16, J, Jaffar and J .-L. Lassez, "Constraint logic programming,"

directions, and challenges," Proc. IEEE, Vol. 78, No, 2, in Proc. 14/h ACM Symp. Principles of Programming pp, 418-435, 1990, Languages, Munich, pp, 111-119, 1987.

4, M, Siamani, B, Kaminska, "Analog circuit fault diagnosis," 17, 1. Cohen, "Constraint logic programming languages," Comm. Design Test Comput" Vol. 9, No, 1, pp, 30-39,1992, ACM, Vol. 33, No, 7, pp, 52-68, 1990.

6. Appendix: CLP(CR) Model of the Filter Circuit

In the following we present the CLP(CR) model of the filter circuit shown in figure I.

% File: filter % I ow - pas s b i qua d f i I t e r % % A complex number Z = Re+j*lm is represented by a pair c(Re,lm). % fi Iterxyz model, xyz denotes states of switches

% fi Iterxyz considers fi Iter model and chosen operation mode

fi Iterxyz( F, VI, V2, Gain, Phase, [X,Y,Z] ) filter( comps(ok,ok,ok,ok,ok,ok,ok,ok,ok,ok,ok,X,Y,Z), F, VI, V2), gain( VI, V2, Gain), phase( V2, Phase),!,

fi Iterxyz( F, VI, V2, Gain, Phase, Test) translate_test( Test, Switches), filterxyz( F, VI, V2, Gain, Phase, Switches),

% definitions of ope rat ion modes

326 Novak, et al.

trans I ate_test ( norma I, [res, res, dis] ) . t ran s I at e_t est ( a I I t est, [d is, dis, res] ) . trans I ate_test ( stage1, [res, dis, res] ) . trans I ate_test ( stage2, [d is, res, dis] ) .

% parameters

fi Iter( Fi Iter, F, Yin, Vout ) frequeney( F, W ), R1 t (100000) , R2 t (10000) , R3 t (10000) , R4 t (50000) , R5 t ( 10000) , R6 t (10000) , C1 t (l00 Oe-9) , C2 t(l00.Oe-9), Tl t(60), T2 t(60), NT2 = t (60) , f i 1ter (Fi Iter, param(W, R1, R2 ,R3 ,R4 ,R5 ,R6,C1 ,C2, Tl, T2, NT2) ,

volt(Vin,Vout,_,_,_,_,_,_,_)), J.

% model of filter

fi Iter( eomps(SR1,SR2,SR3,SR4,SR5,SR6,SC1,SC2,SA1,SA2,SA3,ST1,ST2,SNT2), param(W,R1,R2,R3,R4,R5,R6,C1,C2,T1,T2,NT2) , volt(Vin,Vout,V1,V2,V3,V4,V5,Vt1,Vt2)) ;-

Vgnd = e(O,O), emp_add ( I 1, I b 1, I r4 ), emp_add ( 12, I r 1, 11 ), emp_add( Ir3, leI, 12), emp_add ( leI, I r 1, 13 ), amplifier( SAl, W, Vgnd, VI, V2, la1, Ib1, 101), amp I i fie r ( SA2, W, Vgnd, V3, V4, I a2, I b2, 102 ), amp I i fie r ( SA3, W, Vgnd, V5, Vout, I a3, I b3, 103 ), emp_add( 13, 101, I r2 ), emp_add( 14, Ib2, Ir2), emp_add ( 15, I e2, /4 ), emp_add( 14, 102, 1r5 ), emp_add( Ir6, Ib3, Ir5 ), emp_add( I r3, I r6, 16 ), emp_add( 103, 16, e(O,O) ), b ridge ( STl, Tl, leI, Vtl, V2 ), b ridge ( ST2, T2, I e2, Vt 2, V4 ), bridge( SNT2, NT2, 15, V3, V4 ), eapaeitor( SC2, W, C2, le2, V3, Vt2 ), eapaeitor( SCI, W, C1, leI, VI, Vtl ), resistor( SR6, R6, Ir6, V5, Vout ), resistor( SR5, R5, Ir5, V4, V5 ), resistor( SR2, R2, Ir2, V2, V3 ), resistor( SR4, R4, I r4, Yin, VI ), resistor( SRI, R1, Ir1, VI, V2 ), resistor( SR3, R3, Ir3, VI, Vout ).

%-----------------models of eomponents------------------ ­

% model of MOS switches

Enhancing Design-for-Test for Active Analog Filters 327

bridge( shrt, _, _, v, V). bridge( dis, _ c(O,O), ) . bridge( res, R, I, VI, V2 ) : ­

resistor( ok, R, I, VI, V2).

% model of operational ampl ifier (LS204)

amplifier( ok, W, Vina, Vinb, Vout, lina, linb, lout) AO = pow(10,5/3), Rin = 0.5e6, R3 = 75, Voff = 0.0, Ibias 0.0, loff 0.0, F1 25, F2 = 1. Oe6 R1 = 1000, R2 = 1000, constanLpi( Pi ), C1 1/(2*Pi*R1*F1), C2 = 1/(2*Pi*R2*F2), C3 = 1.0e-12, cmp_add( Vina, c(Voff,O), Va ), resistor( ok, t(Rin), Ir, Va, Vinb ), cmp_add ( I r, c ( I bias, 0), I ina ), cmp_a dd ( linb, I r, c ( I b i as - I 0 f f , 0) ), cmp_add ( VO, Vi nb, Va ), stage( AO, VO, R1, C1, W, c(O,O), VI ), stage( AO, VI, R2, C2, W, c(O.O), V2 ), stage( AO, V2, R3, C3, W, lout, Vout ).

stage( AO, VO, R, C, W, I, V Vgnd = c(O,O), cmpJrlu I Lrea I ( i (AO/R), VO, Is), resistor( ok, t(R), Ir, Vgnd, V), capacitor( ok, W, t(C), Ic, Vgnd, V ), cmp_add ( Is, I r, Is r ), cmp_add ( Is r, I c, I ).

% model of resistor

resistor( ok, t(R), I, VI, V2) cmp_add( DV, V2, VI ), cmpJrlu I Lrea I ( i (R), I, DV ).

% model of capacitor

capacitor( ok, W, t(C), I, VI, V2 cmp_add( DV, V2, VI ), cmpJrlu I Limag( i (C*W) , DV, I ).

%- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ­

% definition of constant_pi

constanLpi( 3.14159).

% computation of W, Gain and Phase

frequency( F, 2*Pi*F) :- constant_pi ( Pi ).

gain( c(Re1,lm1), c(Re2,lm2), Gain) : ­pow(10,G) = (Re2*Re2+lm2*lm2)*(1/(Re1*Re1+lm1*lm1», Gain = 10*G.

328 Novak, et al.

ph as e ( c (0 ,_), ° ) :- !. phase ( c (Re, 1m). Phase )

Re>O, !, con s tan t _p i ( Pi), tan(Rad) = Im*(l/Re), Phase = l80/Pi*Rad.

phase( c(Re, 1m), Phase Re<O, con s tan t _p i ( Pi), tan(Rad) = Im*(l/Re), Phase = l80/Pi*Rad + 180.

%-----------Fault model----------------------- ­

% Faulty resistor

resistor( ab(R), _, I, VI, V2 cmp_add ( DV, V2, VI ), cmp-lTlu I t ( c ( i (R) ,_), I, DV ).

% Faulty capacitor

capacitor( ab(C), W, _, I, VI, V2 cmp_add( DV, V2, VI ), cmp-lTlul t ( c(_, i (C*W» , DV, I ).

%- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ­

% Complex numbers, addition and multipl ication

cmp_add( c(Rel,lml), c(Re2,lm2), c(Rel+Re2,/ml+lm2».

cmp-lTlult( c(Re,lm), CmpO, Cmp) : ­cmp-lTlult_real ( Re, CmpO, Cmpl ), cmp-lTluICimag( 1m, CmpO, Cmp2), cmp_add( Cmpl, Cmp2, Cmp ).

cmp-lTluICreal( Int, c(ReO,lmO), c(Re,lm» i nt -lTlU I t ( I nt, ReO, Re ). i n t -lTlU I t ( I nt, I mO , 1m).

cmp-lTluILimag( Int, c(ReO,lmO), c(-Re,lm» i n t -lTlU I t ( I nt, ReO, 1m), int-lTlult( Int, ImO, Re).

Enhancing Design-for-Test for Active Analog Filters 329

Franc Novak gained the B.Sc., M.Sc. and Ph.D. degrees in elec­trical engineering from the Unive~ity of Ljubljana, Slovenia, in 1975, 1977, and 1988, respectively. Since 1975 he has been with the Institute Joief Stefan, where he is currently head of a research laboratory. He is also an associate professor at the University of Ljubljana. His research interests include electronic testing and diagnosis, VLSI design, and mult-tolerant computing.

Igor Mozetic is a senior research fellow at the Austrian Research Institute for Artificial Intelligence in Vienna, Austria. He holds a Ph.D. in computer science from the Unive~ity of Ljubljana, Slovenia (1988). He participated in the KARDIO project, where he was the principal designer of the qualitative model of the heart. He was a research assistant at the Joief Stemn Institute, Slovenia (1980-88), a visiting Fulbright scholar at the University of Illinois at Urbana­Champaign (1984-86), and a visiting assistant professor at George Mason University, VA (1988-89). His main research interests are in the areas of model-based reasoning, constraint logic programming, and machine learning.

Marina Santo-Zarnik received the B.Sc. degree in electrical engineering and the M.Sc. degree in computer science from the Unive~ity of Ljubljana, Slovenia, in 1982 and 1993, respectively. Since 1982 she has been working in a collaborative R&D team of Iskra HlPaf, Sentjernej, and Joief Stemn Institute, Ljubljana, mainly on the development and the design of thick-film hybrid circuits. In recent yea~, her main interests are in the area of testing and fault diagnosis of analog circuits.

Anton Biasizzo received the B.Sc. degree in electrical engineering from the University of Ljubljana in 1991, and he is currently work­ing toward the M.Sc. degree in the field of electronic design and test. He is a research assistant at Joief Stefan Institute. His research in­terests are built-in self-test, design for testability, and analog and mixed circuit diagnosis.