ENGR 303 – Introduction to Logic Design Lecture 6

Dr. Chuck BrownEngineering and Computer Information Science

Folsom Lake College

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• Digital Building Blocks

• Full Adder

• Ripple Carry Adder

• Carry Look Ahead Adder

• Prefix Adder

• Subtractor

Outline for Todays Lecture

ENGR 303

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• Digital building blocks:– Gates, multiplexers, decoders, registers,

arithmetic circuits, counters, memory arrays, logic arrays

• Building blocks demonstrate hierarchy, modularity, and regularity:– Hierarchy of simpler components

– Well-defined interfaces and functions

– Regular structure easily extends to different sizes

• Will use building and hierarchy to build microarchitecture in lab

Introduction

ENGR 303

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A B

0 0

0 1

1 0

1 1

SCout

S =

Cout

=

Half

Adder

A B

S

Cout +

A B

0 0

0 1

1 0

1 1

SCout

S =

Cout

=

Full

Adder

Cin

0 0

0 1

1 0

1 1

0

0

0

0

1

1

1

1

A B

S

Cout

Cin+

1-Bit Adders

ENGR 303

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A B

0 0

0 1

1 0

1 1

0

1

1

0

SCout

0

0

0

1

S =

Cout

=

Half

Adder

A B

S

Cout +

A B

0 0

0 1

1 0

1 1

0

1

1

0

SCout

0

0

0

1

S =

Cout

=

Full

Adder

Cin

0 0

0 1

1 0

1 1

0

0

0

0

1

1

1

1

1

0

0

1

0

1

1

1

A B

S

Cout

Cin+

1-Bit Adders

ENGR 303

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A B

0 0

0 1

1 0

1 1

0

1

1

0

SCout

0

0

0

1

S = A B

Cout

= AB

Half

Adder

A B

S

Cout +

A B

0 0

0 1

1 0

1 1

0

1

1

0

SCout

0

0

0

1

S = A B Cin

Cout

= AB + ACin

+ BCin

Full

Adder

Cin

0 0

0 1

1 0

1 1

0

0

0

0

1

1

1

1

1

0

0

1

0

1

1

1

A B

S

Cout

Cin+

1-Bit Adders

ENGR 303

Verilogmodule fulladder (input a, b, cin,

output reg s, cout);reg p, g;always @ (*)

begin p <= a^ b;g <= a & b;s <= p ^ cin;cout <= g | (p & cin);

endendmodule

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A B

S

Cout

Cin+

N

NN

• Types of carry propagate adders (CPAs):

– Ripple-carry (slow)

– Carry-lookahead (fast)

– Prefix (faster)

• Carry-lookahead and prefix adders faster for large adders

but require more hardware

Symbol

Multibit Adders (CPAs)

ENGR 303

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S31

A30

B30

S30

A1

B1

S1

A0

B0

S0

C30

C29

C1

C0

Cout ++++

A31

B31

Cin

• Chain 1-bit adders together

• Carry ripples through entire chain

• Disadvantage: slow

Ripple-Carry Adder

ENGR 303

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tripple = NtFA

where tFA is the delay of a 1-bit full adder

Ripple-Carry Adder Delay

ENGR 303

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• Compute carry out (Cout) for k-bit blocks using generate and

propagate signals

• Some definitions:

– Column i produces a carry out by either generating a carry out or

propagating a carry in to the carry out

– Generate (Gi) and propagate (Pi) signals for each column:

• Column i will generate a carry out if Ai AND Bi are both 1.

Gi = Ai Bi• Column i will propagate a carry in to the carry out if Ai OR Bi is 1.

Pi = Ai + Bi• The carry out of column i (Ci) is:

Ci = Ai Bi + (Ai + Bi )Ci-1 = Gi + Pi Ci-1

Carry-Lookahead Adder

ENGR 303

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• Step 1: Compute Gi and Pi for all columns

• Step 2: Compute G and P for k-bit blocks

• Step 3: Cin propagates through each k-bit

propagate/generate block

Carry-Lookahead Addition

ENGR 303

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• Example: 4-bit blocks (G3:0 and P3:0) :

G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 )

P3:0 = P3P2 P1P0

• Generally,

Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj )

Pi:j = PiPi-1 Pi-2Pj

Ci = Gi:j + Pi:j Cj-1

Carry-Lookahead Adder

ENGR 303

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B0

++++

P3:0

G3

P3

G2

P2

G1

P1

G0

P3

P2

P1

P0

G3:0

Cin

Cout

A0

S0

C0

B1

A1

S1

C1

B2

A2

S2

C2

B3

A3

S3

Cin

A3:0

B3:0

S3:0

4-bit CLA

BlockC

in

A7:4

B7:4

S7:4

4-bit CLA

Block

C3

C7

A27:24

B27:24

S27:24

4-bit CLA

Block

C23

A31:28

B31:28

S31:28

4-bit CLA

Block

C27

Cout

32-bit CLA with 4-bit Blocks

ENGR 303

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For N-bit CLA with k-bit blocks:

tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA

– tpg : delay to generate all Pi, Gi

– tpg_block : delay to generate all Pi:j, Gi:j

– tAND_OR : delay from Cin to Cout of final AND/OR gate in k-bit CLA

block

An N-bit carry-lookahead adder is generally much faster than a

ripple-carry adder for N > 16

Carry-Lookahead Adder Delay

ENGR 303

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• Computes carry in (Ci-1) for each column, then

computes sum:

Si = (Ai Bi) Ci

• Computes G and P for 1-, 2-, 4-, 8-bit blocks, etc.

until all Gi (carry in) known

• log2N stages

Prefix Adder

ENGR 303

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• Carry in either generated in a column or propagated from a

previous column.

• Column -1 holds Cin, so

G-1 = Cin, P-1 = 0

• Carry in to column i = carry out of column i-1:

Ci-1 = Gi-1:-1

Gi-1:-1: generate signal spanning columns i-1 to -1

• Sum equation:

Si = (Ai Bi) Gi-1:-1

• Goal: Quickly compute G0:-1, G1:-1, G2:-1, G3:-1, G4:-1, G5:-1,

… (called prefixes)

Prefix Adder

ENGR 303

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• Generate and propagate signals for a block spanning bits i:j:

Gi:j = Gi:k + Pi:k Gk-1:j

Pi:j = Pi:kPk-1:j

• In words:

– Generate: block i:j will generate a carry if:

• upper part (i:k) generates a carry or

• upper part propagates a carry generated in lower part

(k-1:j)

– Propagate: block i:j will propagate a carry if both the

upper and lower parts propagate the carry

Prefix Adder

ENGR 303

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0:-1

-1

2:1

1:-12:-1

012

4:3

3

6:5

5:36:3

456

5:-16:-1 3:-14:-1

8:7

7

10:9

9:710:7

8910

12:11

11

14:13

13:1114:11

121314

13:714:7 11:712:7

9:-110:-1 7:-18:-113:-114:-1 11:-112:-1

15

0123456789101112131415

Bi

Ai

Gi:i

Pi:i

Gk-1:j

Pk-1:j

Gi:k

Pi:k

Gi:j

Pi:j

ii:j

Bi

Ai

Gi-1:-1

Si

iLegend

Prefix Adder Schematic

ENGR 303

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tPA = tpg + log2N(tpg_prefix ) + tXOR

– tpg: delay to produce Pi Gi (AND or OR gate)

– tpg_prefix: delay of black prefix cell (AND-OR gate)

Prefix Adder Delay

ENGR 303

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Compare delay of: 32-bit ripple-carry, carry-lookahead, and

prefix adders

• CLA has 4-bit blocks

• 2-input gate delay = 100 ps; full adder delay = 300 ps

Adder Delay Comparisons

ENGR 303

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Compare delay of: 32-bit ripple-carry, carry-lookahead, and

prefix adders

• CLA has 4-bit blocks

• 2-input gate delay = 100 ps; full adder delay = 300 ps

tripple = NtFA = 32(300 ps)

= 9.6 ns

tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA

= [100 + 600 + (7)200 + 4(300)] ps

= 3.3 ns

tPA = tpg + log2N(tpg_prefix ) + tXOR

= [100 + log232(200) + 100] ps

= 1.2 ns

Adder Delay Comparisons

ENGR 303

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Symbol Implementation

+

A B

-

YY

A B

NN

N

N N

N

N

Subtractor

ENGR 303

Verilogmodule subtractor #(parameter N = 8)

(input [N-1:0] a, b, output [N-1:0] y);

assign y = a – b;endmodule