ENGN3213 Digital Systems and Microprocessors Sequential...

ENGN3213 Digital Systems andMicroprocessors

Sequential Circuits

1 ENGN3213: Digital Systems and Microprocessors L#9-10

Why have sequential circuits?

➤ Sequential systems are serial devices - many systems are serial (e.g.linear time varying systems such as filters)

➤ Memory is time serial

➤ Bit serial devices can replace many combinational circuits.

- truth tables can be expensive to implement. If you have plenty of timethen one could replace complex hardware with stateful hardware (Reverse

Polish Calculator!)

➤ Finite State Machines


Sequential Devices: What is sequential?

➤ In a sequential device the result is only transferred to the output at theactive edge of a clock.


Modelling sequential circuits in Verilog


VERILOG TIP 1: Unwanted latches in VERILOG Synthesis

➤ A reg keeps the value of its last assignment until it is assigned to again. If areg is assigned to on some path of execution through an always block butnot on all paths, it behaves as a latch.

➤ Make sure that non-latch reg variables are assigned to through every path- both arms of ifs, and all arms of cases. A case should have a default evenif all possible inputs match some label.


VERILOG TIP 2: Incomplete Event Control Lists

➤ Always blocks that specify combinational logic and/or flow latches shouldexecute any time that any input changes. If an input is missing from theevent control list, that input will have unwanted state behavior, as if it wereconnected through some strange sort of flop or latch.

➤ One solution: In combinational always blocks use always @(∗).


How do FPGAs model Sequential Circuits?


Circuits with Memory

➤ The essential feature of sequential circuits is that they have memory.

➤ Example: a burglar alarm must remember whether it was tripped...


Schmitt Trigger


Bistable Latch

➤ A latch is a level controlled memory device

➤ There are two stable states for this device. As it has no inputs, the one itassumes depends on its power-up phase.


Basic SR Latch


SR Latch Truth Table

➤ A Race condition occurs if S = 1 and R = 1

S R Q(t + 1) Q(t + 1)

0 0 Q(t) Q(t)

0 1 0 reset

1 0 1 set

1 1 − −


SR Latch Timing


What is wrong with the following circuit?

module RSlatch(R, S, Q, Qbar);input R;input S;output Q;output Qbar;

/ **assign Q = ˜(R | Qbar);assign Qbar = ˜(S | Q);

** /reg Q, Qbar;

always @( * ) beginQ = ˜(R | Qbar);Qbar = ˜(S | Q);

end

endmodule


D Latch and Gated D Latch

➤ The SR latch has memory and could therefore serve the role of an alarmcontrol - but it is transparent

➤ Also there is the (1,1) ambiguity

➤ → Gated D-latch


Gated D Latch

➤ Note that the CLOCK still a level control.

➤ Undesirable (1,1) condition does not arise.

Clock D Q(t + 1)

0 × Q(t)

1 0 01 1 1


module Gated_D_latch(Clk, d, Q);input Clk;input d;output Q;

/ **assign Q = Clk ? q : d;

** /

reg Q;

always @( * ) beginif(Clk) Q = D;

end

endmodule


D Flip Flop


module D_flip_flop(Clk, d, Q);input Clk;input d;output Q;reg Q;

always @(negedge Clk) beginQ <= D;

end

endmodule


D Flip Flop with ASYNCHRONOUS Preset and Clear


module DFF_AR (D, Clock, Presetn, Q);

input D;input Clock;input Presetn;

output Q;reg Q;

always @(negedge Presetn or negedge Clock)if (!Presetn)

Q <= 0;else

Q <= D;

endmodule


D Flip Flop with SYNCHRONOUS Preset and Clear

➤ The way to avoid generating glitches in sequential digital designs is bymaking all inputs to be synchronous

➤ Gating the input signal and the Clear signal through the AND gateeliminates glitches.


module DFF_SR (D, Clock, Resetn, Q);

input D;inptu Clock;input Resetn;

output Q;reg Q;

always @(negedge Clock)if (!Resetn)

Q <= 0;else

Q <= D;

endmodule


T-flip flop


J-K flip flop


Applications of Registers


Counters: Asynchronous Binary Upcounter


Counters: Asynchronous Binary Upcounter or Ripple Counter

➤ T-flip flops: Q → Q if T = 1, Q → Q if T = 0

➤ Works by changing only on the rising edge of the clock inputs.

➤ Asynchronous because the flip-flops do not toggle synchronously with theclock

➤ There is an increasing delay from flip-flop to flip-flop from left to right whichleads to a constraint on size and speed.

➤ The propagationn effect leads to the term: ripple counter .

➤ Eliminate this problem with a synchronous counter.


Counters: Synchronous Counter


Modelling counters

➤ Counters are simple state machines

➤ FSM model has the advantage that the outputs of the counter can bearbitrary (not just count up / count down)

Si S0 S1 S2 S3 S4 S5 S6 S7 SpSi

RESET


Serial-In Serial-Out Register


Serial-In Serial-Out Register

➤ Temporarily stores data: for n-registers, n-clock ticks reads n bits Dn andstored in the Q′

ns. A further n-ticks and the Qn are read out.

➤ Clearly if this were an ideal sequential circuit it would work as described.


module serial_in_serial_out_shift_register (D,CLOCK,Q );input D;input CLOCK;output [7:0] Q;wire [7:0] Q;

D_flipflop s0(D, CLOCK,Q[0]);D_flipflop s1(Q[0],CLOCK,Q[1]);D_flipflop s2(Q[1],CLOCK,Q[2]);D_flipflop s3(Q[2],CLOCK,Q[3]);D_flipflop s4(Q[3],CLOCK,Q[4]);D_flipflop s5(Q[4],CLOCK,Q[5]);D_flipflop s6(Q[5],CLOCK,Q[6]);D_flipflop s7(Q[6],CLOCK,Q[7]);

endmodule

module D_flipflop (D, Clock, Q);input D, Clock;output Q;reg Q;always @(negedge Clock)

Q <= D;endmodule


Parallel to Serial and Serial to Parallel Conversion

➤ Conversion from serial communications channels or in low hardwareresources situations one oftens uses serial data .

➤ Need to convert from parallel to serial and vice versa.

➤ Performed by shift registers


Parallel Access Shift Register

➤ Shift load determines which direction it works.


module muxdff (D0, D1, Sel, Clock, Q);input D0, D1, Sel, Clock;output Q;reg Q;always @(posedge Clock)

if (!Sel)Q <= D0;

elseQ <= D1;

endmodule

module shift4 (R, L, w, Clock, Q);input [3:0] R;input L, w, Clock;output [3:0] Q;wire [3:0] Q;muxdff Stage3 (w, R[3], L, Clock, Q[3]);muxdff Stage2 (Q[3], R[2], L, Clock, Q[2]);muxdff Stage1 (Q[2], R[1], L, Clock, Q[1]);muxdff Stage0 (Q[1], R[0], L, Clock, Q[0]);

endmodule


Asynchronous Communications: A sequential Device

➤ Asynchronous serial: very common communications protocol → many descendents: SPI(serial peripheral interface), RS485, I2C, packet radio (A X25)

➤ Used to be widely used by computers (e.g. PC, MAC, ...) but still dominant inmicroprocessors. Many micros have built in serial comms.

➤ Asynchronous means that the data clock is unimportant. The receiver assumes that itslocal clock is about the same as that of the transmitter.

➤ This is not good enough for some of the descendents .e.g radio packet has asynchronising protocol in the PHY protocol layer called HDLC (High level data linkcontrol).

➤ C.F. A synchronous communications protocol where the receiver must lock onto the clockand synchronously decode the data. E.G. All wireless protocols are synchronous

➤ Asynchronous serial comes as either RS232 ±(12 − 15)V olts or TTL levels (0-5 V fore.g.). You may remember RS232 from the “dial-up days”.

➤ Rather slow: 1200 baud, 19 Kbaud, 56 kBaud even 900 kBaud in specialisedcircumstances.

➤ In anycase all high speed Internet uses synchronous protoco ls e.g. Ethernet.


RS232 pinouts(UART = Universal Asynchronous Receiver Tran smitter


RS232 pinouts


Asynchronous Communications: A sequential Device


Serial to parallel converter finite state machine

Si

In=1

In=0

Start bit

out[0]=in out[1]=in out[2]=in out[3]=in out[4]=in out[5]=in out[6]=in out[7]=in out[8]=in

PCerr=?

Done=1

S0 S1 S2 S3 S4 S5 S6 S7 SpSi


Arithmetic Processors

➤ Can do operations in serial rather than parallel. E.G. Serial adder versusparallel adder (e.g. ripple carry adder)

➤ Good for saving hardware.

➤ Good for saving hardware. Bad for speed.

In1

In2 Processor

Clock

DFFCi Co

Out


Arithmetic Processing

➤ Have already seen ripple carry adders➤ Can apply serial processing to multiplication as well➤ Input b is in parallel and the bits of a in increasing significance are

processed serially - same as textbook multiplication.


DVB-T Transmitter Block Diagram (ETSI EN 300 744 V1.4.1 (200 1-01))

(ETSI = European Telecommunications Standards Institute)


DVB-T ETSI EN 300 744 V1.4.1 (2001-01) (ctd)

The system is defined as the functional block of equipment performing theadaptation of the baseband TV signals from the output of the MPEG-2transport multiplexer, to the terrestrial channel characteristics. The followingprocesses shall be applied to the data stream (see figure 1):➤ transport multiplex adaptation and randomization for energy dispersal;➤ outer coding (i.e. Reed-Sol omon code);➤ outer interleaving (i.e. convolutional interleaving);➤ inner coding (i.e. punctured convolutional code);➤ inner interleaving;➤ mapping and modulation;➤ Orthogonal Frequency Division Multiplexing (OFDM) transmission.

The system is directly compatible with MPEG-2 coded TV signals ISO/IEC13818 [1].


DVB-T Transport Multiplexer (ETSI EN 300 744 V1.4.1 (2001-0 1))

To ensure adequate binary transitions, the data of the input MPEG-2 multiplexshall be randomized in accordance with the configurations depicted below.


DVB-T Inner Coder (ETSI EN 300 744 V1.4.1 (2001-01))

The system shall allow for a range of punctured convolutional codes, based ona mother convolutional code of rate 1/2 with 64 states.


ENGN3213 Digital Systems and Microprocessors Sequential...

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