VI Energetic Distribution of Interface States -Between Metal and 111-V Semiconductor

6.1 Introduction

Metal-semiconductors contacts have been widely investigated over the years because of

two reasons, first the fundamental understanding of their physical properties and second·

their technological application in devices. The properties. of interface states between metal

.. and semiconductor depend on the growth technique, associated processing parameters and

surface states. The process used for depositing metallic layers on a semiconductor strongly

affects the properties of Schottky co"ntact because the process itself can create defects in

the interface region of metal and semiconductor. Some of these phenomena give rise to.

interface states which affect the barrier height and transport processes through the Schottky

contact. The performance and reliability of Schottky diode and Schottky barrier based

devices, such as metal semiconductor field effect transistor(MESFET), detector and high

electron mobility transistor (HEMT) are affected by the interface states between metal and

semiconductor. Interface states between gate metal and semiconductor reduce the device

gain and increase the threshold voltage and gate leakage current, which can cause high

power consumption and noise in circuits[I,2]. It has been shown[3,4] that an important

source of low frequency noise in field effect transistors is the interaction of electrons in the

channel with interface states. Jantch[5] has shown that the origin of l/f noise in field effect

transistors is due to the random walk of mobile carriers in the interface region. The low

frequency noise behavior is important for several applications of HEMTs. AIGaAs/InGaAs

based pseudomorphic HEMTs are enjoying significant success in microwave and millimeter

102

wave power applications[6,7] and are the fastest commercially available 3-terminal devices

to date. There is strong interest in the development of efficient switches in the power ranges

between 100 kW-1 MW and well above 1 MW. In the latter category, the applications include

improved control over power distribution on the electricity grid, and electrical sub-systems

in electric automobiles, advanced aircraft and combat vehicles. It is anticipated that the

packaged semiconductor switches will need in these applications at temperatures in excess of

3000 e without liquid cooling. CaN based high power Schottky rectifier and MESFET will

be ideal candidate for these applications. Interface states between GaN and metal electrode

in high power Schootky diode is detrimental for switching speed and leakage current. Very

few investigations have been published so far regarding this interface defect density and.

their energetic distribution in CaAs based sub-micron devices and there is no report on the

investigation of interface states in CaN based devices. One reason might be the difficulties in

experimental investigations and their theoretical interpretation. Recently, Balakrishnan et

aI., have shown[8] the effect of interface states under passivated source-gate and gate-drain

regions on the transconductance dispersion in GaAs MESFETs.

Starting from the classical work[9] by Bardeen in 1947, several investigations have been

attempted to clarify the properties and origin of interface states[10]. Though the unified

defect model of Spicer and co-workers[1l,12] can explain the mechanism of Schottky barrier

formation on 111-V semiconductors, so far no agreement on the basic properties, such as

whether these states are of a continuous or of a discrete nature, their energetic location and

their electrical parameters have been achieved. In practical cases, Schottky contacts are

not intimate metal-semiconductor contacts, but separated by a thin layer. This inadvertent

interfacial layer can arise from processing steps and due to various reasons such as cross­

diffusion, out-diffusion and chemical reaction between metal and semiconductor. Moreover,

111-V semiconductors used in these devices are plagued with comparatively high density of

surface states compared to elemental semiconductors and the physics of Schottky contacts

on 111-V semiconductors is complicated because of the fact that the Schottky barrier height

103

of III-V semiconductors such as GaAs is weakly dependent or independent of metal work

function due to surface Fermi level pinning[10-12]. Hence, the current transport through

Schottky contacts in III-V semiconductor based devices is affected by the presence of thin

interfacial layer and defect states at the interface between metal and semiconductor.

There are several methods [10,13] to estimate the interface states density in metal­

semiconductor and metal-insulator-semiconductor structures. These methods are mainly

based on high and low frequency capacitance and conductance or sub-threshold current

measurements. All these methods depend on the precise determination of Schottky gate

capacitance, including the sub-threshold current technique which uses depletion layer capac­

itance during weak inversion. In case of sub-micron gate devices, because of the small gate

area, precise determination of capacitance(which will be around IpF) and detection of any

change in capacitance are not possible due to the limitations ofmeasuriIig instruments. As

the gate length is getting scaled down gradually, it is desirable to avoid any method based on

capacitance measurements. There are several attempts to determine interface states density

from current-voltage(I-V) characteristics[10,14-16]. All these works have used either anequi­

libriumapproach or used a priori assumption that interface state distribution is exponential.

Maeda and co-workers[17,18] have proposed a non-equilibrium approach, which is based on

the fact that departure from ideal I-V characteristics of III-V Schottky diode is due to the

change in occupation of interface states with applied bias. Occupation of the interface states

changes due to emission and capture of carriers, which in turn changes the Schottky barrier

height with applied bias.

In this work we have presented a method based on the model proposed by Maeda and

co-workers[17,18] for determining the distribution of interface state density between metal

and semiconductor Schottky contact from I-V characteristics. We have used our techniqU{

to determine the density and the· energetic distribution of interface states in metal-GaA~

(MESFET) and metal-AIGaAs (HEMT) Schottky contacts[19]. The results match well witb

the results obtained by photoemission spectroscopy by other groups. Finally we have used

104

qV. I.

Ec t-t--t-------y-----t- E

FS

qV

E 9

Figure 1: Energy band diagram for metal/interfacial layer / n - semiconductor.

this technique to determine interface density of states in metal-GaN Schottky contacts.

6.2 Theoretical Basis

In case of III-V semiconductor Schottky contact, the semiconductor surface is considered

to be covered with an inadvertent thin layer of native oxide. At the boundary between the

semiconductor and oxide layer, high density of interface electronic states is expected in the

forbidden gap[1l,12]. The interface states of the semiconductor are occupied by electrons up

to the Fermi level. Energy band diagram for metal/interfacial layer / n-type semiconductor

is shown in Fig.I.

The parameter <Po is known as the as the neutral level. The shaded area indicates the

occupied interface states. The occupation of the interface states produces a space charge,

which causes a potential difference in the interfacial layer and reduces the effect of work

function on the barrier height. The interfacial layer model[20] of the actual Schottky barrier

successfully explains the dependence of the Schottky barrier height on the metal work func-

105

tion and based on the thermal equilibrium conditions at zero applied bias(in this case Fermi

level is same throughout the sample). Ma~da and co workers[17,18] extended this model in ~.

case of non-equilibrium situation, i.e. when a .bias voltage is applied to the Schottky bar-

rier. When a forward bias is applied, Fermi level in the metal side(EFm ) differs from that

of semiconductor side(EFs ). The Fermi level of the interface states EFi should be between

these two Fermi levels. Space charge due to the interface states will change depending upon

the position of the Fermi level of the interface states EFi and produces a change in Schot­

tky barrier height. The shift in EFj due to the space charges from the equilibrium position

will cause non-ideality in the forward I-V characteristics. Electrons on the interface states

communicate with conduction band of semiconductor by capture and emission and with the

metal by tunneling. When a voltage is applied, the occupation of the interface states is

determined by the Fermi level EFj of the interface states as shown in Fig.l. Depending .

on the relative magnitude of three communication processes (capture, emission, tunneling)

the level EFj will be higher than or equal or lower than the semiconductor bulk Fermi level

EFs . It has been assumed that the thickness of the interfacial layer is much smaller than

the depletion layer width. According to interfacial layer model[20] the zero bias Schottky

barrier height <PB is represented by

<PB = ,(<Pm - X) + (1-,) [~g - <Po] (1)

where, = 1/(1 + q8~S). X is the electron affinity of the semiconductor, Ds is the interface

energy state density(eV /cm2), Ej is the dielectric constant of the interfacial layer, <Pm is the

work function of metal, 8 is the thickness of the interfacial layer, <Po is the neutral level of

the interface states measured from the top of the valence band and Eg is the band gap of

the semiconductor. When the bias is applied to the Schottky barrier, the occupation of

electrons in the interface states changes, thus altering the amount of space charge created

due to interface states. This, in turn, changes the Schottky barrier height <PB and can be

given by,

106

<PB = (<Pm - X) + ~: [( ~g - <PB - <Po) Ds + VDSb] (2)

where Dsb is the density of interface states due to applied bias V. The second term in the

square bracket in Eqn.2 represents the density of occupied interface states due to the applied

voltage V and the first term represents the density of electrons in the interface states under

zero bias. The term V Dsb is related to the Fermi level EFi of the interface state above the

metal Fermi level EFm through the relation

VDsb Ds q

(3)

Taking the metal Fermi level EFm as the zero energy reference, the change in the barrier

height /).<PB due to applied bias from Eqn.l and 2 is given by,

/).<PB = (<pB - <PH) = (l_,)EFi q

(4)

The calculation of the change in Schottky barrier height due to incremental change in ap-

plied bias will depend on the trap kinetics of the interface states between metal gate and

semiconductor. As already discussed, on the application of the voltage 'bias, the occupation

of the interface states changes through the capture, emission and tunneling processes. The

electron emission probability e by the interface states can be given by

e = eo exp ( - q<p:B; E) (5)

where eo is a constant and depend on the electron capture cross-section of interface states

and effective density of states of the conduction band, E is the energy of the electron in

the interface states, KB is the Boltzman constant and T is the temperature. The electron

capture probability c of the interface states from the conduction band can be given by

_ 0 (_ q(<PB - V)) c - c exp kBT (6)

107

where Co is a constant and depends on electron capture cross-section and electron concen-

tration in the conduction band. The occupation probability f of the interface states can be

given by

f = c e+c+t

(7)

where t is the tunneling probability of electrons from interface states to metal. In case of

zero forward bias, the Fermi levels in metal and semiconductor are aligned. Now, let us

suppose the applied forward bias is being increased in steps, of .~ V. After the first step, the

Schottky barrier changes from <PB (zero bias barrier height) to <p1 and the change in barrier

height becomes ~<p1. Due to change in forward. bias, Fermi level at the interface EFi also

changes by an amount ~EFi due to the change in the occupation of the interface states

from the equilibrium situation. The modified barrier height ( <p1) and the new position of the

Fermi level(E}J will be

(8)

After N increment of the forward bias of equal step, barrier height and the position of the

Fermi level can be given by

",N ",N-l "",N EN EN- 1 "EN 'l'B = 'l'B + ll'l'B' Fi = Fi + II Fi

Eqn.(l) can be expressed as

and after application of a forward bias step ~ V, Eqn.lO becomes

From Eqn.8, 10 and 11, we can get

108

(9)

(10)

(11)

al ~E}i q(1 + al) ~V

where al = q8DsI/f.i and similarly after Nth step, we can get

aN ~E~ q(1 + aN) ~V

(12)

(13)

Now, the variation of ~EFi with applied forward bias has to be determined. In the steady

state condition, if we put f = 1/2, we will have c = e + t. After application of first bias

step ~ V, the capture and emission probabilities can be given by

(14)

We can get, after assuming ~ V to be very small and neglecting higher order terms in

Eqn.12,13 and 14

1

Similarly after Nth step we can get

·N ~EFi 1 ~V - 1- t

cN(l+C>N}

(15)

(16)

The I - V characteristics of a rectifying metal semiconductor contact is normally described

by the thermoionic relation

(17)

where V is the applied bias, T the temperature, n the ideality factor, kB the Boltzman's

constant and q is the electronic charge. Is is the saturation current and related to the metal

semiconductor barrier height through the relation

(18)

109

where A is the area of the diode, A ** is the effective Richardson constant and <PB is the

Schottky barrier height. From Eqn.18, we can get

(19)

Now using Eqn.12 and 15, we can express Eqn.19 as

kBTlnJl-lnIO =_ al +1

q ~V (1 + al) (1- Cdl~al») (20)

The reciprocal of the term on the left hand side in Eqn.20 is the ideality factor n, which can

be denoted asnlafter the application of first forward bias step of ~ V. The term al can be

extracted from the·· above relation as

(21)

Finally, the density of the interface states can be expressed as

(22)

and similarly

DsN = ~ (1 - _t ) (nN - 1) qo eN (23)

The distribution of interface density of states can be given by

Ds = ~ ;~ (1 - :j) (nj - 1) J

(24)

It is clear from Eqn.24 that density of interface states is proportional to the ideality factor

n. One can now proceed to determine the energy distribution of interface states from the

bottom of the conduction band Ec through the relation

110

q¢>B - EFi

q(¢>~ + ~¢>k + ... + ~¢>~) - (E~i + ~E~i + ... + ~Ef.i) o (a1) 1 ( aN) N q¢>B + ~EF· + ... + ~EF· 1 + al l 1 + aN l

q"-O + ~ ( aj ) ~Ej . 'l-'B ~ 1 + a. F,

j J

6.3 Experimental Details

(25)

(26)

The devices used in this work are GaAs MESFET and GaAIAs/InGaAs pseudomorphic

HEMTs(pHEMTs). MESFETs were fabricated by ion-implantation. Ti/Pt/ Au was used as

the gate metal. The gate dimensions of the MESFET are Lg =0.8JLm, z=550JLm. More details

of the MESFET structure is given in Ref.8. The pHEMT structure"was grown by molecular

beam epitaxy. The layer structure for pHEMT features, from bottom to top, a 1JLm thick

undoped GaAs buffer, 130A undoped Ino.2Gao.8As channel, 30A undoped Alo.23Gao.77As

spacer, 600A Si-doped(5xlO12cm-2) Alo.23Gao.77As supply and 400A n+(5x1018cm-3) GaAs

cap layer. The device was grown on a semi-insulating GaAs(100) wafer. The epitaxial layer

was grown at 500°C. The V /111 flux ratio was maintained in the range of 30 to 50 for As-

stabilized condition. Following .epitaxial growth, the active device was isolated by a mesa

. etch and Au:Ge/Ni/ Au ohmic contact was deposited and annealed at 400°C for lOs by rapid

thermal processing. A gate recess etch was then performed to allow the gate metal to set

directly on the AIGaAs electron supply layer. Au/Ti/ Au Schottky gate was formed by e­

beam lithography. The gate dimensions of pHEMT are Lg =0.2JLm, z=200JLm. The forward

and reverse I-V characteristics at various temperatures were measured using the Keithley 428

current amplifier, 230 voltage source and liquid nitrogen cryostat. MESFET was fabricated

at SPL, Delhi and pHEMT at NEe, Japan.

In this work, we have investigated the I-V characteristics of two Au/Pt n GaN Schottky

contacts from Ref.21. The GaN layer was grown on Ah03 substrates by radio frequency

111

plasma-assisted MBE. In one set of devices, Schottky contacts were formed on one sample

after a conventional surface cleaning. The conventional cleaning process involves sequential

. rinsing in acetone, isopropyl alcohol and de-ionized water prior to lithography for defining

the contact area. After lithography, the samples were rinsed for 60 s in Hel and 30 s in

buffered HF to remove the native oxide. In case of the second set of devices, samples were

first cleaned in the conventional way then boiled in (NH4h S solution for 20 min before

making Schottky contact. The Pt (400 It)/ Au (1500 It) Schottky contacts were fabricated

by electron beam deposition.

6.4 Experimental Results and Discussions

6.4.1 GaAs-MESFET and GaAIAs/InGaAs-pHEMT

The forward I-V characteristics of MESFET and pHEMT at room temperature are shown

in Fig.2. The figure also shows the fitting with the thermionic emission mechanism. The

excess current in low bias region with high ideality factor suggests a deviation from the

thermionic emission mechanism. At larger bias, the thermionic emission dominates and the

current increases exponentially with bias according to Eqn.18. The temperature dependence

of the saturation current has been used to obtain the Schottky barrier height. The inclusion

of the ideality factor n in the saturation current is necessary to determine the correct Schot­

tky barrier height ¢B from the extrapolated saturation current Is . It has been reported by

Ashok et al[22] and Shewchun et al[23,24] that inclusion of the ideality factor in Is is neces­

sary to explain the experimental data(Is, ¢B and A**) for Au-GaAs and Ni-GaAs Schottky

diodes and Si MIS solar cells respectively. Fig.3 shows the linear dependence of Is/T2 on

lOOO/nT for MESFET and pHEMT, the slope being proportional to barrier height. In Fig.3,

both In(Is/T2) vs. lOOO/T and In(Is/T2) vs. lOOO/nT are plotted for comparison and the

deviation from linearity at low temperature for 1000/T plot is evident. The ideality factor

at OAV bias has been used, where thermionic emission is dominant. The barrier height ¢B

for the Ti/Pt/ Au-GaAs Schottky diode in the MESFET is O.gleV which agrees well with

112

10-6 10.6

T = 300K T = 300K 10.7

10-8

- 10-8 <C --c CI)

10.10 10.9 ~ ~

:l (.)

10.12

(a) 10.11 (b)

o 0.1 0.2 0.3 0.4 0.5 o 0.1 0.2 0.3 0.4 0.5

Forward Voltage (V) Forward Voltage(V)

Figure 2: The forward J- V characteristics of the Schottky gate of (a) MESFET and (b) pHEMT. Solid lines are the simulated data for thermionic emission and symbols are measured data.

the reported values in case of GaAs Schottky diodes with a very thin interfaciallayer[22].

¢>B for the Au/Ti/ Au-AIGaAs Schottky diode in pHEMT is1.16eV which agrees well with

the results reported by Best[25]. High barrier manifests the presence of a thin interfacial

layer between gate metal-GaAs and metal-AIGaAs in MESFET and pHEMT respectively.

It is clear from Fig.2 that the I-V characteristics at low bias exhibit an excess current,

which cannot be accounted for only by thermionic emission. The origin ofthisexcess current

and the high value of ideality factor in this region suggest recombination in the depletion

region and tunneling as probable causes. We have tried to fit the forward current in the low

biaS region{0-0.3V) with a simulated current comprised of three components, current due

to thermionic emission, current due to field emission and recombination current [10,22,26]'

but we failed to get a reasonable fit. The non-conformity between the experimental data

and the theoretical fit suggests that the current conduction mechanism between the metal

gate and GaAs and AIGaAs in MESFET and pHEMT respectively with the thin interfacial

113

-20 c 10001T 0 1000/nT 0 1000/nT C 10001T

-35.0

-40 -(\I

~ « -37.5 --(\I

t::: -60 C/)

:::::.. r::: -40.0

-80 -42.5 (b)

2.5 5.0 7.5 3 5

10001T or 1000/nT (11K) 10001T or 1000/nT(1/K)

Figure 3: Plots for the determination of barrier height of the (aJ Ti/Pt/Au-GaAs Schottky gate in MESFET and (b) Au/Ti/Au-AIGaAs Schottky gate in pHEMT. The value of ideality factor n is taken at 0.4 V forward bias.

layer is more complicated than an intimate metal-semiconductor contact. Card and Rhod­

erick[27] tried to explain the current conduction mechanism in silicon Schottky diodes with

a thin interfacial layer and proposed a correction for the saturation current with a factor

proportional to exp(O.26X¥28), where XS is the mean barrier height and 8is the thickness of

the interfacial layer. However, this model cannot be applied to III-V semiconductor-metal

contacts because of high density of surface states.

Ashok an~ co-workers[22] showed that in case of GaAs, xs determined using Roderick's

method gives too Iowa value to be interpreted as the distance from the conduction band

edge of the semiconductor to that of the insulator. It has been suggested[17,18] that we

have to consider the recombination and generation by the interface states and interface state

assisted tunneling in the current transport mechanism of the metal-interfacial layer-III-V

semiconductor system. In addition, a non-equilibrium theory has to be invoked to take into

account the capture and emission of the carriers from interface states to the conduction

14

3.5 T = 300K T = 300K

3.0 2.0 -c 2.5 -10..

0 -u as LL 2.0 1.5 >-!:: as Q) 1.5 :2

1.0 1.0 (b)

0.5 0.5 '-----'-_--'--_-'----1._--'

o 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5

Forward Voltage(V) Forward Voltage(V)

Figure 4: The variation of the ideality factor n with forward bias applied at the gate in case of (aJ MESFET and (b) pHEMT.

band o,f the semiconductor. The ideality factor n(= k;T d:JI») in Eqn.18 determined from

the forward I-V characteristics at 300K is shown in Fig.3 for MESFET and pHEMT. All

I-V data have been corrected for series resistance using Lee's method[28]. It is clear from

FigA, that the ideality factor n increases with bias to almost 3 and then decreases in both

devices. Such voltage dependence of n has not been observed in Si with interface layers and

is very unique for 111-V semiconductors with high density of surface states. This apparently

strange behavior is considered to be due to interface states between the metal and the 111-V

semiconductor. Spicer and co-workers[11,12] have reported energetic distribution of interface

states between metal and GaAs from photo-emission experiments. The strange behavior of

the ideality factor with applied bias is considered to be related with the distribution of

interface states in the semiconductor forbidden gap[11,12,18]. The density of interface states.

can be determined from Eqn.24 using the forward bias dependent ideality factor n as shown

in FigA. The exact values of the parameters such as dielectric constant of the interfacial

layer Ei, thickness of the interfacial layer b, capture probability c and tunneling probability

115

6

C? ,.. 0.8 0 ..... 5 >< ->

(1) N-

E 4 u ....... CI) 0.4 C

3

0.4 0.6 0.8 1.0 0.6 0.8 1.0 1.2

Ec· E (eV)

Figure 5: Plots of energetic distribution of interface states between metal and semiconductor as a function of energy measured from the bottom of the conduction band in case of (a) A-[ESFET and (b) pHEMT. .

t are not known experimentally. We can however estimate the interface density of states by

assuming fi = 4fo[17,18,20], where fois the dielectric constant of free space, 6 = 30A and t= ,

c/2. It is difficult to measure the thickness of the interfacial layer accurately, but it has been

reported[18,22] 6 ~ 20 - 30A in a similar device structure and processing. Fig.5 shows the

. energetic distribution of the interface states between gate metal and GaAs in MESFET and

gate metal and Alo.23Gao.77As in pHEMT respectively using Eqn.26. The interface density

between Schottky metal gate and GaAs in MESFET peaks at O. 78e V. This value matches

well with the energy level measured by photoemission spectroscopy[11,12]. Spicer and co­

workers[11,12] have proposed the existence of two energy levels which are present in the band

gap. The level at O.7eV below the conduction band minimum(CBM) is an acceptor type due

to missing As and the other at 0.geV below CBM is a donor type due to missing Ga on

the surface. Similar work in case of AlxGal_xAs is not available in theliterature. However,

interface density peaking at an energy of 1.02e V might also be due to the As vacancy. In

116

Figure 6: The forward 1- V characteristics of Conventionally cleaned (empty circle) and (N H4hS treated (solid circle) Au/Pt/n CaN Schottky contact. Solid lines are the simu-lated data for thermionic emission.

case of metal-Alo.23Gao.77As in pHEMT, the origin of another broad peak at O.86eV is not

known.

6.4.2 Metal-GaN Schottky contacts

The development of reliable, reproducible and thermally stable Ohmic and Schottky con­

tacts is one of the most important areas for GaN device technology. High quality rectifying

and Ohmic contacts 'With low specific resistance are needed for better performance of the

devices. Research on both Ohmic and Schottky contacts of GaN are of current interest.

Schottky contact of various elemental metals like Au, Pt, Pd,Ni, Ti, Cr[29-33] and some

metal oxides like indium tin oxide (ITO)[34,35], cadmium tin oxide(CTO)[36] and also some

silicide like PtSi[37] and NiSi[38] have been investigated. There are still large variations

in barrier heights reported by different workers for standard metals on GaN[29-33]. This

nonuniformity can be due to various reasons, the presence of several transport mechanisms,

the presence of defects in the film, the local stoichiometry variations and the presence of an

117

-c -o 5 -(,) co u. ~ -.--;3 Q)

" 0.2 0.4 0.6 0.8 1.0 1.2

Voltage (V)

Figure 7: The variation of the ideality factor n with forward bias in case of conventionally cleaned (solid line) and (NH4hS treated (dashed line) Au/Pt/n GaN Schottky diode.

interfacial layer between the metal and the semiconductor. Thermal annealing and the effec~

tiveness of the surface cleaning prior to the metal deposition can also affect ,the properties of·

the interface. Shen et al.[35] has shown the effects ofthermalannealing on the ITO Schottky

contacts on GaN. The effective Schottky barrier heights were 0.68, 0.88, 0.94 and 0.95 eV

for nonannealed, 400, 500 and 6000 C annealed samples respectively. Liu et al.[38] have also

shown the thermal annealing effect on Ni and NiSi-GaN Schottky contacts. These results

indicate that an increase of barrier height may be attributed to the change of the properties

of the interfacial states at the metal and GaN interface after annealing. Cao et al. [21] have

shown that the Au/Pt Schottky barrier height on both nand p type GaN samples reduces

with an additional treatment in (NH4hS after conventional surface cleaning prior to the

metal deposition. The role of surface treatments in determining the barrier heights has been

investigated by many others.

In Fig.6, forward I-V characteristics of two Schottky diodes are shown. All I-V char­

acteristics have been corrected for series resistance using Lee's method[28]. We have got a

118

10

C") 8 ,.. 0 ,.... ><

6 -> (1) -('II I 4 E (.) -(I)

2 C

0 0.3 0.5 0.7

" ",

Ec - E (eV)

, , ,/

, , / , , , , ,

0.9 1.1

Figure 8: Plots of energetic distribution of interface states between metal and semiconductor as a function. of energy measured from the bottom of the conduction band in case of Con-ventionally cleaned (solid line) and (NH4hS treated (dashed line) Au/Ptfn GaN Schottky diode.

series resistance Rs of 13 K!1 in conventionally cleaned sample and 4 K!1 in (NH4hS treated

sample. Clearly, forward current increases as a result of the (NH4hS treatment. Fig.6also

shows the fitting with the thermoionic emission mechanism of current transport through

the Schottky contact(Eqn.18). The experimental data is showing a clear deviation from the

thermoionic emission current at low and high bias region. The voltage dependence of the

ideality factor n is shown in Fig.7. It shows two distinct picks, one at low bias and another

at high bias region for both the samples. The exact value of the parameters such as dielectric

constant of the interfacial layer ti, thickness of the interfacial layer 8, capture probability c

and tunneling probability t are not known experimentally. We have taken ti = 2to·, 8 = 20

A and the ratio t / c = 0.5 to estimate the interface density of states.

Fig.8 shows the energetic distribution of the interface states for both the samples. The

conventionally cleaned sample shows higher level of interface state density than the treated

sample. Two distinct picks are appearing at around 0.45 eV and Ie V, which are same as the

119

energy levels for V Ga and/or V Ga-ON in bulk GaN( discussed in detail in Chapter III). The

mechanism, which is responsible of these native defects(V Ga and V Ga-ON) in bulk n-type -.

GaN, should also be responsible for these defects on n-type GaN surface. After the treatment

with (NH4hS both the pick heights reduced. V Ga and V Ga-ON are acceptor type defects.

Either H or S from (NH4hS can passivate these interface states.

6.5 Conclusion

The departure from an ideal metal-semiconductor contact inSchottky diode and Schottky

diode based devices has been explained quantitatively. Nonideal I-V characteristics and bias

dependent ideality factor have been correlated with the existence of interface states and a

thin interfacial layer between metal and GaAs in MESFET, metal and AIGaAs in pHEMT

and metal and GaN in Gan-Schottky diode. Using a non-equilibrium theoretical model,

energetic distribution and density of interface states have been determined from the bias

depended ideality factor. This me~hod can be successfully applied to study the interface

states in sub-micron devices.

120

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