End-to-End Veriﬁcation of ARM Processors with ISA-Formal · ARMResearch End-to-End Veriﬁcation...

ARMResearch

End-to-End Verification of ARM®

Processors with ISA-Formal

Alastair Reid, Rick Chen, Anastasios Deligiannis, David Gilday, David Hoyes, Will Keen, Ashan Pathirane, Owen Shepherd, Peter Vrabel, Ali Zaidi

[email protected]@alastair_d_reid

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Scale

Large Specifications

Large Implementations

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Checking an instruction

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ADD

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Checking an instruction

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ADDCMPLDR STRBNE

Context

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Memory

R0-

R15DecodeFetch

EX MEM WBIF ID

R0-

R15

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Memory

R0-

R15DecodeFetch

EX MEM WBIF ID

R0-

R15

πpre

πpost

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Memory

R0-

R15DecodeFetch

EX MEM WBIF ID

R0-

R15

πpre

πpost

Pre Post_spec

Post_cpu

Spec ==?

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Errors ISA-Formal can catch

• Errors in decode

• Errors in data path

• Errors in forwarding logic

• Errors in register renaming

• Errors in exception handling

• Errors in speculative execution

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NoContext

Context

{

{

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Specifying ADD

assign ADD_retiring = (pre.opcode & 16'b1111_1110_0000_0000) == 16'b0001_1000_0000_0000;assign ADD_result = pre.R[pre.opcode[8:6]] + pre.R[pre.opcode[5:3]];assign ADD_Rd = pre.opcode[2:0];

assert property (@(posedge clk) disable iff (~reset_n) ADD_retiring |-> (ADD_result == post.R[ADD_Rd]));

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ISA Formal

• Finds complex bugs in processor pipelines

• Applied to wide range of μArchitectures

• Uses translation of ARM’s internal ISA specification

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Challenges

• Complex Functional Units• FP• Memory

• Dual Issue• Instruction Fusion• Register Renaming• Out-of-order Retire

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Memory

R0-

R15DecodeFetch

EX MEM WBIF ID

R0-

R15

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MemoryTLB

Prefetch

PTW

Coherence

Cache

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MemoryTLB

Prefetch

PTW

Coherence

Cache

FPUFMUL

FADD FDIV

FSQRT

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Memory

R0-

R15DecodeFetch

R0-

R15

Memory

FPU

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FP Subset Behaviour

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-∞ -1 0 1 ∞-∞ -∞ -∞ -∞ -∞

-1 -∞ -1 0 ∞0 -∞ -1 0 1 ∞1 -∞ 0 1 ∞∞ ∞ ∞ ∞ ∞

FPAdd

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ISA Formal

• Finds complex bugs in processor pipelines

• Applied to wide range of μArchitectures

• Uses translation of ARM’s internal ISA specification

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ISA-Formal Properties

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ADC ADD B … YIELDR[] ✔

NZCVSPPC

S[],D[],V[]FPSR

MemReadMemWriteSysRegRW

ELRESR…

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ADC ADD B … YIELDR[] ✔

NZCVSP ✔

PCS[],D[],V[]FPSR


ELRESR…

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ADC ADD B … YIELDR[] ✔ ✔

NZCVSP ✔

PC ✔

S[],D[],V[]FPSR


ELRESR…

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ADC ADD B … YIELDR[] ✔ ✔ ✔

NZCV ✔

SP ✔ ✔

PC ✔

S[],D[],V[]FPSR


ELRESR…

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But this is slowand inconsistent

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ADC ADD B … YIELDR[] ✔ ✔ ✔ ✔ ✔

NZCVSPPC

S[],D[],V[]FPSR


ELRESR…

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NZCV ✔ ✔ ✔ ✔ ✔

SP ✔ ✔ ✔ ✔ ✔

PC ✔ ✔ ✔ ✔ ✔

S[],D[],V[]FPSR


ELRESR…

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NZCV ✔ ✔ ✔ ✔ ✔

SP ✔ ✔ ✔ ✔ ✔

PC ✔ ✔ ✔ ✔ ✔

S[],D[],V[] ✔ ✔ ✔ ✔ ✔

FPSR ✔ ✔ ✔ ✔ ✔


ELRESR…

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NZCV ✔ ✔ ✔ ✔ ✔

SP ✔ ✔ ✔ ✔ ✔

PC ✔ ✔ ✔ ✔ ✔

S[],D[],V[] ✔ ✔ ✔ ✔ ✔

FPSR ✔ ✔ ✔ ✔ ✔

MemRead ✔ ✔ ✔ ✔ ✔

MemWrite ✔ ✔ ✔ ✔ ✔

SysRegRWELRESR…

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NZCV ✔ ✔ ✔ ✔ ✔

SP ✔ ✔ ✔ ✔ ✔

PC ✔ ✔ ✔ ✔ ✔

S[],D[],V[] ✔ ✔ ✔ ✔ ✔

FPSR ✔ ✔ ✔ ✔ ✔

MemRead ✔ ✔ ✔ ✔ ✔

MemWrite ✔ ✔ ✔ ✔ ✔

SysRegRW ✔ ✔ ✔ ✔ ✔

ELR ✔ ✔ ✔ ✔ ✔

ESR ✔ ✔ ✔ ✔ ✔

…

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Automation

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CombinationalVerilog

ASL to Verilog

ArchitectureSpecification

Specialize Monomorphize

Constant Propagation Width Analysis

Exception Handling …

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Summary• Finds complex bugs in processor pipelines

• Complete RTL, not just model

• Bug absence not being proved (yet)

• Applied to wide range of μArchitectures• 3 trials, 6 full deployments.

• Uses translation of ARM’s internal ISA specification• Public release of ISA spec this fall in collaboration w/ Cambridge University

• “Trustworthy Specifications of ARM® v8-A and v8-M System Level Architecture,” to appear, FMCAD 2016

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End

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[email protected]@alastair_d_reid

End-to-End Veriﬁcation of ARM Processors with ISA-Formal · ARMResearch End-to-End Veriﬁcation...

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