Enabling Power-Efficient Designs With III-V Heterojunction Tunnel...

CSICS 2014 San Diego, California

Enabling Power-Efficient Designs With III-V Heterojunction Tunnel FETs

Moon S. Kim, Huichu Liu, Karthik Swaminathan, Xueqing Li, Suman

Datta, and Vijaykrishnan Narayanan The Pennsylvania State University

Oct 21, 2014


Why TFET? CMOS Scaling Challenge

Slide 2

3.0

2.5

1.5

1.0

0.0

1995 2000 2005 2010 2015

Year

VC

C a

nd

VT (

V)

VT

VCC

1.0 V

0.2 V

2.0

0.5

Slowdown of

VCC scaling Non-Scalability

of VT

1.6

1.2

0.8

0.4

0.0

0.5 0.4 0.3 0.2 0.1

VCC (V)

Dela

y (

us)

VT

K. Swaminathan et al, IEEE Micro 2013. H. Jeon Trans on Instrument and Measurement 2010.

CSICS 2014 San Diego, California Slide 3

• Due to 60 mV/dec CMOS SS limit, reducing VT (so as to reduce VDD for lower power) increases the leakage power significantly;

• With a lower SS, Tunnel FETs can operate at a lower VDD and lower power.

A. M. Ionescu, H. Riel, Nature 2011. A. M. Ionescu, IEDM short course 2013.

VDD

Device: off on

S

• Subthreshold Swing (SS), ION, and Leakage IOFF

Why TFET? CMOS Scaling Challenge


Emerging Tunnel FETs (TFETs)

Slide 4

Deway et al., IEDM 11 Mohata et al., VLSI 12 K. Moselund et al., IBM

Xing et al., IEDM 12 Rooyackers et al., IEDM 13

High-k

Pd (gate)

N+ In0.9Ga0.1As

(drain)

i-In0.9Ga0.1As

(channel)

P+ GaAs0.18Sb0.82

(source)

Mo

ILD

100nm

Bijesh R. et al., IEDM 13

A. M. Ionescu, IEDM short course 2013.


III-V GaSb-InAs Heterojunction TFET (HTFET)

• HTFET: High Ion and low SS achieved in n- and p- TFET with electrostatic improvement.

• Non-steep subthreshold slope is mainly due to the trap assisted tunneling (TAT) of the source/channel interface states. Further improvement on material interface is required.

V. Narayanan, ISLPED 2013.


IOFF

Gate Voltage, VG

Dra

in C

urr

en

t, lo

g(I

D)

Eg

Band-to-Band Tunneling

Source

Channel

EC

EVe

-

Eg

Gate Bias Eg

Band-gap blocks

Tunneling Current

SourceChannel

EC

EVe

-

Eg

ON

OFFDrainSource Channel

Gate

ION

60 mV/decade

Sub-60

mV/decade

III-V GaSb-InAs Heterojunction TFET (HTFET)

Slide 6

Essentially a gated reverse-biased p-i-n tunnel diode with asymmetrical source/drain doping;

Band-to-Band tunneling (BTBT) induced from the sub-thermal switching leads to <60mV/dec SS, more abrupt ON-OFF transition compared to CMOS.

L. Chang IEEE Proceeding 2010; A. Seabaugh et al, IEEE Proc., Nov 2010

HTFET Structure and Operation


Modeling HTFET: Device to Architecture

Slide 7

DC Validation

Transient Validation

Verilog-A Device Model

Circuit & Architecture Design

TCAD Model Calibration


GaSb-InAs TFET Characteristics

Slide 8

0.80.60.20 0.4

10-8

10-7

10-6

10-5

10-4

I DS

(uA

/um

)

VGS (V)

@VDS = 0.4 V10-3

10-9

60 mV/decade

30 mV/decade

HTFETCMOS

Key Features Observed

Steep-slope with High Ion @ low VCC

High saturated small-signal RO

Uni-directional Tunneling

Negative differential resistance (NDR)

0.80.60.20 0.4000

050

100

150

200

250

I DS

(uA

/um

)

VDS (V)

@VGS = 0.4 V

HTFETCMOS

300

High RO

NDR

H. Liu et al, ISLPED13

B. Sedighi et al, “A CNN-Inspired Mixed Signal Processor Based on Tunnel

Transistors,” DATE 2015, submitted

I DS (

A/u

m)


GaSb-InAs TFET Characteristics (cont.)

Slide 9

CLK

CLK

CLK

CLK

Q

Reset Reset

D

D

CLKCLK

CLK

CLK

CLK

CLK

CLKCLK

CLK

Reset Reset

Q

Type 2. Transmission based Si FinFET DFF

Type 2. Transmission based HTFET DFF

Discharging path

QD

Reset

CLK

CLKCLK

CLK

CLK

Reset

CLK

CLK

CLK

Type 1. C2MOS DFF

CLK

CLK

CLK

Example of Switch Design Considerations

Additional switch for

bidirectional conduction



Slide 10

Capacitance versus gate voltage

Suppressed capacitance (low voltage)

Enhanced Miller effect (full voltage)

3020100

-200

0

200

400

1000

VIN

, V

OU

T (

mV

)

Time (ps)

HTFET FO1 INV1

Enhanced

Miller Cap Effect600

800

VIN

VOUT

40 50

S. Mookerjea et al., EDL 2009.

H. Liu et al., “Tunnel FET RF rectifier design for energy harvesting applications,” JETCAS 2014



Slide 11

IDS (uA/um)

gm

,HT

FE

T/g

m,C

MO

S

IDS (uA/um)

f T (

GH

z)

B. Sedighi et al., “Analog Circuit Design Using Tunnel-FETs,” TCAS-I, to be published

@VDS=0.4V

Gain

of

gm

RO

10

100

1000

10-2 100 102

IDS (uA/um)

The gm, HTFET is significantly larger than gm,CMOS at a low current.

With larger small-signal Ro, the intrinsic gain is further improved.

HTFET has >300 GHz while CMOS shows higher fT at a higher current.

The peak fT at a lower current makes HTFET attractive for low-power

applications.

HTFET HTFET HTFET

CMOS

CMOS

CMOS

gm,HTFET/gm,CMOS fT (GHz) Gain of gmRO



Slide 12

Flicker noise is based on carrier number fluctuation

The shot noise is modeled similar to tunnel diode

The thermal noise model is similar to

the Si-FinFET thermal model

R. Pandey, et al., “Electrical Noise in Heterojunction Interband Tunnel FETs,” TED, Feb 2014 K. K. Hung, et al., “A physics-based MOSFET noise model for circuit simulators,” TED, May 1990.



Slide 13

Tunnel FET Flicker Noise (interface traps)

TFET flicker noise highly depends on the spreading of the tunneled carriers in the channel (L’), which is independent of the channel-length (Lg)

0.01 0.1 1 10 1000.0

5.0x10-9

1.0x10-8

1.5x10-8

2.0x10-8

B=1.46x106 V/cm

T=77K

Heteroj-TFET

Homoj-TFETS

id/i

d

2 [

Hz

-1]

IDS

[A/m]

VDS

=0.5V

Measured: Scatter

Analytical Model: Line

B=4x106 V/cm

1 10 100 100010-10

10-9

10-8

10-7

10-6

10-5

10-4

T=77K

Heteroj-TFET

Homoj-TFET

Sid /

i d

2[H

z-1]

Frequency [Hz]

VDS

=0.5V

1/f

T=300KMeasurements

TFET Drain Current Flicker Noise Power

Analytical Model:

Bijesh, R., et al, DRC 2012. Rahul, P., et al, TED 2014.



Slide 14

Overall Electrical Noise: HTFETs vs Si FinFETs

Ref: Rahul, P., et al, TED 2014.

• A larger noise of HTFET at

low ID is due to the smaller tunneling length of carriers.

• HTFET noise reduces faster is due to faster carrier density increase.

• Competitive device noise • Lower input-referred

noise for HTFET with high gains


HTFET Standard Cell Library

Slide 15

Standard Cell Library Design Flow Enables quick evaluation of large-scale digital circuits.

Synthesis

Architecture levelDesigns

TFET Verilog-A models Lookup tables

Modification of design for cells

Spice Simulations

Technology library database (*.db)

Optimization(timing and power)

Generate Power and timing tables

TFET Cell Library

Device: 20nm TFET [1]

Modification of circuit

designs:

Due to uni-directional

conduction of TFET, some

circuits (i.e., MUX, DFF, Etc.)

have been modified to

retain the discharge path.

Behavioral Verilog System Designs

(i.e., Arithmetic logics, Accelerators,

Registers, etc.)

Architecture Evaluation

Existing Core Models

(Ivybridge, UltraSparc)

Architecture Simulation

(Sniper, Gem5, GEMS)

Timing + Power with Wire

Models (McPAT)

System Evaluation

K. Swaminathan et al, DAC2014.


Potential Design Space By TFETs

Slide 16

Ultra Low power

Energy

Harvesting,

Wearable

Computing

Low power/

Embedded

Systems

Mobile/Tablet

Processors

Heterogeneous

multicores

Simple/complex

pipelined processors

Thermal-aware design Domain-specific

accelerators

X

X

-

-

P1

Q1

P2

Q2

+

High Performance

Computing

3D Stacking

Architectural Innovation

Hotspots


preferred corner

• Estimated performance

• Nikonov and Young, IEEE Proc. 2013

• Device simulations 0.09 V

0.2 V

VDD = 0.5 V unless indicated

Digital Benchmarking: Tunnel FET vs. CMOS

Slide 17

Lower delay

than LP

CMOS

Lower

energy than

HP CMOS

D. Nikonov and I. Young, “Overview of beyond-CMOS devices and a uniform methodology for their benchmarking”, Proc. IEEE, 2013


Euclidean Distance Computation

Slide 18

HTFET accelerators outperform a range

of CMOS designs 6X energy reduction over iso-voltage CMOS

design

30% less energy than iso-performance

CMOS design

P1

Q1

P2

Q2

P3

Q3

P4

Q4

P63

Q63

P64

Q64

Ref: K. Swaminathan et al, DATE 2014.


CMOS-TFET Heterogeneous Multicores

Slide 19

Many TFET cores

Few CMOS cores

CMOS has higher peak performance @ high VDD

TFET Processor is “cooler”

Maximize performance using CMOS-TFET heterogeneous multicores

0

0.5

1

1.5

2

applu apsi equake gafort swim wupwise Average

No

rmal

ize

d S

pe

ed

up

Best-Base Hetero-Simple Hetero-DynWork Hetero-AutoBaselineDevice replacement

Dynamic task mapStatic power partition

Dyn. task mapDyn. power partition

K. Swaminathan et al, ISCA 2014.


TFET in 3D Stacked Multicore Systems

Slide 20

0

5

10

15

20

25

30

35

40

No

rmal

ized

Sp

eed

up

Best CMOS perf Best TFET perf

Relative performance of a 64-core CMOS and HTFET 3D stacked

system, normalized to a single core CMOS performance.

18% speedup obtained by using HTFET cores over CMOS cores.

Heterogeneous 3D stacked CMOS-HTFET multicore system can result

in even higher speedups

Peak performance (thermal

and yield constrained)

K. Swaminathan et al, ISCA 2014.


Emerging System Design Using HTFET

Slide 21

Increase the

harvested power

Reduce the power

consumption

(H. Liu et al., ISLPED’13, JETCAS14)


High-Efficiency HTFET Rectifier

Slide 22 H. Liu et al., “Tunnel FET RF rectifier design for energy harvesting applications,” JETCAS 2014

Steep-Slope Features: Lower threshold voltage and resistive loss

Uni-diretional Conduction: Lower leakage current from output to input


High-Efficiency HTFET Switched-Capacitor DC-DC Converter

VOUT

CL RL

Bia

sin

g

CP CP

VIN

Nonoverlapping phase driver

φA φB

Bia

sin

g

X

Y

M1

M2

M3

M4

X

Y

Slide 23

VOUT

VIN

Simplified phase generator

Φ’A Φ’B

X

M1

M2

M3

M4

Φ’A

Φ’B

Steep-Slope Features Lower threshold voltage and resistive loss

Uni-diretional Current Conduction Lower leakage current from output to input

Lower power by simplified phase generator

Novel topology of doubling output gate

control for lower resistive loss

(a) Conventional design (b) Proposed design (c) Efficiency

U. Heo et al., “A high-efficiency switched-capacitance HTFET charge pump for low-input-voltage

applications,” VLSI Design 2015


Low-Noise HTFET Neural Amplifier

Slide 24 H. Liu., et al, ISLPED‘14.

Motivation: Low-Noise Amplifier for Neural Signal Recording

Nurmikko et al. “Listening to Brain Microcircuits for Interfacing With External World”, 2010 IEEE Proceeding.

Key Design Points: High gain Low input-referred noise Low power

Steep-Slope Tunnel FET Neural Amplifier

10-2

10-1

100

101

10-4

10-3

10-2

10-1

100

101

102

103

Si FinFET

Neural

Amplifier

[this work]HTFET

Neural

Amplifier

[6]

[8] [9]

NEF=10S

up

ply

Cu

rren

t [

A]

vin,rms

/BW [Vrms

/Hz]

NEF=1

[4]

[this work]NEF

CMOS,min

[4] UU@JSSC’03 [6] [email protected]’12 [8] EPFL@EMBC’12 [9] [email protected]’07


Low-Power HTFET SAR ADC

Slide 25

0 10 20 30 40 50 60 70 80 90 100 11010

0

102

104

106

108

1010

1012

1014

Noise Limit

EClass_A ADCs 2009-2013

ADCs 2004-2008

ADCs 1999-2003

En

erg

y [

kT

]

SNDR [dB]

A/D Converter Survey Data

Emin

Technology Limit

HTFET Enables Energy Reduction

28 30 32 34 36 38 4010

4

105

106

107

108

0.50 V0.40 V

0.30 V

0.50V

0.40V0.30V HTFET ADC

Si FinFET ADCE

nerg

y [

kT

]

SNDR [dB]

EClass-AEmin

Comparator

CLK

VDD

External CLK

6bit Successive

Approximation Register

6bit

6bit BinaryBinary Decoder

Analog Input

6bit

VREF

VREF

fc

MUX

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFETHTFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFETSi FinFET

100 200 300 400

27

30

33

SN

DR

[d

B]

Input Frequencies [kHz]

100 200 300 400

4.0

4.5

5.0

5.5

EN

OB

s [

bit

]


0.30 0.40 0.504.0

4.5

5.0

5.5

EN

OB

s [

bit

]

Supply Voltages [V]

0.30 0.40 0.500

2

4

6

Fo

M

[fJ/c

on

vers

ion

-ste

p]

Supply Voltages [V]

HTFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFETHTFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFETSi FinFET

100 200 300 400

27

30

33

SN

DR

[d

B]


100 200 300 400

4.0

4.5

5.0

5.5

EN

OB

s [

bit

]


0.30 0.40 0.504.0

4.5

5.0

5.5

EN

OB

s [

bit

]

Supply Voltages [V]

0.30 0.40 0.500

2

4

6

Fo

M

[fJ/c

on

vers

ion

-ste

p]

Supply Voltages [V]

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFETHTFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFET

0.3 0.4 0.54

5

6

7

8

EN

OB

s [

bit

]

Supply Voltages [V]

Ideal HTFET

HTFET

Ideal Si FinFET

Si FinFETSi FinFET

100 200 300 400

27

30

33

SN

DR

[d

B]


100 200 300 400

4.0

4.5

5.0

5.5

EN

OB

s [

bit

]


0.30 0.40 0.504.0

4.5

5.0

5.5

EN

OB

s [

bit

]

Supply Voltages [V]

0.30 0.40 0.500

2

4

6

Fo

M

[fJ/c

on

vers

ion

-ste

p]

Supply Voltages [V]

Si FinFET

M. Kim., et al, TED 2014

SAR:

most

digitized


Summary

Slide 26

Promising “Beyond-CMOS” candidate Technology scaling has forced us to plan for the Post-CMOS era

HTFET can complement, or replace CMOS enabling new design spaces

Key devices features Steep-slope switching, Uni-directional current conduction,

High small-signal RO in saturation, high gm/Ids, high fT at low current,

Negative differential resistance (NDR), Competitive noise performance

Parallelism and 3D design further improves performance

Beneficial device features in analog/RF circuits design

Future work Device fabrication, modeling, circuit & system design and evaluations

Energy harvesting

Power management

Rectifier

DC-DC converter

A/D converter

Amplifier

Current-mode logic

RF transceiver


Thanks

Q&A

Contact Info

Xueqing Li: [email protected]

Vijaykrishnan Narayanan: [email protected]

Suman Datta: [email protected]

Huichu Liu: [email protected]

Moon Seok Kim: [email protected]

Karthik Swaminathan: [email protected]

Enabling Power-Efficient Designs With III-V Heterojunction Tunnel...

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